1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 #[doc = "0x00 - System Control Register"]
5 pub ctrl: crate::Reg<ctrl::CTRL_SPEC>,
6 #[doc = "0x04 - System Status Register"]
7 pub status: crate::Reg<status::STATUS_SPEC>,
8 #[doc = "0x08 - Interrupt Flag Register"]
9 pub if_: crate::Reg<if_::IF_SPEC>,
10 #[doc = "0x0c - Interrupt Flag Set Register"]
11 pub ifs: crate::Reg<ifs::IFS_SPEC>,
12 #[doc = "0x10 - Interrupt Flag Clear Register"]
13 pub ifc: crate::Reg<ifc::IFC_SPEC>,
14 #[doc = "0x14 - Interrupt Enable Register"]
15 pub ien: crate::Reg<ien::IEN_SPEC>,
16 #[doc = "0x18 - I/O Routing Register"]
17 pub route: crate::Reg<route::ROUTE_SPEC>,
18 _reserved7: [u8; 0x10],
19 #[doc = "0x2c - Charger Detect Configuration Register"]
20 pub cdconf: crate::Reg<cdconf::CDCONF_SPEC>,
21 #[doc = "0x30 - Command Register"]
22 pub cmd: crate::Reg<cmd::CMD_SPEC>,
23 #[doc = "0x34 - Data TRIM 1 Values for USB DP and DM"]
24 pub dattrim1: crate::Reg<dattrim1::DATTRIM1_SPEC>,
25 _reserved10: [u8; 0x04],
26 #[doc = "0x3c - USB LEM Control Register"]
27 pub lemctrl: crate::Reg<lemctrl::LEMCTRL_SPEC>,
28 _reserved11: [u8; 0x000d_dfc0],
29 #[doc = "0xde000 - OTG Control and Status Register"]
30 pub gotgctl: crate::Reg<gotgctl::GOTGCTL_SPEC>,
31 #[doc = "0xde004 - OTG Interrupt Register"]
32 pub gotgint: crate::Reg<gotgint::GOTGINT_SPEC>,
33 #[doc = "0xde008 - AHB Configuration Register"]
34 pub gahbcfg: crate::Reg<gahbcfg::GAHBCFG_SPEC>,
35 #[doc = "0xde00c - USB Configuration Register"]
36 pub gusbcfg: crate::Reg<gusbcfg::GUSBCFG_SPEC>,
37 #[doc = "0xde010 - Reset Register"]
38 pub grstctl: crate::Reg<grstctl::GRSTCTL_SPEC>,
39 #[doc = "0xde014 - Interrupt Register"]
40 pub gintsts: crate::Reg<gintsts::GINTSTS_SPEC>,
41 #[doc = "0xde018 - Interrupt Mask Register"]
42 pub gintmsk: crate::Reg<gintmsk::GINTMSK_SPEC>,
43 #[doc = "0xde01c - Receive Status Debug Read Register"]
44 pub grxstsr: crate::Reg<grxstsr::GRXSTSR_SPEC>,
45 #[doc = "0xde020 - Receive Status Read /Pop Register"]
46 pub grxstsp: crate::Reg<grxstsp::GRXSTSP_SPEC>,
47 #[doc = "0xde024 - Receive FIFO Size Register"]
48 pub grxfsiz: crate::Reg<grxfsiz::GRXFSIZ_SPEC>,
49 #[doc = "0xde028 - Non-periodic Transmit FIFO Size Register"]
50 pub gnptxfsiz: crate::Reg<gnptxfsiz::GNPTXFSIZ_SPEC>,
51 #[doc = "0xde02c - Non-periodic Transmit FIFO/Queue Status Register"]
52 pub gnptxsts: crate::Reg<gnptxsts::GNPTXSTS_SPEC>,
53 _reserved23: [u8; 0x10],
54 #[doc = "0xde040 - Synopsys ID Register"]
55 pub gsnpsid: crate::Reg<gsnpsid::GSNPSID_SPEC>,
56 _reserved24: [u8; 0x18],
57 #[doc = "0xde05c - Global DFIFO Configuration Register"]
58 pub gdfifocfg: crate::Reg<gdfifocfg::GDFIFOCFG_SPEC>,
59 _reserved25: [u8; 0xa0],
60 #[doc = "0xde100 - Host Periodic Transmit FIFO Size Register"]
61 pub hptxfsiz: crate::Reg<hptxfsiz::HPTXFSIZ_SPEC>,
62 #[doc = "0xde104 - Device IN Endpoint Transmit FIFO Size Register 1"]
63 pub dieptxf1: crate::Reg<dieptxf1::DIEPTXF1_SPEC>,
64 #[doc = "0xde108 - Device IN Endpoint Transmit FIFO Size Register 2"]
65 pub dieptxf2: crate::Reg<dieptxf2::DIEPTXF2_SPEC>,
66 #[doc = "0xde10c - Device IN Endpoint Transmit FIFO Size Register 3"]
67 pub dieptxf3: crate::Reg<dieptxf3::DIEPTXF3_SPEC>,
68 #[doc = "0xde110 - Device IN Endpoint Transmit FIFO Size Register 4"]
69 pub dieptxf4: crate::Reg<dieptxf4::DIEPTXF4_SPEC>,
70 #[doc = "0xde114 - Device IN Endpoint Transmit FIFO Size Register 5"]
71 pub dieptxf5: crate::Reg<dieptxf5::DIEPTXF5_SPEC>,
72 #[doc = "0xde118 - Device IN Endpoint Transmit FIFO Size Register 6"]
73 pub dieptxf6: crate::Reg<dieptxf6::DIEPTXF6_SPEC>,
74 _reserved32: [u8; 0x02e4],
75 #[doc = "0xde400 - Host Configuration Register"]
76 pub hcfg: crate::Reg<hcfg::HCFG_SPEC>,
77 #[doc = "0xde404 - Host Frame Interval Register"]
78 pub hfir: crate::Reg<hfir::HFIR_SPEC>,
79 #[doc = "0xde408 - Host Frame Number/Frame Time Remaining Register"]
80 pub hfnum: crate::Reg<hfnum::HFNUM_SPEC>,
81 _reserved35: [u8; 0x04],
82 #[doc = "0xde410 - Host Periodic Transmit FIFO/Queue Status Register"]
83 pub hptxsts: crate::Reg<hptxsts::HPTXSTS_SPEC>,
84 #[doc = "0xde414 - Host All Channels Interrupt Register"]
85 pub haint: crate::Reg<haint::HAINT_SPEC>,
86 #[doc = "0xde418 - Host All Channels Interrupt Mask Register"]
87 pub haintmsk: crate::Reg<haintmsk::HAINTMSK_SPEC>,
88 _reserved38: [u8; 0x24],
89 #[doc = "0xde440 - Host Port Control and Status Register"]
90 pub hprt: crate::Reg<hprt::HPRT_SPEC>,
91 _reserved39: [u8; 0xbc],
92 #[doc = "0xde500 - Host Channel x Characteristics Register"]
93 pub hc0_char: crate::Reg<hc0_char::HC0_CHAR_SPEC>,
94 #[doc = "0xde504 - Host Channel x Split Control Register"]
95 pub hc0_splt: crate::Reg<hc0_splt::HC0_SPLT_SPEC>,
96 #[doc = "0xde508 - Host Channel x Interrupt Register"]
97 pub hc0_int: crate::Reg<hc0_int::HC0_INT_SPEC>,
98 #[doc = "0xde50c - Host Channel x Interrupt Mask Register"]
99 pub hc0_intmsk: crate::Reg<hc0_intmsk::HC0_INTMSK_SPEC>,
100 #[doc = "0xde510 - Host Channel x Transfer Size Register"]
101 pub hc0_tsiz: crate::Reg<hc0_tsiz::HC0_TSIZ_SPEC>,
102 #[doc = "0xde514 - Host Channel x DMA Address Register"]
103 pub hc0_dmaaddr: crate::Reg<hc0_dmaaddr::HC0_DMAADDR_SPEC>,
104 _reserved45: [u8; 0x08],
105 #[doc = "0xde520 - Host Channel x Characteristics Register"]
106 pub hc1_char: crate::Reg<hc1_char::HC1_CHAR_SPEC>,
107 #[doc = "0xde524 - Host Channel x Split Control Register"]
108 pub hc1_splt: crate::Reg<hc1_splt::HC1_SPLT_SPEC>,
109 #[doc = "0xde528 - Host Channel x Interrupt Register"]
110 pub hc1_int: crate::Reg<hc1_int::HC1_INT_SPEC>,
111 #[doc = "0xde52c - Host Channel x Interrupt Mask Register"]
112 pub hc1_intmsk: crate::Reg<hc1_intmsk::HC1_INTMSK_SPEC>,
113 #[doc = "0xde530 - Host Channel x Transfer Size Register"]
114 pub hc1_tsiz: crate::Reg<hc1_tsiz::HC1_TSIZ_SPEC>,
115 #[doc = "0xde534 - Host Channel x DMA Address Register"]
116 pub hc1_dmaaddr: crate::Reg<hc1_dmaaddr::HC1_DMAADDR_SPEC>,
117 _reserved51: [u8; 0x08],
118 #[doc = "0xde540 - Host Channel x Characteristics Register"]
119 pub hc2_char: crate::Reg<hc2_char::HC2_CHAR_SPEC>,
120 #[doc = "0xde544 - Host Channel x Split Control Register"]
121 pub hc2_splt: crate::Reg<hc2_splt::HC2_SPLT_SPEC>,
122 #[doc = "0xde548 - Host Channel x Interrupt Register"]
123 pub hc2_int: crate::Reg<hc2_int::HC2_INT_SPEC>,
124 #[doc = "0xde54c - Host Channel x Interrupt Mask Register"]
125 pub hc2_intmsk: crate::Reg<hc2_intmsk::HC2_INTMSK_SPEC>,
126 #[doc = "0xde550 - Host Channel x Transfer Size Register"]
127 pub hc2_tsiz: crate::Reg<hc2_tsiz::HC2_TSIZ_SPEC>,
128 #[doc = "0xde554 - Host Channel x DMA Address Register"]
129 pub hc2_dmaaddr: crate::Reg<hc2_dmaaddr::HC2_DMAADDR_SPEC>,
130 _reserved57: [u8; 0x08],
131 #[doc = "0xde560 - Host Channel x Characteristics Register"]
132 pub hc3_char: crate::Reg<hc3_char::HC3_CHAR_SPEC>,
133 #[doc = "0xde564 - Host Channel x Split Control Register"]
134 pub hc3_splt: crate::Reg<hc3_splt::HC3_SPLT_SPEC>,
135 #[doc = "0xde568 - Host Channel x Interrupt Register"]
136 pub hc3_int: crate::Reg<hc3_int::HC3_INT_SPEC>,
137 #[doc = "0xde56c - Host Channel x Interrupt Mask Register"]
138 pub hc3_intmsk: crate::Reg<hc3_intmsk::HC3_INTMSK_SPEC>,
139 #[doc = "0xde570 - Host Channel x Transfer Size Register"]
140 pub hc3_tsiz: crate::Reg<hc3_tsiz::HC3_TSIZ_SPEC>,
141 #[doc = "0xde574 - Host Channel x DMA Address Register"]
142 pub hc3_dmaaddr: crate::Reg<hc3_dmaaddr::HC3_DMAADDR_SPEC>,
143 _reserved63: [u8; 0x08],
144 #[doc = "0xde580 - Host Channel x Characteristics Register"]
145 pub hc4_char: crate::Reg<hc4_char::HC4_CHAR_SPEC>,
146 #[doc = "0xde584 - Host Channel x Split Control Register"]
147 pub hc4_splt: crate::Reg<hc4_splt::HC4_SPLT_SPEC>,
148 #[doc = "0xde588 - Host Channel x Interrupt Register"]
149 pub hc4_int: crate::Reg<hc4_int::HC4_INT_SPEC>,
150 #[doc = "0xde58c - Host Channel x Interrupt Mask Register"]
151 pub hc4_intmsk: crate::Reg<hc4_intmsk::HC4_INTMSK_SPEC>,
152 #[doc = "0xde590 - Host Channel x Transfer Size Register"]
153 pub hc4_tsiz: crate::Reg<hc4_tsiz::HC4_TSIZ_SPEC>,
154 #[doc = "0xde594 - Host Channel x DMA Address Register"]
155 pub hc4_dmaaddr: crate::Reg<hc4_dmaaddr::HC4_DMAADDR_SPEC>,
156 _reserved69: [u8; 0x08],
157 #[doc = "0xde5a0 - Host Channel x Characteristics Register"]
158 pub hc5_char: crate::Reg<hc5_char::HC5_CHAR_SPEC>,
159 #[doc = "0xde5a4 - Host Channel x Split Control Register"]
160 pub hc5_splt: crate::Reg<hc5_splt::HC5_SPLT_SPEC>,
161 #[doc = "0xde5a8 - Host Channel x Interrupt Register"]
162 pub hc5_int: crate::Reg<hc5_int::HC5_INT_SPEC>,
163 #[doc = "0xde5ac - Host Channel x Interrupt Mask Register"]
164 pub hc5_intmsk: crate::Reg<hc5_intmsk::HC5_INTMSK_SPEC>,
165 #[doc = "0xde5b0 - Host Channel x Transfer Size Register"]
166 pub hc5_tsiz: crate::Reg<hc5_tsiz::HC5_TSIZ_SPEC>,
167 #[doc = "0xde5b4 - Host Channel x DMA Address Register"]
168 pub hc5_dmaaddr: crate::Reg<hc5_dmaaddr::HC5_DMAADDR_SPEC>,
169 _reserved75: [u8; 0x08],
170 #[doc = "0xde5c0 - Host Channel x Characteristics Register"]
171 pub hc6_char: crate::Reg<hc6_char::HC6_CHAR_SPEC>,
172 #[doc = "0xde5c4 - Host Channel x Split Control Register"]
173 pub hc6_splt: crate::Reg<hc6_splt::HC6_SPLT_SPEC>,
174 #[doc = "0xde5c8 - Host Channel x Interrupt Register"]
175 pub hc6_int: crate::Reg<hc6_int::HC6_INT_SPEC>,
176 #[doc = "0xde5cc - Host Channel x Interrupt Mask Register"]
177 pub hc6_intmsk: crate::Reg<hc6_intmsk::HC6_INTMSK_SPEC>,
178 #[doc = "0xde5d0 - Host Channel x Transfer Size Register"]
179 pub hc6_tsiz: crate::Reg<hc6_tsiz::HC6_TSIZ_SPEC>,
180 #[doc = "0xde5d4 - Host Channel x DMA Address Register"]
181 pub hc6_dmaaddr: crate::Reg<hc6_dmaaddr::HC6_DMAADDR_SPEC>,
182 _reserved81: [u8; 0x08],
183 #[doc = "0xde5e0 - Host Channel x Characteristics Register"]
184 pub hc7_char: crate::Reg<hc7_char::HC7_CHAR_SPEC>,
185 #[doc = "0xde5e4 - Host Channel x Split Control Register"]
186 pub hc7_splt: crate::Reg<hc7_splt::HC7_SPLT_SPEC>,
187 #[doc = "0xde5e8 - Host Channel x Interrupt Register"]
188 pub hc7_int: crate::Reg<hc7_int::HC7_INT_SPEC>,
189 #[doc = "0xde5ec - Host Channel x Interrupt Mask Register"]
190 pub hc7_intmsk: crate::Reg<hc7_intmsk::HC7_INTMSK_SPEC>,
191 #[doc = "0xde5f0 - Host Channel x Transfer Size Register"]
192 pub hc7_tsiz: crate::Reg<hc7_tsiz::HC7_TSIZ_SPEC>,
193 #[doc = "0xde5f4 - Host Channel x DMA Address Register"]
194 pub hc7_dmaaddr: crate::Reg<hc7_dmaaddr::HC7_DMAADDR_SPEC>,
195 _reserved87: [u8; 0x08],
196 #[doc = "0xde600 - Host Channel x Characteristics Register"]
197 pub hc8_char: crate::Reg<hc8_char::HC8_CHAR_SPEC>,
198 #[doc = "0xde604 - Host Channel x Split Control Register"]
199 pub hc8_splt: crate::Reg<hc8_splt::HC8_SPLT_SPEC>,
200 #[doc = "0xde608 - Host Channel x Interrupt Register"]
201 pub hc8_int: crate::Reg<hc8_int::HC8_INT_SPEC>,
202 #[doc = "0xde60c - Host Channel x Interrupt Mask Register"]
203 pub hc8_intmsk: crate::Reg<hc8_intmsk::HC8_INTMSK_SPEC>,
204 #[doc = "0xde610 - Host Channel x Transfer Size Register"]
205 pub hc8_tsiz: crate::Reg<hc8_tsiz::HC8_TSIZ_SPEC>,
206 #[doc = "0xde614 - Host Channel x DMA Address Register"]
207 pub hc8_dmaaddr: crate::Reg<hc8_dmaaddr::HC8_DMAADDR_SPEC>,
208 _reserved93: [u8; 0x08],
209 #[doc = "0xde620 - Host Channel x Characteristics Register"]
210 pub hc9_char: crate::Reg<hc9_char::HC9_CHAR_SPEC>,
211 #[doc = "0xde624 - Host Channel x Split Control Register"]
212 pub hc9_splt: crate::Reg<hc9_splt::HC9_SPLT_SPEC>,
213 #[doc = "0xde628 - Host Channel x Interrupt Register"]
214 pub hc9_int: crate::Reg<hc9_int::HC9_INT_SPEC>,
215 #[doc = "0xde62c - Host Channel x Interrupt Mask Register"]
216 pub hc9_intmsk: crate::Reg<hc9_intmsk::HC9_INTMSK_SPEC>,
217 #[doc = "0xde630 - Host Channel x Transfer Size Register"]
218 pub hc9_tsiz: crate::Reg<hc9_tsiz::HC9_TSIZ_SPEC>,
219 #[doc = "0xde634 - Host Channel x DMA Address Register"]
220 pub hc9_dmaaddr: crate::Reg<hc9_dmaaddr::HC9_DMAADDR_SPEC>,
221 _reserved99: [u8; 0x08],
222 #[doc = "0xde640 - Host Channel x Characteristics Register"]
223 pub hc10_char: crate::Reg<hc10_char::HC10_CHAR_SPEC>,
224 #[doc = "0xde644 - Host Channel x Split Control Register"]
225 pub hc10_splt: crate::Reg<hc10_splt::HC10_SPLT_SPEC>,
226 #[doc = "0xde648 - Host Channel x Interrupt Register"]
227 pub hc10_int: crate::Reg<hc10_int::HC10_INT_SPEC>,
228 #[doc = "0xde64c - Host Channel x Interrupt Mask Register"]
229 pub hc10_intmsk: crate::Reg<hc10_intmsk::HC10_INTMSK_SPEC>,
230 #[doc = "0xde650 - Host Channel x Transfer Size Register"]
231 pub hc10_tsiz: crate::Reg<hc10_tsiz::HC10_TSIZ_SPEC>,
232 #[doc = "0xde654 - Host Channel x DMA Address Register"]
233 pub hc10_dmaaddr: crate::Reg<hc10_dmaaddr::HC10_DMAADDR_SPEC>,
234 _reserved105: [u8; 0x08],
235 #[doc = "0xde660 - Host Channel x Characteristics Register"]
236 pub hc11_char: crate::Reg<hc11_char::HC11_CHAR_SPEC>,
237 #[doc = "0xde664 - Host Channel x Split Control Register"]
238 pub hc11_splt: crate::Reg<hc11_splt::HC11_SPLT_SPEC>,
239 #[doc = "0xde668 - Host Channel x Interrupt Register"]
240 pub hc11_int: crate::Reg<hc11_int::HC11_INT_SPEC>,
241 #[doc = "0xde66c - Host Channel x Interrupt Mask Register"]
242 pub hc11_intmsk: crate::Reg<hc11_intmsk::HC11_INTMSK_SPEC>,
243 #[doc = "0xde670 - Host Channel x Transfer Size Register"]
244 pub hc11_tsiz: crate::Reg<hc11_tsiz::HC11_TSIZ_SPEC>,
245 #[doc = "0xde674 - Host Channel x DMA Address Register"]
246 pub hc11_dmaaddr: crate::Reg<hc11_dmaaddr::HC11_DMAADDR_SPEC>,
247 _reserved111: [u8; 0x08],
248 #[doc = "0xde680 - Host Channel x Characteristics Register"]
249 pub hc12_char: crate::Reg<hc12_char::HC12_CHAR_SPEC>,
250 #[doc = "0xde684 - Host Channel x Split Control Register"]
251 pub hc12_splt: crate::Reg<hc12_splt::HC12_SPLT_SPEC>,
252 #[doc = "0xde688 - Host Channel x Interrupt Register"]
253 pub hc12_int: crate::Reg<hc12_int::HC12_INT_SPEC>,
254 #[doc = "0xde68c - Host Channel x Interrupt Mask Register"]
255 pub hc12_intmsk: crate::Reg<hc12_intmsk::HC12_INTMSK_SPEC>,
256 #[doc = "0xde690 - Host Channel x Transfer Size Register"]
257 pub hc12_tsiz: crate::Reg<hc12_tsiz::HC12_TSIZ_SPEC>,
258 #[doc = "0xde694 - Host Channel x DMA Address Register"]
259 pub hc12_dmaaddr: crate::Reg<hc12_dmaaddr::HC12_DMAADDR_SPEC>,
260 _reserved117: [u8; 0x08],
261 #[doc = "0xde6a0 - Host Channel x Characteristics Register"]
262 pub hc13_char: crate::Reg<hc13_char::HC13_CHAR_SPEC>,
263 #[doc = "0xde6a4 - Host Channel x Split Control Register"]
264 pub hc13_splt: crate::Reg<hc13_splt::HC13_SPLT_SPEC>,
265 #[doc = "0xde6a8 - Host Channel x Interrupt Register"]
266 pub hc13_int: crate::Reg<hc13_int::HC13_INT_SPEC>,
267 #[doc = "0xde6ac - Host Channel x Interrupt Mask Register"]
268 pub hc13_intmsk: crate::Reg<hc13_intmsk::HC13_INTMSK_SPEC>,
269 #[doc = "0xde6b0 - Host Channel x Transfer Size Register"]
270 pub hc13_tsiz: crate::Reg<hc13_tsiz::HC13_TSIZ_SPEC>,
271 #[doc = "0xde6b4 - Host Channel x DMA Address Register"]
272 pub hc13_dmaaddr: crate::Reg<hc13_dmaaddr::HC13_DMAADDR_SPEC>,
273 _reserved123: [u8; 0x0148],
274 #[doc = "0xde800 - Device Configuration Register"]
275 pub dcfg: crate::Reg<dcfg::DCFG_SPEC>,
276 #[doc = "0xde804 - Device Control Register"]
277 pub dctl: crate::Reg<dctl::DCTL_SPEC>,
278 #[doc = "0xde808 - Device Status Register"]
279 pub dsts: crate::Reg<dsts::DSTS_SPEC>,
280 _reserved126: [u8; 0x04],
281 #[doc = "0xde810 - Device IN Endpoint Common Interrupt Mask Register"]
282 pub diepmsk: crate::Reg<diepmsk::DIEPMSK_SPEC>,
283 #[doc = "0xde814 - Device OUT Endpoint Common Interrupt Mask Register"]
284 pub doepmsk: crate::Reg<doepmsk::DOEPMSK_SPEC>,
285 #[doc = "0xde818 - Device All Endpoints Interrupt Register"]
286 pub daint: crate::Reg<daint::DAINT_SPEC>,
287 #[doc = "0xde81c - Device All Endpoints Interrupt Mask Register"]
288 pub daintmsk: crate::Reg<daintmsk::DAINTMSK_SPEC>,
289 _reserved130: [u8; 0x08],
290 #[doc = "0xde828 - Device VBUS Discharge Time Register"]
291 pub dvbusdis: crate::Reg<dvbusdis::DVBUSDIS_SPEC>,
292 #[doc = "0xde82c - Device VBUS Pulsing Time Register"]
293 pub dvbuspulse: crate::Reg<dvbuspulse::DVBUSPULSE_SPEC>,
294 #[doc = "0xde830 - Device Threshold Control Register"]
295 pub dthrctl: crate::Reg<dthrctl::DTHRCTL_SPEC>,
296 #[doc = "0xde834 - Device IN Endpoint FIFO Empty Interrupt Mask Register"]
297 pub diepempmsk: crate::Reg<diepempmsk::DIEPEMPMSK_SPEC>,
298 _reserved134: [u8; 0xc8],
299 #[doc = "0xde900 - Device Control IN Endpoint 0 Control Register"]
300 pub diep0ctl: crate::Reg<diep0ctl::DIEP0CTL_SPEC>,
301 _reserved135: [u8; 0x04],
302 #[doc = "0xde908 - Device IN Endpoint 0 Interrupt Register"]
303 pub diep0int: crate::Reg<diep0int::DIEP0INT_SPEC>,
304 _reserved136: [u8; 0x04],
305 #[doc = "0xde910 - Device IN Endpoint 0 Transfer Size Register"]
306 pub diep0tsiz: crate::Reg<diep0tsiz::DIEP0TSIZ_SPEC>,
307 #[doc = "0xde914 - Device IN Endpoint 0 DMA Address Register"]
308 pub diep0dmaaddr: crate::Reg<diep0dmaaddr::DIEP0DMAADDR_SPEC>,
309 #[doc = "0xde918 - Device IN Endpoint Transmit FIFO Status Register 0"]
310 pub diep0txfsts: crate::Reg<diep0txfsts::DIEP0TXFSTS_SPEC>,
311 _reserved139: [u8; 0x04],
312 #[doc = "0xde920 - Device Control IN Endpoint x+1 Control Register"]
313 pub diep0_ctl: crate::Reg<diep0_ctl::DIEP0_CTL_SPEC>,
314 _reserved140: [u8; 0x04],
315 #[doc = "0xde928 - Device IN Endpoint x+1 Interrupt Register"]
316 pub diep0_int: crate::Reg<diep0_int::DIEP0_INT_SPEC>,
317 _reserved141: [u8; 0x04],
318 #[doc = "0xde930 - Device IN Endpoint x+1 Transfer Size Register"]
319 pub diep0_tsiz: crate::Reg<diep0_tsiz::DIEP0_TSIZ_SPEC>,
320 #[doc = "0xde934 - Device IN Endpoint x+1 DMA Address Register"]
321 pub diep0_dmaaddr: crate::Reg<diep0_dmaaddr::DIEP0_DMAADDR_SPEC>,
322 #[doc = "0xde938 - Device IN Endpoint Transmit FIFO Status Register 1"]
323 pub diep0_dtxfsts: crate::Reg<diep0_dtxfsts::DIEP0_DTXFSTS_SPEC>,
324 _reserved144: [u8; 0x04],
325 #[doc = "0xde940 - Device Control IN Endpoint x+1 Control Register"]
326 pub diep1_ctl: crate::Reg<diep1_ctl::DIEP1_CTL_SPEC>,
327 _reserved145: [u8; 0x04],
328 #[doc = "0xde948 - Device IN Endpoint x+1 Interrupt Register"]
329 pub diep1_int: crate::Reg<diep1_int::DIEP1_INT_SPEC>,
330 _reserved146: [u8; 0x04],
331 #[doc = "0xde950 - Device IN Endpoint x+1 Transfer Size Register"]
332 pub diep1_tsiz: crate::Reg<diep1_tsiz::DIEP1_TSIZ_SPEC>,
333 #[doc = "0xde954 - Device IN Endpoint x+1 DMA Address Register"]
334 pub diep1_dmaaddr: crate::Reg<diep1_dmaaddr::DIEP1_DMAADDR_SPEC>,
335 #[doc = "0xde958 - Device IN Endpoint Transmit FIFO Status Register 1"]
336 pub diep1_dtxfsts: crate::Reg<diep1_dtxfsts::DIEP1_DTXFSTS_SPEC>,
337 _reserved149: [u8; 0x04],
338 #[doc = "0xde960 - Device Control IN Endpoint x+1 Control Register"]
339 pub diep2_ctl: crate::Reg<diep2_ctl::DIEP2_CTL_SPEC>,
340 _reserved150: [u8; 0x04],
341 #[doc = "0xde968 - Device IN Endpoint x+1 Interrupt Register"]
342 pub diep2_int: crate::Reg<diep2_int::DIEP2_INT_SPEC>,
343 _reserved151: [u8; 0x04],
344 #[doc = "0xde970 - Device IN Endpoint x+1 Transfer Size Register"]
345 pub diep2_tsiz: crate::Reg<diep2_tsiz::DIEP2_TSIZ_SPEC>,
346 #[doc = "0xde974 - Device IN Endpoint x+1 DMA Address Register"]
347 pub diep2_dmaaddr: crate::Reg<diep2_dmaaddr::DIEP2_DMAADDR_SPEC>,
348 #[doc = "0xde978 - Device IN Endpoint Transmit FIFO Status Register 1"]
349 pub diep2_dtxfsts: crate::Reg<diep2_dtxfsts::DIEP2_DTXFSTS_SPEC>,
350 _reserved154: [u8; 0x04],
351 #[doc = "0xde980 - Device Control IN Endpoint x+1 Control Register"]
352 pub diep3_ctl: crate::Reg<diep3_ctl::DIEP3_CTL_SPEC>,
353 _reserved155: [u8; 0x04],
354 #[doc = "0xde988 - Device IN Endpoint x+1 Interrupt Register"]
355 pub diep3_int: crate::Reg<diep3_int::DIEP3_INT_SPEC>,
356 _reserved156: [u8; 0x04],
357 #[doc = "0xde990 - Device IN Endpoint x+1 Transfer Size Register"]
358 pub diep3_tsiz: crate::Reg<diep3_tsiz::DIEP3_TSIZ_SPEC>,
359 #[doc = "0xde994 - Device IN Endpoint x+1 DMA Address Register"]
360 pub diep3_dmaaddr: crate::Reg<diep3_dmaaddr::DIEP3_DMAADDR_SPEC>,
361 #[doc = "0xde998 - Device IN Endpoint Transmit FIFO Status Register 1"]
362 pub diep3_dtxfsts: crate::Reg<diep3_dtxfsts::DIEP3_DTXFSTS_SPEC>,
363 _reserved159: [u8; 0x04],
364 #[doc = "0xde9a0 - Device Control IN Endpoint x+1 Control Register"]
365 pub diep4_ctl: crate::Reg<diep4_ctl::DIEP4_CTL_SPEC>,
366 _reserved160: [u8; 0x04],
367 #[doc = "0xde9a8 - Device IN Endpoint x+1 Interrupt Register"]
368 pub diep4_int: crate::Reg<diep4_int::DIEP4_INT_SPEC>,
369 _reserved161: [u8; 0x04],
370 #[doc = "0xde9b0 - Device IN Endpoint x+1 Transfer Size Register"]
371 pub diep4_tsiz: crate::Reg<diep4_tsiz::DIEP4_TSIZ_SPEC>,
372 #[doc = "0xde9b4 - Device IN Endpoint x+1 DMA Address Register"]
373 pub diep4_dmaaddr: crate::Reg<diep4_dmaaddr::DIEP4_DMAADDR_SPEC>,
374 #[doc = "0xde9b8 - Device IN Endpoint Transmit FIFO Status Register 1"]
375 pub diep4_dtxfsts: crate::Reg<diep4_dtxfsts::DIEP4_DTXFSTS_SPEC>,
376 _reserved164: [u8; 0x04],
377 #[doc = "0xde9c0 - Device Control IN Endpoint x+1 Control Register"]
378 pub diep5_ctl: crate::Reg<diep5_ctl::DIEP5_CTL_SPEC>,
379 _reserved165: [u8; 0x04],
380 #[doc = "0xde9c8 - Device IN Endpoint x+1 Interrupt Register"]
381 pub diep5_int: crate::Reg<diep5_int::DIEP5_INT_SPEC>,
382 _reserved166: [u8; 0x04],
383 #[doc = "0xde9d0 - Device IN Endpoint x+1 Transfer Size Register"]
384 pub diep5_tsiz: crate::Reg<diep5_tsiz::DIEP5_TSIZ_SPEC>,
385 #[doc = "0xde9d4 - Device IN Endpoint x+1 DMA Address Register"]
386 pub diep5_dmaaddr: crate::Reg<diep5_dmaaddr::DIEP5_DMAADDR_SPEC>,
387 #[doc = "0xde9d8 - Device IN Endpoint Transmit FIFO Status Register 1"]
388 pub diep5_dtxfsts: crate::Reg<diep5_dtxfsts::DIEP5_DTXFSTS_SPEC>,
389 _reserved169: [u8; 0x0124],
390 #[doc = "0xdeb00 - Device Control OUT Endpoint 0 Control Register"]
391 pub doep0ctl: crate::Reg<doep0ctl::DOEP0CTL_SPEC>,
392 _reserved170: [u8; 0x04],
393 #[doc = "0xdeb08 - Device OUT Endpoint 0 Interrupt Register"]
394 pub doep0int: crate::Reg<doep0int::DOEP0INT_SPEC>,
395 _reserved171: [u8; 0x04],
396 #[doc = "0xdeb10 - Device OUT Endpoint 0 Transfer Size Register"]
397 pub doep0tsiz: crate::Reg<doep0tsiz::DOEP0TSIZ_SPEC>,
398 #[doc = "0xdeb14 - Device OUT Endpoint 0 DMA Address Register"]
399 pub doep0dmaaddr: crate::Reg<doep0dmaaddr::DOEP0DMAADDR_SPEC>,
400 _reserved173: [u8; 0x08],
401 #[doc = "0xdeb20 - Device Control OUT Endpoint x+1 Control Register"]
402 pub doep0_ctl: crate::Reg<doep0_ctl::DOEP0_CTL_SPEC>,
403 _reserved174: [u8; 0x04],
404 #[doc = "0xdeb28 - Device OUT Endpoint x+1 Interrupt Register"]
405 pub doep0_int: crate::Reg<doep0_int::DOEP0_INT_SPEC>,
406 _reserved175: [u8; 0x04],
407 #[doc = "0xdeb30 - Device OUT Endpoint x+1 Transfer Size Register"]
408 pub doep0_tsiz: crate::Reg<doep0_tsiz::DOEP0_TSIZ_SPEC>,
409 #[doc = "0xdeb34 - Device OUT Endpoint x+1 DMA Address Register"]
410 pub doep0_dmaaddr: crate::Reg<doep0_dmaaddr::DOEP0_DMAADDR_SPEC>,
411 _reserved177: [u8; 0x08],
412 #[doc = "0xdeb40 - Device Control OUT Endpoint x+1 Control Register"]
413 pub doep1_ctl: crate::Reg<doep1_ctl::DOEP1_CTL_SPEC>,
414 _reserved178: [u8; 0x04],
415 #[doc = "0xdeb48 - Device OUT Endpoint x+1 Interrupt Register"]
416 pub doep1_int: crate::Reg<doep1_int::DOEP1_INT_SPEC>,
417 _reserved179: [u8; 0x04],
418 #[doc = "0xdeb50 - Device OUT Endpoint x+1 Transfer Size Register"]
419 pub doep1_tsiz: crate::Reg<doep1_tsiz::DOEP1_TSIZ_SPEC>,
420 #[doc = "0xdeb54 - Device OUT Endpoint x+1 DMA Address Register"]
421 pub doep1_dmaaddr: crate::Reg<doep1_dmaaddr::DOEP1_DMAADDR_SPEC>,
422 _reserved181: [u8; 0x08],
423 #[doc = "0xdeb60 - Device Control OUT Endpoint x+1 Control Register"]
424 pub doep2_ctl: crate::Reg<doep2_ctl::DOEP2_CTL_SPEC>,
425 _reserved182: [u8; 0x04],
426 #[doc = "0xdeb68 - Device OUT Endpoint x+1 Interrupt Register"]
427 pub doep2_int: crate::Reg<doep2_int::DOEP2_INT_SPEC>,
428 _reserved183: [u8; 0x04],
429 #[doc = "0xdeb70 - Device OUT Endpoint x+1 Transfer Size Register"]
430 pub doep2_tsiz: crate::Reg<doep2_tsiz::DOEP2_TSIZ_SPEC>,
431 #[doc = "0xdeb74 - Device OUT Endpoint x+1 DMA Address Register"]
432 pub doep2_dmaaddr: crate::Reg<doep2_dmaaddr::DOEP2_DMAADDR_SPEC>,
433 _reserved185: [u8; 0x08],
434 #[doc = "0xdeb80 - Device Control OUT Endpoint x+1 Control Register"]
435 pub doep3_ctl: crate::Reg<doep3_ctl::DOEP3_CTL_SPEC>,
436 _reserved186: [u8; 0x04],
437 #[doc = "0xdeb88 - Device OUT Endpoint x+1 Interrupt Register"]
438 pub doep3_int: crate::Reg<doep3_int::DOEP3_INT_SPEC>,
439 _reserved187: [u8; 0x04],
440 #[doc = "0xdeb90 - Device OUT Endpoint x+1 Transfer Size Register"]
441 pub doep3_tsiz: crate::Reg<doep3_tsiz::DOEP3_TSIZ_SPEC>,
442 #[doc = "0xdeb94 - Device OUT Endpoint x+1 DMA Address Register"]
443 pub doep3_dmaaddr: crate::Reg<doep3_dmaaddr::DOEP3_DMAADDR_SPEC>,
444 _reserved189: [u8; 0x08],
445 #[doc = "0xdeba0 - Device Control OUT Endpoint x+1 Control Register"]
446 pub doep4_ctl: crate::Reg<doep4_ctl::DOEP4_CTL_SPEC>,
447 _reserved190: [u8; 0x04],
448 #[doc = "0xdeba8 - Device OUT Endpoint x+1 Interrupt Register"]
449 pub doep4_int: crate::Reg<doep4_int::DOEP4_INT_SPEC>,
450 _reserved191: [u8; 0x04],
451 #[doc = "0xdebb0 - Device OUT Endpoint x+1 Transfer Size Register"]
452 pub doep4_tsiz: crate::Reg<doep4_tsiz::DOEP4_TSIZ_SPEC>,
453 #[doc = "0xdebb4 - Device OUT Endpoint x+1 DMA Address Register"]
454 pub doep4_dmaaddr: crate::Reg<doep4_dmaaddr::DOEP4_DMAADDR_SPEC>,
455 _reserved193: [u8; 0x08],
456 #[doc = "0xdebc0 - Device Control OUT Endpoint x+1 Control Register"]
457 pub doep5_ctl: crate::Reg<doep5_ctl::DOEP5_CTL_SPEC>,
458 _reserved194: [u8; 0x04],
459 #[doc = "0xdebc8 - Device OUT Endpoint x+1 Interrupt Register"]
460 pub doep5_int: crate::Reg<doep5_int::DOEP5_INT_SPEC>,
461 _reserved195: [u8; 0x04],
462 #[doc = "0xdebd0 - Device OUT Endpoint x+1 Transfer Size Register"]
463 pub doep5_tsiz: crate::Reg<doep5_tsiz::DOEP5_TSIZ_SPEC>,
464 #[doc = "0xdebd4 - Device OUT Endpoint x+1 DMA Address Register"]
465 pub doep5_dmaaddr: crate::Reg<doep5_dmaaddr::DOEP5_DMAADDR_SPEC>,
466 _reserved197: [u8; 0x0228],
467 #[doc = "0xdee00 - Power and Clock Gating Control Register"]
468 pub pcgcctl: crate::Reg<pcgcctl::PCGCCTL_SPEC>,
469}
470#[doc = "CTRL register accessor: an alias for `Reg<CTRL_SPEC>`"]
471pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
472#[doc = "System Control Register"]
473pub mod ctrl;
474#[doc = "STATUS register accessor: an alias for `Reg<STATUS_SPEC>`"]
475pub type STATUS = crate::Reg<status::STATUS_SPEC>;
476#[doc = "System Status Register"]
477pub mod status;
478#[doc = "IF register accessor: an alias for `Reg<IF_SPEC>`"]
479pub type IF = crate::Reg<if_::IF_SPEC>;
480#[doc = "Interrupt Flag Register"]
481pub mod if_;
482#[doc = "IFS register accessor: an alias for `Reg<IFS_SPEC>`"]
483pub type IFS = crate::Reg<ifs::IFS_SPEC>;
484#[doc = "Interrupt Flag Set Register"]
485pub mod ifs;
486#[doc = "IFC register accessor: an alias for `Reg<IFC_SPEC>`"]
487pub type IFC = crate::Reg<ifc::IFC_SPEC>;
488#[doc = "Interrupt Flag Clear Register"]
489pub mod ifc;
490#[doc = "IEN register accessor: an alias for `Reg<IEN_SPEC>`"]
491pub type IEN = crate::Reg<ien::IEN_SPEC>;
492#[doc = "Interrupt Enable Register"]
493pub mod ien;
494#[doc = "ROUTE register accessor: an alias for `Reg<ROUTE_SPEC>`"]
495pub type ROUTE = crate::Reg<route::ROUTE_SPEC>;
496#[doc = "I/O Routing Register"]
497pub mod route;
498#[doc = "CDCONF register accessor: an alias for `Reg<CDCONF_SPEC>`"]
499pub type CDCONF = crate::Reg<cdconf::CDCONF_SPEC>;
500#[doc = "Charger Detect Configuration Register"]
501pub mod cdconf;
502#[doc = "CMD register accessor: an alias for `Reg<CMD_SPEC>`"]
503pub type CMD = crate::Reg<cmd::CMD_SPEC>;
504#[doc = "Command Register"]
505pub mod cmd;
506#[doc = "DATTRIM1 register accessor: an alias for `Reg<DATTRIM1_SPEC>`"]
507pub type DATTRIM1 = crate::Reg<dattrim1::DATTRIM1_SPEC>;
508#[doc = "Data TRIM 1 Values for USB DP and DM"]
509pub mod dattrim1;
510#[doc = "LEMCTRL register accessor: an alias for `Reg<LEMCTRL_SPEC>`"]
511pub type LEMCTRL = crate::Reg<lemctrl::LEMCTRL_SPEC>;
512#[doc = "USB LEM Control Register"]
513pub mod lemctrl;
514#[doc = "GOTGCTL register accessor: an alias for `Reg<GOTGCTL_SPEC>`"]
515pub type GOTGCTL = crate::Reg<gotgctl::GOTGCTL_SPEC>;
516#[doc = "OTG Control and Status Register"]
517pub mod gotgctl;
518#[doc = "GOTGINT register accessor: an alias for `Reg<GOTGINT_SPEC>`"]
519pub type GOTGINT = crate::Reg<gotgint::GOTGINT_SPEC>;
520#[doc = "OTG Interrupt Register"]
521pub mod gotgint;
522#[doc = "GAHBCFG register accessor: an alias for `Reg<GAHBCFG_SPEC>`"]
523pub type GAHBCFG = crate::Reg<gahbcfg::GAHBCFG_SPEC>;
524#[doc = "AHB Configuration Register"]
525pub mod gahbcfg;
526#[doc = "GUSBCFG register accessor: an alias for `Reg<GUSBCFG_SPEC>`"]
527pub type GUSBCFG = crate::Reg<gusbcfg::GUSBCFG_SPEC>;
528#[doc = "USB Configuration Register"]
529pub mod gusbcfg;
530#[doc = "GRSTCTL register accessor: an alias for `Reg<GRSTCTL_SPEC>`"]
531pub type GRSTCTL = crate::Reg<grstctl::GRSTCTL_SPEC>;
532#[doc = "Reset Register"]
533pub mod grstctl;
534#[doc = "GINTSTS register accessor: an alias for `Reg<GINTSTS_SPEC>`"]
535pub type GINTSTS = crate::Reg<gintsts::GINTSTS_SPEC>;
536#[doc = "Interrupt Register"]
537pub mod gintsts;
538#[doc = "GINTMSK register accessor: an alias for `Reg<GINTMSK_SPEC>`"]
539pub type GINTMSK = crate::Reg<gintmsk::GINTMSK_SPEC>;
540#[doc = "Interrupt Mask Register"]
541pub mod gintmsk;
542#[doc = "GRXSTSR register accessor: an alias for `Reg<GRXSTSR_SPEC>`"]
543pub type GRXSTSR = crate::Reg<grxstsr::GRXSTSR_SPEC>;
544#[doc = "Receive Status Debug Read Register"]
545pub mod grxstsr;
546#[doc = "GRXSTSP register accessor: an alias for `Reg<GRXSTSP_SPEC>`"]
547pub type GRXSTSP = crate::Reg<grxstsp::GRXSTSP_SPEC>;
548#[doc = "Receive Status Read /Pop Register"]
549pub mod grxstsp;
550#[doc = "GRXFSIZ register accessor: an alias for `Reg<GRXFSIZ_SPEC>`"]
551pub type GRXFSIZ = crate::Reg<grxfsiz::GRXFSIZ_SPEC>;
552#[doc = "Receive FIFO Size Register"]
553pub mod grxfsiz;
554#[doc = "GNPTXFSIZ register accessor: an alias for `Reg<GNPTXFSIZ_SPEC>`"]
555pub type GNPTXFSIZ = crate::Reg<gnptxfsiz::GNPTXFSIZ_SPEC>;
556#[doc = "Non-periodic Transmit FIFO Size Register"]
557pub mod gnptxfsiz;
558#[doc = "GNPTXSTS register accessor: an alias for `Reg<GNPTXSTS_SPEC>`"]
559pub type GNPTXSTS = crate::Reg<gnptxsts::GNPTXSTS_SPEC>;
560#[doc = "Non-periodic Transmit FIFO/Queue Status Register"]
561pub mod gnptxsts;
562#[doc = "GSNPSID register accessor: an alias for `Reg<GSNPSID_SPEC>`"]
563pub type GSNPSID = crate::Reg<gsnpsid::GSNPSID_SPEC>;
564#[doc = "Synopsys ID Register"]
565pub mod gsnpsid;
566#[doc = "GDFIFOCFG register accessor: an alias for `Reg<GDFIFOCFG_SPEC>`"]
567pub type GDFIFOCFG = crate::Reg<gdfifocfg::GDFIFOCFG_SPEC>;
568#[doc = "Global DFIFO Configuration Register"]
569pub mod gdfifocfg;
570#[doc = "HPTXFSIZ register accessor: an alias for `Reg<HPTXFSIZ_SPEC>`"]
571pub type HPTXFSIZ = crate::Reg<hptxfsiz::HPTXFSIZ_SPEC>;
572#[doc = "Host Periodic Transmit FIFO Size Register"]
573pub mod hptxfsiz;
574#[doc = "DIEPTXF1 register accessor: an alias for `Reg<DIEPTXF1_SPEC>`"]
575pub type DIEPTXF1 = crate::Reg<dieptxf1::DIEPTXF1_SPEC>;
576#[doc = "Device IN Endpoint Transmit FIFO Size Register 1"]
577pub mod dieptxf1;
578#[doc = "DIEPTXF2 register accessor: an alias for `Reg<DIEPTXF2_SPEC>`"]
579pub type DIEPTXF2 = crate::Reg<dieptxf2::DIEPTXF2_SPEC>;
580#[doc = "Device IN Endpoint Transmit FIFO Size Register 2"]
581pub mod dieptxf2;
582#[doc = "DIEPTXF3 register accessor: an alias for `Reg<DIEPTXF3_SPEC>`"]
583pub type DIEPTXF3 = crate::Reg<dieptxf3::DIEPTXF3_SPEC>;
584#[doc = "Device IN Endpoint Transmit FIFO Size Register 3"]
585pub mod dieptxf3;
586#[doc = "DIEPTXF4 register accessor: an alias for `Reg<DIEPTXF4_SPEC>`"]
587pub type DIEPTXF4 = crate::Reg<dieptxf4::DIEPTXF4_SPEC>;
588#[doc = "Device IN Endpoint Transmit FIFO Size Register 4"]
589pub mod dieptxf4;
590#[doc = "DIEPTXF5 register accessor: an alias for `Reg<DIEPTXF5_SPEC>`"]
591pub type DIEPTXF5 = crate::Reg<dieptxf5::DIEPTXF5_SPEC>;
592#[doc = "Device IN Endpoint Transmit FIFO Size Register 5"]
593pub mod dieptxf5;
594#[doc = "DIEPTXF6 register accessor: an alias for `Reg<DIEPTXF6_SPEC>`"]
595pub type DIEPTXF6 = crate::Reg<dieptxf6::DIEPTXF6_SPEC>;
596#[doc = "Device IN Endpoint Transmit FIFO Size Register 6"]
597pub mod dieptxf6;
598#[doc = "HCFG register accessor: an alias for `Reg<HCFG_SPEC>`"]
599pub type HCFG = crate::Reg<hcfg::HCFG_SPEC>;
600#[doc = "Host Configuration Register"]
601pub mod hcfg;
602#[doc = "HFIR register accessor: an alias for `Reg<HFIR_SPEC>`"]
603pub type HFIR = crate::Reg<hfir::HFIR_SPEC>;
604#[doc = "Host Frame Interval Register"]
605pub mod hfir;
606#[doc = "HFNUM register accessor: an alias for `Reg<HFNUM_SPEC>`"]
607pub type HFNUM = crate::Reg<hfnum::HFNUM_SPEC>;
608#[doc = "Host Frame Number/Frame Time Remaining Register"]
609pub mod hfnum;
610#[doc = "HPTXSTS register accessor: an alias for `Reg<HPTXSTS_SPEC>`"]
611pub type HPTXSTS = crate::Reg<hptxsts::HPTXSTS_SPEC>;
612#[doc = "Host Periodic Transmit FIFO/Queue Status Register"]
613pub mod hptxsts;
614#[doc = "HAINT register accessor: an alias for `Reg<HAINT_SPEC>`"]
615pub type HAINT = crate::Reg<haint::HAINT_SPEC>;
616#[doc = "Host All Channels Interrupt Register"]
617pub mod haint;
618#[doc = "HAINTMSK register accessor: an alias for `Reg<HAINTMSK_SPEC>`"]
619pub type HAINTMSK = crate::Reg<haintmsk::HAINTMSK_SPEC>;
620#[doc = "Host All Channels Interrupt Mask Register"]
621pub mod haintmsk;
622#[doc = "HPRT register accessor: an alias for `Reg<HPRT_SPEC>`"]
623pub type HPRT = crate::Reg<hprt::HPRT_SPEC>;
624#[doc = "Host Port Control and Status Register"]
625pub mod hprt;
626#[doc = "HC0_CHAR register accessor: an alias for `Reg<HC0_CHAR_SPEC>`"]
627pub type HC0_CHAR = crate::Reg<hc0_char::HC0_CHAR_SPEC>;
628#[doc = "Host Channel x Characteristics Register"]
629pub mod hc0_char;
630#[doc = "HC0_SPLT register accessor: an alias for `Reg<HC0_SPLT_SPEC>`"]
631pub type HC0_SPLT = crate::Reg<hc0_splt::HC0_SPLT_SPEC>;
632#[doc = "Host Channel x Split Control Register"]
633pub mod hc0_splt;
634#[doc = "HC0_INT register accessor: an alias for `Reg<HC0_INT_SPEC>`"]
635pub type HC0_INT = crate::Reg<hc0_int::HC0_INT_SPEC>;
636#[doc = "Host Channel x Interrupt Register"]
637pub mod hc0_int;
638#[doc = "HC0_INTMSK register accessor: an alias for `Reg<HC0_INTMSK_SPEC>`"]
639pub type HC0_INTMSK = crate::Reg<hc0_intmsk::HC0_INTMSK_SPEC>;
640#[doc = "Host Channel x Interrupt Mask Register"]
641pub mod hc0_intmsk;
642#[doc = "HC0_TSIZ register accessor: an alias for `Reg<HC0_TSIZ_SPEC>`"]
643pub type HC0_TSIZ = crate::Reg<hc0_tsiz::HC0_TSIZ_SPEC>;
644#[doc = "Host Channel x Transfer Size Register"]
645pub mod hc0_tsiz;
646#[doc = "HC0_DMAADDR register accessor: an alias for `Reg<HC0_DMAADDR_SPEC>`"]
647pub type HC0_DMAADDR = crate::Reg<hc0_dmaaddr::HC0_DMAADDR_SPEC>;
648#[doc = "Host Channel x DMA Address Register"]
649pub mod hc0_dmaaddr;
650#[doc = "HC1_CHAR register accessor: an alias for `Reg<HC1_CHAR_SPEC>`"]
651pub type HC1_CHAR = crate::Reg<hc1_char::HC1_CHAR_SPEC>;
652#[doc = "Host Channel x Characteristics Register"]
653pub mod hc1_char;
654#[doc = "HC1_SPLT register accessor: an alias for `Reg<HC1_SPLT_SPEC>`"]
655pub type HC1_SPLT = crate::Reg<hc1_splt::HC1_SPLT_SPEC>;
656#[doc = "Host Channel x Split Control Register"]
657pub mod hc1_splt;
658#[doc = "HC1_INT register accessor: an alias for `Reg<HC1_INT_SPEC>`"]
659pub type HC1_INT = crate::Reg<hc1_int::HC1_INT_SPEC>;
660#[doc = "Host Channel x Interrupt Register"]
661pub mod hc1_int;
662#[doc = "HC1_INTMSK register accessor: an alias for `Reg<HC1_INTMSK_SPEC>`"]
663pub type HC1_INTMSK = crate::Reg<hc1_intmsk::HC1_INTMSK_SPEC>;
664#[doc = "Host Channel x Interrupt Mask Register"]
665pub mod hc1_intmsk;
666#[doc = "HC1_TSIZ register accessor: an alias for `Reg<HC1_TSIZ_SPEC>`"]
667pub type HC1_TSIZ = crate::Reg<hc1_tsiz::HC1_TSIZ_SPEC>;
668#[doc = "Host Channel x Transfer Size Register"]
669pub mod hc1_tsiz;
670#[doc = "HC1_DMAADDR register accessor: an alias for `Reg<HC1_DMAADDR_SPEC>`"]
671pub type HC1_DMAADDR = crate::Reg<hc1_dmaaddr::HC1_DMAADDR_SPEC>;
672#[doc = "Host Channel x DMA Address Register"]
673pub mod hc1_dmaaddr;
674#[doc = "HC2_CHAR register accessor: an alias for `Reg<HC2_CHAR_SPEC>`"]
675pub type HC2_CHAR = crate::Reg<hc2_char::HC2_CHAR_SPEC>;
676#[doc = "Host Channel x Characteristics Register"]
677pub mod hc2_char;
678#[doc = "HC2_SPLT register accessor: an alias for `Reg<HC2_SPLT_SPEC>`"]
679pub type HC2_SPLT = crate::Reg<hc2_splt::HC2_SPLT_SPEC>;
680#[doc = "Host Channel x Split Control Register"]
681pub mod hc2_splt;
682#[doc = "HC2_INT register accessor: an alias for `Reg<HC2_INT_SPEC>`"]
683pub type HC2_INT = crate::Reg<hc2_int::HC2_INT_SPEC>;
684#[doc = "Host Channel x Interrupt Register"]
685pub mod hc2_int;
686#[doc = "HC2_INTMSK register accessor: an alias for `Reg<HC2_INTMSK_SPEC>`"]
687pub type HC2_INTMSK = crate::Reg<hc2_intmsk::HC2_INTMSK_SPEC>;
688#[doc = "Host Channel x Interrupt Mask Register"]
689pub mod hc2_intmsk;
690#[doc = "HC2_TSIZ register accessor: an alias for `Reg<HC2_TSIZ_SPEC>`"]
691pub type HC2_TSIZ = crate::Reg<hc2_tsiz::HC2_TSIZ_SPEC>;
692#[doc = "Host Channel x Transfer Size Register"]
693pub mod hc2_tsiz;
694#[doc = "HC2_DMAADDR register accessor: an alias for `Reg<HC2_DMAADDR_SPEC>`"]
695pub type HC2_DMAADDR = crate::Reg<hc2_dmaaddr::HC2_DMAADDR_SPEC>;
696#[doc = "Host Channel x DMA Address Register"]
697pub mod hc2_dmaaddr;
698#[doc = "HC3_CHAR register accessor: an alias for `Reg<HC3_CHAR_SPEC>`"]
699pub type HC3_CHAR = crate::Reg<hc3_char::HC3_CHAR_SPEC>;
700#[doc = "Host Channel x Characteristics Register"]
701pub mod hc3_char;
702#[doc = "HC3_SPLT register accessor: an alias for `Reg<HC3_SPLT_SPEC>`"]
703pub type HC3_SPLT = crate::Reg<hc3_splt::HC3_SPLT_SPEC>;
704#[doc = "Host Channel x Split Control Register"]
705pub mod hc3_splt;
706#[doc = "HC3_INT register accessor: an alias for `Reg<HC3_INT_SPEC>`"]
707pub type HC3_INT = crate::Reg<hc3_int::HC3_INT_SPEC>;
708#[doc = "Host Channel x Interrupt Register"]
709pub mod hc3_int;
710#[doc = "HC3_INTMSK register accessor: an alias for `Reg<HC3_INTMSK_SPEC>`"]
711pub type HC3_INTMSK = crate::Reg<hc3_intmsk::HC3_INTMSK_SPEC>;
712#[doc = "Host Channel x Interrupt Mask Register"]
713pub mod hc3_intmsk;
714#[doc = "HC3_TSIZ register accessor: an alias for `Reg<HC3_TSIZ_SPEC>`"]
715pub type HC3_TSIZ = crate::Reg<hc3_tsiz::HC3_TSIZ_SPEC>;
716#[doc = "Host Channel x Transfer Size Register"]
717pub mod hc3_tsiz;
718#[doc = "HC3_DMAADDR register accessor: an alias for `Reg<HC3_DMAADDR_SPEC>`"]
719pub type HC3_DMAADDR = crate::Reg<hc3_dmaaddr::HC3_DMAADDR_SPEC>;
720#[doc = "Host Channel x DMA Address Register"]
721pub mod hc3_dmaaddr;
722#[doc = "HC4_CHAR register accessor: an alias for `Reg<HC4_CHAR_SPEC>`"]
723pub type HC4_CHAR = crate::Reg<hc4_char::HC4_CHAR_SPEC>;
724#[doc = "Host Channel x Characteristics Register"]
725pub mod hc4_char;
726#[doc = "HC4_SPLT register accessor: an alias for `Reg<HC4_SPLT_SPEC>`"]
727pub type HC4_SPLT = crate::Reg<hc4_splt::HC4_SPLT_SPEC>;
728#[doc = "Host Channel x Split Control Register"]
729pub mod hc4_splt;
730#[doc = "HC4_INT register accessor: an alias for `Reg<HC4_INT_SPEC>`"]
731pub type HC4_INT = crate::Reg<hc4_int::HC4_INT_SPEC>;
732#[doc = "Host Channel x Interrupt Register"]
733pub mod hc4_int;
734#[doc = "HC4_INTMSK register accessor: an alias for `Reg<HC4_INTMSK_SPEC>`"]
735pub type HC4_INTMSK = crate::Reg<hc4_intmsk::HC4_INTMSK_SPEC>;
736#[doc = "Host Channel x Interrupt Mask Register"]
737pub mod hc4_intmsk;
738#[doc = "HC4_TSIZ register accessor: an alias for `Reg<HC4_TSIZ_SPEC>`"]
739pub type HC4_TSIZ = crate::Reg<hc4_tsiz::HC4_TSIZ_SPEC>;
740#[doc = "Host Channel x Transfer Size Register"]
741pub mod hc4_tsiz;
742#[doc = "HC4_DMAADDR register accessor: an alias for `Reg<HC4_DMAADDR_SPEC>`"]
743pub type HC4_DMAADDR = crate::Reg<hc4_dmaaddr::HC4_DMAADDR_SPEC>;
744#[doc = "Host Channel x DMA Address Register"]
745pub mod hc4_dmaaddr;
746#[doc = "HC5_CHAR register accessor: an alias for `Reg<HC5_CHAR_SPEC>`"]
747pub type HC5_CHAR = crate::Reg<hc5_char::HC5_CHAR_SPEC>;
748#[doc = "Host Channel x Characteristics Register"]
749pub mod hc5_char;
750#[doc = "HC5_SPLT register accessor: an alias for `Reg<HC5_SPLT_SPEC>`"]
751pub type HC5_SPLT = crate::Reg<hc5_splt::HC5_SPLT_SPEC>;
752#[doc = "Host Channel x Split Control Register"]
753pub mod hc5_splt;
754#[doc = "HC5_INT register accessor: an alias for `Reg<HC5_INT_SPEC>`"]
755pub type HC5_INT = crate::Reg<hc5_int::HC5_INT_SPEC>;
756#[doc = "Host Channel x Interrupt Register"]
757pub mod hc5_int;
758#[doc = "HC5_INTMSK register accessor: an alias for `Reg<HC5_INTMSK_SPEC>`"]
759pub type HC5_INTMSK = crate::Reg<hc5_intmsk::HC5_INTMSK_SPEC>;
760#[doc = "Host Channel x Interrupt Mask Register"]
761pub mod hc5_intmsk;
762#[doc = "HC5_TSIZ register accessor: an alias for `Reg<HC5_TSIZ_SPEC>`"]
763pub type HC5_TSIZ = crate::Reg<hc5_tsiz::HC5_TSIZ_SPEC>;
764#[doc = "Host Channel x Transfer Size Register"]
765pub mod hc5_tsiz;
766#[doc = "HC5_DMAADDR register accessor: an alias for `Reg<HC5_DMAADDR_SPEC>`"]
767pub type HC5_DMAADDR = crate::Reg<hc5_dmaaddr::HC5_DMAADDR_SPEC>;
768#[doc = "Host Channel x DMA Address Register"]
769pub mod hc5_dmaaddr;
770#[doc = "HC6_CHAR register accessor: an alias for `Reg<HC6_CHAR_SPEC>`"]
771pub type HC6_CHAR = crate::Reg<hc6_char::HC6_CHAR_SPEC>;
772#[doc = "Host Channel x Characteristics Register"]
773pub mod hc6_char;
774#[doc = "HC6_SPLT register accessor: an alias for `Reg<HC6_SPLT_SPEC>`"]
775pub type HC6_SPLT = crate::Reg<hc6_splt::HC6_SPLT_SPEC>;
776#[doc = "Host Channel x Split Control Register"]
777pub mod hc6_splt;
778#[doc = "HC6_INT register accessor: an alias for `Reg<HC6_INT_SPEC>`"]
779pub type HC6_INT = crate::Reg<hc6_int::HC6_INT_SPEC>;
780#[doc = "Host Channel x Interrupt Register"]
781pub mod hc6_int;
782#[doc = "HC6_INTMSK register accessor: an alias for `Reg<HC6_INTMSK_SPEC>`"]
783pub type HC6_INTMSK = crate::Reg<hc6_intmsk::HC6_INTMSK_SPEC>;
784#[doc = "Host Channel x Interrupt Mask Register"]
785pub mod hc6_intmsk;
786#[doc = "HC6_TSIZ register accessor: an alias for `Reg<HC6_TSIZ_SPEC>`"]
787pub type HC6_TSIZ = crate::Reg<hc6_tsiz::HC6_TSIZ_SPEC>;
788#[doc = "Host Channel x Transfer Size Register"]
789pub mod hc6_tsiz;
790#[doc = "HC6_DMAADDR register accessor: an alias for `Reg<HC6_DMAADDR_SPEC>`"]
791pub type HC6_DMAADDR = crate::Reg<hc6_dmaaddr::HC6_DMAADDR_SPEC>;
792#[doc = "Host Channel x DMA Address Register"]
793pub mod hc6_dmaaddr;
794#[doc = "HC7_CHAR register accessor: an alias for `Reg<HC7_CHAR_SPEC>`"]
795pub type HC7_CHAR = crate::Reg<hc7_char::HC7_CHAR_SPEC>;
796#[doc = "Host Channel x Characteristics Register"]
797pub mod hc7_char;
798#[doc = "HC7_SPLT register accessor: an alias for `Reg<HC7_SPLT_SPEC>`"]
799pub type HC7_SPLT = crate::Reg<hc7_splt::HC7_SPLT_SPEC>;
800#[doc = "Host Channel x Split Control Register"]
801pub mod hc7_splt;
802#[doc = "HC7_INT register accessor: an alias for `Reg<HC7_INT_SPEC>`"]
803pub type HC7_INT = crate::Reg<hc7_int::HC7_INT_SPEC>;
804#[doc = "Host Channel x Interrupt Register"]
805pub mod hc7_int;
806#[doc = "HC7_INTMSK register accessor: an alias for `Reg<HC7_INTMSK_SPEC>`"]
807pub type HC7_INTMSK = crate::Reg<hc7_intmsk::HC7_INTMSK_SPEC>;
808#[doc = "Host Channel x Interrupt Mask Register"]
809pub mod hc7_intmsk;
810#[doc = "HC7_TSIZ register accessor: an alias for `Reg<HC7_TSIZ_SPEC>`"]
811pub type HC7_TSIZ = crate::Reg<hc7_tsiz::HC7_TSIZ_SPEC>;
812#[doc = "Host Channel x Transfer Size Register"]
813pub mod hc7_tsiz;
814#[doc = "HC7_DMAADDR register accessor: an alias for `Reg<HC7_DMAADDR_SPEC>`"]
815pub type HC7_DMAADDR = crate::Reg<hc7_dmaaddr::HC7_DMAADDR_SPEC>;
816#[doc = "Host Channel x DMA Address Register"]
817pub mod hc7_dmaaddr;
818#[doc = "HC8_CHAR register accessor: an alias for `Reg<HC8_CHAR_SPEC>`"]
819pub type HC8_CHAR = crate::Reg<hc8_char::HC8_CHAR_SPEC>;
820#[doc = "Host Channel x Characteristics Register"]
821pub mod hc8_char;
822#[doc = "HC8_SPLT register accessor: an alias for `Reg<HC8_SPLT_SPEC>`"]
823pub type HC8_SPLT = crate::Reg<hc8_splt::HC8_SPLT_SPEC>;
824#[doc = "Host Channel x Split Control Register"]
825pub mod hc8_splt;
826#[doc = "HC8_INT register accessor: an alias for `Reg<HC8_INT_SPEC>`"]
827pub type HC8_INT = crate::Reg<hc8_int::HC8_INT_SPEC>;
828#[doc = "Host Channel x Interrupt Register"]
829pub mod hc8_int;
830#[doc = "HC8_INTMSK register accessor: an alias for `Reg<HC8_INTMSK_SPEC>`"]
831pub type HC8_INTMSK = crate::Reg<hc8_intmsk::HC8_INTMSK_SPEC>;
832#[doc = "Host Channel x Interrupt Mask Register"]
833pub mod hc8_intmsk;
834#[doc = "HC8_TSIZ register accessor: an alias for `Reg<HC8_TSIZ_SPEC>`"]
835pub type HC8_TSIZ = crate::Reg<hc8_tsiz::HC8_TSIZ_SPEC>;
836#[doc = "Host Channel x Transfer Size Register"]
837pub mod hc8_tsiz;
838#[doc = "HC8_DMAADDR register accessor: an alias for `Reg<HC8_DMAADDR_SPEC>`"]
839pub type HC8_DMAADDR = crate::Reg<hc8_dmaaddr::HC8_DMAADDR_SPEC>;
840#[doc = "Host Channel x DMA Address Register"]
841pub mod hc8_dmaaddr;
842#[doc = "HC9_CHAR register accessor: an alias for `Reg<HC9_CHAR_SPEC>`"]
843pub type HC9_CHAR = crate::Reg<hc9_char::HC9_CHAR_SPEC>;
844#[doc = "Host Channel x Characteristics Register"]
845pub mod hc9_char;
846#[doc = "HC9_SPLT register accessor: an alias for `Reg<HC9_SPLT_SPEC>`"]
847pub type HC9_SPLT = crate::Reg<hc9_splt::HC9_SPLT_SPEC>;
848#[doc = "Host Channel x Split Control Register"]
849pub mod hc9_splt;
850#[doc = "HC9_INT register accessor: an alias for `Reg<HC9_INT_SPEC>`"]
851pub type HC9_INT = crate::Reg<hc9_int::HC9_INT_SPEC>;
852#[doc = "Host Channel x Interrupt Register"]
853pub mod hc9_int;
854#[doc = "HC9_INTMSK register accessor: an alias for `Reg<HC9_INTMSK_SPEC>`"]
855pub type HC9_INTMSK = crate::Reg<hc9_intmsk::HC9_INTMSK_SPEC>;
856#[doc = "Host Channel x Interrupt Mask Register"]
857pub mod hc9_intmsk;
858#[doc = "HC9_TSIZ register accessor: an alias for `Reg<HC9_TSIZ_SPEC>`"]
859pub type HC9_TSIZ = crate::Reg<hc9_tsiz::HC9_TSIZ_SPEC>;
860#[doc = "Host Channel x Transfer Size Register"]
861pub mod hc9_tsiz;
862#[doc = "HC9_DMAADDR register accessor: an alias for `Reg<HC9_DMAADDR_SPEC>`"]
863pub type HC9_DMAADDR = crate::Reg<hc9_dmaaddr::HC9_DMAADDR_SPEC>;
864#[doc = "Host Channel x DMA Address Register"]
865pub mod hc9_dmaaddr;
866#[doc = "HC10_CHAR register accessor: an alias for `Reg<HC10_CHAR_SPEC>`"]
867pub type HC10_CHAR = crate::Reg<hc10_char::HC10_CHAR_SPEC>;
868#[doc = "Host Channel x Characteristics Register"]
869pub mod hc10_char;
870#[doc = "HC10_SPLT register accessor: an alias for `Reg<HC10_SPLT_SPEC>`"]
871pub type HC10_SPLT = crate::Reg<hc10_splt::HC10_SPLT_SPEC>;
872#[doc = "Host Channel x Split Control Register"]
873pub mod hc10_splt;
874#[doc = "HC10_INT register accessor: an alias for `Reg<HC10_INT_SPEC>`"]
875pub type HC10_INT = crate::Reg<hc10_int::HC10_INT_SPEC>;
876#[doc = "Host Channel x Interrupt Register"]
877pub mod hc10_int;
878#[doc = "HC10_INTMSK register accessor: an alias for `Reg<HC10_INTMSK_SPEC>`"]
879pub type HC10_INTMSK = crate::Reg<hc10_intmsk::HC10_INTMSK_SPEC>;
880#[doc = "Host Channel x Interrupt Mask Register"]
881pub mod hc10_intmsk;
882#[doc = "HC10_TSIZ register accessor: an alias for `Reg<HC10_TSIZ_SPEC>`"]
883pub type HC10_TSIZ = crate::Reg<hc10_tsiz::HC10_TSIZ_SPEC>;
884#[doc = "Host Channel x Transfer Size Register"]
885pub mod hc10_tsiz;
886#[doc = "HC10_DMAADDR register accessor: an alias for `Reg<HC10_DMAADDR_SPEC>`"]
887pub type HC10_DMAADDR = crate::Reg<hc10_dmaaddr::HC10_DMAADDR_SPEC>;
888#[doc = "Host Channel x DMA Address Register"]
889pub mod hc10_dmaaddr;
890#[doc = "HC11_CHAR register accessor: an alias for `Reg<HC11_CHAR_SPEC>`"]
891pub type HC11_CHAR = crate::Reg<hc11_char::HC11_CHAR_SPEC>;
892#[doc = "Host Channel x Characteristics Register"]
893pub mod hc11_char;
894#[doc = "HC11_SPLT register accessor: an alias for `Reg<HC11_SPLT_SPEC>`"]
895pub type HC11_SPLT = crate::Reg<hc11_splt::HC11_SPLT_SPEC>;
896#[doc = "Host Channel x Split Control Register"]
897pub mod hc11_splt;
898#[doc = "HC11_INT register accessor: an alias for `Reg<HC11_INT_SPEC>`"]
899pub type HC11_INT = crate::Reg<hc11_int::HC11_INT_SPEC>;
900#[doc = "Host Channel x Interrupt Register"]
901pub mod hc11_int;
902#[doc = "HC11_INTMSK register accessor: an alias for `Reg<HC11_INTMSK_SPEC>`"]
903pub type HC11_INTMSK = crate::Reg<hc11_intmsk::HC11_INTMSK_SPEC>;
904#[doc = "Host Channel x Interrupt Mask Register"]
905pub mod hc11_intmsk;
906#[doc = "HC11_TSIZ register accessor: an alias for `Reg<HC11_TSIZ_SPEC>`"]
907pub type HC11_TSIZ = crate::Reg<hc11_tsiz::HC11_TSIZ_SPEC>;
908#[doc = "Host Channel x Transfer Size Register"]
909pub mod hc11_tsiz;
910#[doc = "HC11_DMAADDR register accessor: an alias for `Reg<HC11_DMAADDR_SPEC>`"]
911pub type HC11_DMAADDR = crate::Reg<hc11_dmaaddr::HC11_DMAADDR_SPEC>;
912#[doc = "Host Channel x DMA Address Register"]
913pub mod hc11_dmaaddr;
914#[doc = "HC12_CHAR register accessor: an alias for `Reg<HC12_CHAR_SPEC>`"]
915pub type HC12_CHAR = crate::Reg<hc12_char::HC12_CHAR_SPEC>;
916#[doc = "Host Channel x Characteristics Register"]
917pub mod hc12_char;
918#[doc = "HC12_SPLT register accessor: an alias for `Reg<HC12_SPLT_SPEC>`"]
919pub type HC12_SPLT = crate::Reg<hc12_splt::HC12_SPLT_SPEC>;
920#[doc = "Host Channel x Split Control Register"]
921pub mod hc12_splt;
922#[doc = "HC12_INT register accessor: an alias for `Reg<HC12_INT_SPEC>`"]
923pub type HC12_INT = crate::Reg<hc12_int::HC12_INT_SPEC>;
924#[doc = "Host Channel x Interrupt Register"]
925pub mod hc12_int;
926#[doc = "HC12_INTMSK register accessor: an alias for `Reg<HC12_INTMSK_SPEC>`"]
927pub type HC12_INTMSK = crate::Reg<hc12_intmsk::HC12_INTMSK_SPEC>;
928#[doc = "Host Channel x Interrupt Mask Register"]
929pub mod hc12_intmsk;
930#[doc = "HC12_TSIZ register accessor: an alias for `Reg<HC12_TSIZ_SPEC>`"]
931pub type HC12_TSIZ = crate::Reg<hc12_tsiz::HC12_TSIZ_SPEC>;
932#[doc = "Host Channel x Transfer Size Register"]
933pub mod hc12_tsiz;
934#[doc = "HC12_DMAADDR register accessor: an alias for `Reg<HC12_DMAADDR_SPEC>`"]
935pub type HC12_DMAADDR = crate::Reg<hc12_dmaaddr::HC12_DMAADDR_SPEC>;
936#[doc = "Host Channel x DMA Address Register"]
937pub mod hc12_dmaaddr;
938#[doc = "HC13_CHAR register accessor: an alias for `Reg<HC13_CHAR_SPEC>`"]
939pub type HC13_CHAR = crate::Reg<hc13_char::HC13_CHAR_SPEC>;
940#[doc = "Host Channel x Characteristics Register"]
941pub mod hc13_char;
942#[doc = "HC13_SPLT register accessor: an alias for `Reg<HC13_SPLT_SPEC>`"]
943pub type HC13_SPLT = crate::Reg<hc13_splt::HC13_SPLT_SPEC>;
944#[doc = "Host Channel x Split Control Register"]
945pub mod hc13_splt;
946#[doc = "HC13_INT register accessor: an alias for `Reg<HC13_INT_SPEC>`"]
947pub type HC13_INT = crate::Reg<hc13_int::HC13_INT_SPEC>;
948#[doc = "Host Channel x Interrupt Register"]
949pub mod hc13_int;
950#[doc = "HC13_INTMSK register accessor: an alias for `Reg<HC13_INTMSK_SPEC>`"]
951pub type HC13_INTMSK = crate::Reg<hc13_intmsk::HC13_INTMSK_SPEC>;
952#[doc = "Host Channel x Interrupt Mask Register"]
953pub mod hc13_intmsk;
954#[doc = "HC13_TSIZ register accessor: an alias for `Reg<HC13_TSIZ_SPEC>`"]
955pub type HC13_TSIZ = crate::Reg<hc13_tsiz::HC13_TSIZ_SPEC>;
956#[doc = "Host Channel x Transfer Size Register"]
957pub mod hc13_tsiz;
958#[doc = "HC13_DMAADDR register accessor: an alias for `Reg<HC13_DMAADDR_SPEC>`"]
959pub type HC13_DMAADDR = crate::Reg<hc13_dmaaddr::HC13_DMAADDR_SPEC>;
960#[doc = "Host Channel x DMA Address Register"]
961pub mod hc13_dmaaddr;
962#[doc = "DCFG register accessor: an alias for `Reg<DCFG_SPEC>`"]
963pub type DCFG = crate::Reg<dcfg::DCFG_SPEC>;
964#[doc = "Device Configuration Register"]
965pub mod dcfg;
966#[doc = "DCTL register accessor: an alias for `Reg<DCTL_SPEC>`"]
967pub type DCTL = crate::Reg<dctl::DCTL_SPEC>;
968#[doc = "Device Control Register"]
969pub mod dctl;
970#[doc = "DSTS register accessor: an alias for `Reg<DSTS_SPEC>`"]
971pub type DSTS = crate::Reg<dsts::DSTS_SPEC>;
972#[doc = "Device Status Register"]
973pub mod dsts;
974#[doc = "DIEPMSK register accessor: an alias for `Reg<DIEPMSK_SPEC>`"]
975pub type DIEPMSK = crate::Reg<diepmsk::DIEPMSK_SPEC>;
976#[doc = "Device IN Endpoint Common Interrupt Mask Register"]
977pub mod diepmsk;
978#[doc = "DOEPMSK register accessor: an alias for `Reg<DOEPMSK_SPEC>`"]
979pub type DOEPMSK = crate::Reg<doepmsk::DOEPMSK_SPEC>;
980#[doc = "Device OUT Endpoint Common Interrupt Mask Register"]
981pub mod doepmsk;
982#[doc = "DAINT register accessor: an alias for `Reg<DAINT_SPEC>`"]
983pub type DAINT = crate::Reg<daint::DAINT_SPEC>;
984#[doc = "Device All Endpoints Interrupt Register"]
985pub mod daint;
986#[doc = "DAINTMSK register accessor: an alias for `Reg<DAINTMSK_SPEC>`"]
987pub type DAINTMSK = crate::Reg<daintmsk::DAINTMSK_SPEC>;
988#[doc = "Device All Endpoints Interrupt Mask Register"]
989pub mod daintmsk;
990#[doc = "DVBUSDIS register accessor: an alias for `Reg<DVBUSDIS_SPEC>`"]
991pub type DVBUSDIS = crate::Reg<dvbusdis::DVBUSDIS_SPEC>;
992#[doc = "Device VBUS Discharge Time Register"]
993pub mod dvbusdis;
994#[doc = "DVBUSPULSE register accessor: an alias for `Reg<DVBUSPULSE_SPEC>`"]
995pub type DVBUSPULSE = crate::Reg<dvbuspulse::DVBUSPULSE_SPEC>;
996#[doc = "Device VBUS Pulsing Time Register"]
997pub mod dvbuspulse;
998#[doc = "DTHRCTL register accessor: an alias for `Reg<DTHRCTL_SPEC>`"]
999pub type DTHRCTL = crate::Reg<dthrctl::DTHRCTL_SPEC>;
1000#[doc = "Device Threshold Control Register"]
1001pub mod dthrctl;
1002#[doc = "DIEPEMPMSK register accessor: an alias for `Reg<DIEPEMPMSK_SPEC>`"]
1003pub type DIEPEMPMSK = crate::Reg<diepempmsk::DIEPEMPMSK_SPEC>;
1004#[doc = "Device IN Endpoint FIFO Empty Interrupt Mask Register"]
1005pub mod diepempmsk;
1006#[doc = "DIEP0CTL register accessor: an alias for `Reg<DIEP0CTL_SPEC>`"]
1007pub type DIEP0CTL = crate::Reg<diep0ctl::DIEP0CTL_SPEC>;
1008#[doc = "Device Control IN Endpoint 0 Control Register"]
1009pub mod diep0ctl;
1010#[doc = "DIEP0INT register accessor: an alias for `Reg<DIEP0INT_SPEC>`"]
1011pub type DIEP0INT = crate::Reg<diep0int::DIEP0INT_SPEC>;
1012#[doc = "Device IN Endpoint 0 Interrupt Register"]
1013pub mod diep0int;
1014#[doc = "DIEP0TSIZ register accessor: an alias for `Reg<DIEP0TSIZ_SPEC>`"]
1015pub type DIEP0TSIZ = crate::Reg<diep0tsiz::DIEP0TSIZ_SPEC>;
1016#[doc = "Device IN Endpoint 0 Transfer Size Register"]
1017pub mod diep0tsiz;
1018#[doc = "DIEP0DMAADDR register accessor: an alias for `Reg<DIEP0DMAADDR_SPEC>`"]
1019pub type DIEP0DMAADDR = crate::Reg<diep0dmaaddr::DIEP0DMAADDR_SPEC>;
1020#[doc = "Device IN Endpoint 0 DMA Address Register"]
1021pub mod diep0dmaaddr;
1022#[doc = "DIEP0TXFSTS register accessor: an alias for `Reg<DIEP0TXFSTS_SPEC>`"]
1023pub type DIEP0TXFSTS = crate::Reg<diep0txfsts::DIEP0TXFSTS_SPEC>;
1024#[doc = "Device IN Endpoint Transmit FIFO Status Register 0"]
1025pub mod diep0txfsts;
1026#[doc = "DIEP0_CTL register accessor: an alias for `Reg<DIEP0_CTL_SPEC>`"]
1027pub type DIEP0_CTL = crate::Reg<diep0_ctl::DIEP0_CTL_SPEC>;
1028#[doc = "Device Control IN Endpoint x+1 Control Register"]
1029pub mod diep0_ctl;
1030#[doc = "DIEP0_INT register accessor: an alias for `Reg<DIEP0_INT_SPEC>`"]
1031pub type DIEP0_INT = crate::Reg<diep0_int::DIEP0_INT_SPEC>;
1032#[doc = "Device IN Endpoint x+1 Interrupt Register"]
1033pub mod diep0_int;
1034#[doc = "DIEP0_TSIZ register accessor: an alias for `Reg<DIEP0_TSIZ_SPEC>`"]
1035pub type DIEP0_TSIZ = crate::Reg<diep0_tsiz::DIEP0_TSIZ_SPEC>;
1036#[doc = "Device IN Endpoint x+1 Transfer Size Register"]
1037pub mod diep0_tsiz;
1038#[doc = "DIEP0_DMAADDR register accessor: an alias for `Reg<DIEP0_DMAADDR_SPEC>`"]
1039pub type DIEP0_DMAADDR = crate::Reg<diep0_dmaaddr::DIEP0_DMAADDR_SPEC>;
1040#[doc = "Device IN Endpoint x+1 DMA Address Register"]
1041pub mod diep0_dmaaddr;
1042#[doc = "DIEP0_DTXFSTS register accessor: an alias for `Reg<DIEP0_DTXFSTS_SPEC>`"]
1043pub type DIEP0_DTXFSTS = crate::Reg<diep0_dtxfsts::DIEP0_DTXFSTS_SPEC>;
1044#[doc = "Device IN Endpoint Transmit FIFO Status Register 1"]
1045pub mod diep0_dtxfsts;
1046#[doc = "DIEP1_CTL register accessor: an alias for `Reg<DIEP1_CTL_SPEC>`"]
1047pub type DIEP1_CTL = crate::Reg<diep1_ctl::DIEP1_CTL_SPEC>;
1048#[doc = "Device Control IN Endpoint x+1 Control Register"]
1049pub mod diep1_ctl;
1050#[doc = "DIEP1_INT register accessor: an alias for `Reg<DIEP1_INT_SPEC>`"]
1051pub type DIEP1_INT = crate::Reg<diep1_int::DIEP1_INT_SPEC>;
1052#[doc = "Device IN Endpoint x+1 Interrupt Register"]
1053pub mod diep1_int;
1054#[doc = "DIEP1_TSIZ register accessor: an alias for `Reg<DIEP1_TSIZ_SPEC>`"]
1055pub type DIEP1_TSIZ = crate::Reg<diep1_tsiz::DIEP1_TSIZ_SPEC>;
1056#[doc = "Device IN Endpoint x+1 Transfer Size Register"]
1057pub mod diep1_tsiz;
1058#[doc = "DIEP1_DMAADDR register accessor: an alias for `Reg<DIEP1_DMAADDR_SPEC>`"]
1059pub type DIEP1_DMAADDR = crate::Reg<diep1_dmaaddr::DIEP1_DMAADDR_SPEC>;
1060#[doc = "Device IN Endpoint x+1 DMA Address Register"]
1061pub mod diep1_dmaaddr;
1062#[doc = "DIEP1_DTXFSTS register accessor: an alias for `Reg<DIEP1_DTXFSTS_SPEC>`"]
1063pub type DIEP1_DTXFSTS = crate::Reg<diep1_dtxfsts::DIEP1_DTXFSTS_SPEC>;
1064#[doc = "Device IN Endpoint Transmit FIFO Status Register 1"]
1065pub mod diep1_dtxfsts;
1066#[doc = "DIEP2_CTL register accessor: an alias for `Reg<DIEP2_CTL_SPEC>`"]
1067pub type DIEP2_CTL = crate::Reg<diep2_ctl::DIEP2_CTL_SPEC>;
1068#[doc = "Device Control IN Endpoint x+1 Control Register"]
1069pub mod diep2_ctl;
1070#[doc = "DIEP2_INT register accessor: an alias for `Reg<DIEP2_INT_SPEC>`"]
1071pub type DIEP2_INT = crate::Reg<diep2_int::DIEP2_INT_SPEC>;
1072#[doc = "Device IN Endpoint x+1 Interrupt Register"]
1073pub mod diep2_int;
1074#[doc = "DIEP2_TSIZ register accessor: an alias for `Reg<DIEP2_TSIZ_SPEC>`"]
1075pub type DIEP2_TSIZ = crate::Reg<diep2_tsiz::DIEP2_TSIZ_SPEC>;
1076#[doc = "Device IN Endpoint x+1 Transfer Size Register"]
1077pub mod diep2_tsiz;
1078#[doc = "DIEP2_DMAADDR register accessor: an alias for `Reg<DIEP2_DMAADDR_SPEC>`"]
1079pub type DIEP2_DMAADDR = crate::Reg<diep2_dmaaddr::DIEP2_DMAADDR_SPEC>;
1080#[doc = "Device IN Endpoint x+1 DMA Address Register"]
1081pub mod diep2_dmaaddr;
1082#[doc = "DIEP2_DTXFSTS register accessor: an alias for `Reg<DIEP2_DTXFSTS_SPEC>`"]
1083pub type DIEP2_DTXFSTS = crate::Reg<diep2_dtxfsts::DIEP2_DTXFSTS_SPEC>;
1084#[doc = "Device IN Endpoint Transmit FIFO Status Register 1"]
1085pub mod diep2_dtxfsts;
1086#[doc = "DIEP3_CTL register accessor: an alias for `Reg<DIEP3_CTL_SPEC>`"]
1087pub type DIEP3_CTL = crate::Reg<diep3_ctl::DIEP3_CTL_SPEC>;
1088#[doc = "Device Control IN Endpoint x+1 Control Register"]
1089pub mod diep3_ctl;
1090#[doc = "DIEP3_INT register accessor: an alias for `Reg<DIEP3_INT_SPEC>`"]
1091pub type DIEP3_INT = crate::Reg<diep3_int::DIEP3_INT_SPEC>;
1092#[doc = "Device IN Endpoint x+1 Interrupt Register"]
1093pub mod diep3_int;
1094#[doc = "DIEP3_TSIZ register accessor: an alias for `Reg<DIEP3_TSIZ_SPEC>`"]
1095pub type DIEP3_TSIZ = crate::Reg<diep3_tsiz::DIEP3_TSIZ_SPEC>;
1096#[doc = "Device IN Endpoint x+1 Transfer Size Register"]
1097pub mod diep3_tsiz;
1098#[doc = "DIEP3_DMAADDR register accessor: an alias for `Reg<DIEP3_DMAADDR_SPEC>`"]
1099pub type DIEP3_DMAADDR = crate::Reg<diep3_dmaaddr::DIEP3_DMAADDR_SPEC>;
1100#[doc = "Device IN Endpoint x+1 DMA Address Register"]
1101pub mod diep3_dmaaddr;
1102#[doc = "DIEP3_DTXFSTS register accessor: an alias for `Reg<DIEP3_DTXFSTS_SPEC>`"]
1103pub type DIEP3_DTXFSTS = crate::Reg<diep3_dtxfsts::DIEP3_DTXFSTS_SPEC>;
1104#[doc = "Device IN Endpoint Transmit FIFO Status Register 1"]
1105pub mod diep3_dtxfsts;
1106#[doc = "DIEP4_CTL register accessor: an alias for `Reg<DIEP4_CTL_SPEC>`"]
1107pub type DIEP4_CTL = crate::Reg<diep4_ctl::DIEP4_CTL_SPEC>;
1108#[doc = "Device Control IN Endpoint x+1 Control Register"]
1109pub mod diep4_ctl;
1110#[doc = "DIEP4_INT register accessor: an alias for `Reg<DIEP4_INT_SPEC>`"]
1111pub type DIEP4_INT = crate::Reg<diep4_int::DIEP4_INT_SPEC>;
1112#[doc = "Device IN Endpoint x+1 Interrupt Register"]
1113pub mod diep4_int;
1114#[doc = "DIEP4_TSIZ register accessor: an alias for `Reg<DIEP4_TSIZ_SPEC>`"]
1115pub type DIEP4_TSIZ = crate::Reg<diep4_tsiz::DIEP4_TSIZ_SPEC>;
1116#[doc = "Device IN Endpoint x+1 Transfer Size Register"]
1117pub mod diep4_tsiz;
1118#[doc = "DIEP4_DMAADDR register accessor: an alias for `Reg<DIEP4_DMAADDR_SPEC>`"]
1119pub type DIEP4_DMAADDR = crate::Reg<diep4_dmaaddr::DIEP4_DMAADDR_SPEC>;
1120#[doc = "Device IN Endpoint x+1 DMA Address Register"]
1121pub mod diep4_dmaaddr;
1122#[doc = "DIEP4_DTXFSTS register accessor: an alias for `Reg<DIEP4_DTXFSTS_SPEC>`"]
1123pub type DIEP4_DTXFSTS = crate::Reg<diep4_dtxfsts::DIEP4_DTXFSTS_SPEC>;
1124#[doc = "Device IN Endpoint Transmit FIFO Status Register 1"]
1125pub mod diep4_dtxfsts;
1126#[doc = "DIEP5_CTL register accessor: an alias for `Reg<DIEP5_CTL_SPEC>`"]
1127pub type DIEP5_CTL = crate::Reg<diep5_ctl::DIEP5_CTL_SPEC>;
1128#[doc = "Device Control IN Endpoint x+1 Control Register"]
1129pub mod diep5_ctl;
1130#[doc = "DIEP5_INT register accessor: an alias for `Reg<DIEP5_INT_SPEC>`"]
1131pub type DIEP5_INT = crate::Reg<diep5_int::DIEP5_INT_SPEC>;
1132#[doc = "Device IN Endpoint x+1 Interrupt Register"]
1133pub mod diep5_int;
1134#[doc = "DIEP5_TSIZ register accessor: an alias for `Reg<DIEP5_TSIZ_SPEC>`"]
1135pub type DIEP5_TSIZ = crate::Reg<diep5_tsiz::DIEP5_TSIZ_SPEC>;
1136#[doc = "Device IN Endpoint x+1 Transfer Size Register"]
1137pub mod diep5_tsiz;
1138#[doc = "DIEP5_DMAADDR register accessor: an alias for `Reg<DIEP5_DMAADDR_SPEC>`"]
1139pub type DIEP5_DMAADDR = crate::Reg<diep5_dmaaddr::DIEP5_DMAADDR_SPEC>;
1140#[doc = "Device IN Endpoint x+1 DMA Address Register"]
1141pub mod diep5_dmaaddr;
1142#[doc = "DIEP5_DTXFSTS register accessor: an alias for `Reg<DIEP5_DTXFSTS_SPEC>`"]
1143pub type DIEP5_DTXFSTS = crate::Reg<diep5_dtxfsts::DIEP5_DTXFSTS_SPEC>;
1144#[doc = "Device IN Endpoint Transmit FIFO Status Register 1"]
1145pub mod diep5_dtxfsts;
1146#[doc = "DOEP0CTL register accessor: an alias for `Reg<DOEP0CTL_SPEC>`"]
1147pub type DOEP0CTL = crate::Reg<doep0ctl::DOEP0CTL_SPEC>;
1148#[doc = "Device Control OUT Endpoint 0 Control Register"]
1149pub mod doep0ctl;
1150#[doc = "DOEP0INT register accessor: an alias for `Reg<DOEP0INT_SPEC>`"]
1151pub type DOEP0INT = crate::Reg<doep0int::DOEP0INT_SPEC>;
1152#[doc = "Device OUT Endpoint 0 Interrupt Register"]
1153pub mod doep0int;
1154#[doc = "DOEP0TSIZ register accessor: an alias for `Reg<DOEP0TSIZ_SPEC>`"]
1155pub type DOEP0TSIZ = crate::Reg<doep0tsiz::DOEP0TSIZ_SPEC>;
1156#[doc = "Device OUT Endpoint 0 Transfer Size Register"]
1157pub mod doep0tsiz;
1158#[doc = "DOEP0DMAADDR register accessor: an alias for `Reg<DOEP0DMAADDR_SPEC>`"]
1159pub type DOEP0DMAADDR = crate::Reg<doep0dmaaddr::DOEP0DMAADDR_SPEC>;
1160#[doc = "Device OUT Endpoint 0 DMA Address Register"]
1161pub mod doep0dmaaddr;
1162#[doc = "DOEP0_CTL register accessor: an alias for `Reg<DOEP0_CTL_SPEC>`"]
1163pub type DOEP0_CTL = crate::Reg<doep0_ctl::DOEP0_CTL_SPEC>;
1164#[doc = "Device Control OUT Endpoint x+1 Control Register"]
1165pub mod doep0_ctl;
1166#[doc = "DOEP0_INT register accessor: an alias for `Reg<DOEP0_INT_SPEC>`"]
1167pub type DOEP0_INT = crate::Reg<doep0_int::DOEP0_INT_SPEC>;
1168#[doc = "Device OUT Endpoint x+1 Interrupt Register"]
1169pub mod doep0_int;
1170#[doc = "DOEP0_TSIZ register accessor: an alias for `Reg<DOEP0_TSIZ_SPEC>`"]
1171pub type DOEP0_TSIZ = crate::Reg<doep0_tsiz::DOEP0_TSIZ_SPEC>;
1172#[doc = "Device OUT Endpoint x+1 Transfer Size Register"]
1173pub mod doep0_tsiz;
1174#[doc = "DOEP0_DMAADDR register accessor: an alias for `Reg<DOEP0_DMAADDR_SPEC>`"]
1175pub type DOEP0_DMAADDR = crate::Reg<doep0_dmaaddr::DOEP0_DMAADDR_SPEC>;
1176#[doc = "Device OUT Endpoint x+1 DMA Address Register"]
1177pub mod doep0_dmaaddr;
1178#[doc = "DOEP1_CTL register accessor: an alias for `Reg<DOEP1_CTL_SPEC>`"]
1179pub type DOEP1_CTL = crate::Reg<doep1_ctl::DOEP1_CTL_SPEC>;
1180#[doc = "Device Control OUT Endpoint x+1 Control Register"]
1181pub mod doep1_ctl;
1182#[doc = "DOEP1_INT register accessor: an alias for `Reg<DOEP1_INT_SPEC>`"]
1183pub type DOEP1_INT = crate::Reg<doep1_int::DOEP1_INT_SPEC>;
1184#[doc = "Device OUT Endpoint x+1 Interrupt Register"]
1185pub mod doep1_int;
1186#[doc = "DOEP1_TSIZ register accessor: an alias for `Reg<DOEP1_TSIZ_SPEC>`"]
1187pub type DOEP1_TSIZ = crate::Reg<doep1_tsiz::DOEP1_TSIZ_SPEC>;
1188#[doc = "Device OUT Endpoint x+1 Transfer Size Register"]
1189pub mod doep1_tsiz;
1190#[doc = "DOEP1_DMAADDR register accessor: an alias for `Reg<DOEP1_DMAADDR_SPEC>`"]
1191pub type DOEP1_DMAADDR = crate::Reg<doep1_dmaaddr::DOEP1_DMAADDR_SPEC>;
1192#[doc = "Device OUT Endpoint x+1 DMA Address Register"]
1193pub mod doep1_dmaaddr;
1194#[doc = "DOEP2_CTL register accessor: an alias for `Reg<DOEP2_CTL_SPEC>`"]
1195pub type DOEP2_CTL = crate::Reg<doep2_ctl::DOEP2_CTL_SPEC>;
1196#[doc = "Device Control OUT Endpoint x+1 Control Register"]
1197pub mod doep2_ctl;
1198#[doc = "DOEP2_INT register accessor: an alias for `Reg<DOEP2_INT_SPEC>`"]
1199pub type DOEP2_INT = crate::Reg<doep2_int::DOEP2_INT_SPEC>;
1200#[doc = "Device OUT Endpoint x+1 Interrupt Register"]
1201pub mod doep2_int;
1202#[doc = "DOEP2_TSIZ register accessor: an alias for `Reg<DOEP2_TSIZ_SPEC>`"]
1203pub type DOEP2_TSIZ = crate::Reg<doep2_tsiz::DOEP2_TSIZ_SPEC>;
1204#[doc = "Device OUT Endpoint x+1 Transfer Size Register"]
1205pub mod doep2_tsiz;
1206#[doc = "DOEP2_DMAADDR register accessor: an alias for `Reg<DOEP2_DMAADDR_SPEC>`"]
1207pub type DOEP2_DMAADDR = crate::Reg<doep2_dmaaddr::DOEP2_DMAADDR_SPEC>;
1208#[doc = "Device OUT Endpoint x+1 DMA Address Register"]
1209pub mod doep2_dmaaddr;
1210#[doc = "DOEP3_CTL register accessor: an alias for `Reg<DOEP3_CTL_SPEC>`"]
1211pub type DOEP3_CTL = crate::Reg<doep3_ctl::DOEP3_CTL_SPEC>;
1212#[doc = "Device Control OUT Endpoint x+1 Control Register"]
1213pub mod doep3_ctl;
1214#[doc = "DOEP3_INT register accessor: an alias for `Reg<DOEP3_INT_SPEC>`"]
1215pub type DOEP3_INT = crate::Reg<doep3_int::DOEP3_INT_SPEC>;
1216#[doc = "Device OUT Endpoint x+1 Interrupt Register"]
1217pub mod doep3_int;
1218#[doc = "DOEP3_TSIZ register accessor: an alias for `Reg<DOEP3_TSIZ_SPEC>`"]
1219pub type DOEP3_TSIZ = crate::Reg<doep3_tsiz::DOEP3_TSIZ_SPEC>;
1220#[doc = "Device OUT Endpoint x+1 Transfer Size Register"]
1221pub mod doep3_tsiz;
1222#[doc = "DOEP3_DMAADDR register accessor: an alias for `Reg<DOEP3_DMAADDR_SPEC>`"]
1223pub type DOEP3_DMAADDR = crate::Reg<doep3_dmaaddr::DOEP3_DMAADDR_SPEC>;
1224#[doc = "Device OUT Endpoint x+1 DMA Address Register"]
1225pub mod doep3_dmaaddr;
1226#[doc = "DOEP4_CTL register accessor: an alias for `Reg<DOEP4_CTL_SPEC>`"]
1227pub type DOEP4_CTL = crate::Reg<doep4_ctl::DOEP4_CTL_SPEC>;
1228#[doc = "Device Control OUT Endpoint x+1 Control Register"]
1229pub mod doep4_ctl;
1230#[doc = "DOEP4_INT register accessor: an alias for `Reg<DOEP4_INT_SPEC>`"]
1231pub type DOEP4_INT = crate::Reg<doep4_int::DOEP4_INT_SPEC>;
1232#[doc = "Device OUT Endpoint x+1 Interrupt Register"]
1233pub mod doep4_int;
1234#[doc = "DOEP4_TSIZ register accessor: an alias for `Reg<DOEP4_TSIZ_SPEC>`"]
1235pub type DOEP4_TSIZ = crate::Reg<doep4_tsiz::DOEP4_TSIZ_SPEC>;
1236#[doc = "Device OUT Endpoint x+1 Transfer Size Register"]
1237pub mod doep4_tsiz;
1238#[doc = "DOEP4_DMAADDR register accessor: an alias for `Reg<DOEP4_DMAADDR_SPEC>`"]
1239pub type DOEP4_DMAADDR = crate::Reg<doep4_dmaaddr::DOEP4_DMAADDR_SPEC>;
1240#[doc = "Device OUT Endpoint x+1 DMA Address Register"]
1241pub mod doep4_dmaaddr;
1242#[doc = "DOEP5_CTL register accessor: an alias for `Reg<DOEP5_CTL_SPEC>`"]
1243pub type DOEP5_CTL = crate::Reg<doep5_ctl::DOEP5_CTL_SPEC>;
1244#[doc = "Device Control OUT Endpoint x+1 Control Register"]
1245pub mod doep5_ctl;
1246#[doc = "DOEP5_INT register accessor: an alias for `Reg<DOEP5_INT_SPEC>`"]
1247pub type DOEP5_INT = crate::Reg<doep5_int::DOEP5_INT_SPEC>;
1248#[doc = "Device OUT Endpoint x+1 Interrupt Register"]
1249pub mod doep5_int;
1250#[doc = "DOEP5_TSIZ register accessor: an alias for `Reg<DOEP5_TSIZ_SPEC>`"]
1251pub type DOEP5_TSIZ = crate::Reg<doep5_tsiz::DOEP5_TSIZ_SPEC>;
1252#[doc = "Device OUT Endpoint x+1 Transfer Size Register"]
1253pub mod doep5_tsiz;
1254#[doc = "DOEP5_DMAADDR register accessor: an alias for `Reg<DOEP5_DMAADDR_SPEC>`"]
1255pub type DOEP5_DMAADDR = crate::Reg<doep5_dmaaddr::DOEP5_DMAADDR_SPEC>;
1256#[doc = "Device OUT Endpoint x+1 DMA Address Register"]
1257pub mod doep5_dmaaddr;
1258#[doc = "PCGCCTL register accessor: an alias for `Reg<PCGCCTL_SPEC>`"]
1259pub type PCGCCTL = crate::Reg<pcgcctl::PCGCCTL_SPEC>;
1260#[doc = "Power and Clock Gating Control Register"]
1261pub mod pcgcctl;