efm32gg11b820_pac/cmu/
dpllctrl.rs

1#[doc = "Register `DPLLCTRL` reader"]
2pub struct R(crate::R<DPLLCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DPLLCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DPLLCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DPLLCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DPLLCTRL` writer"]
17pub struct W(crate::W<DPLLCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DPLLCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DPLLCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DPLLCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MODE` reader - Operating Mode Control"]
38pub type MODE_R = crate::BitReader<bool>;
39#[doc = "Field `MODE` writer - Operating Mode Control"]
40pub type MODE_W<'a> = crate::BitWriter<'a, u32, DPLLCTRL_SPEC, bool, 0>;
41#[doc = "Field `EDGESEL` reader - Reference Edge Select"]
42pub type EDGESEL_R = crate::BitReader<bool>;
43#[doc = "Field `EDGESEL` writer - Reference Edge Select"]
44pub type EDGESEL_W<'a> = crate::BitWriter<'a, u32, DPLLCTRL_SPEC, bool, 1>;
45#[doc = "Field `AUTORECOVER` reader - Automatic Recovery Ctrl"]
46pub type AUTORECOVER_R = crate::BitReader<bool>;
47#[doc = "Field `AUTORECOVER` writer - Automatic Recovery Ctrl"]
48pub type AUTORECOVER_W<'a> = crate::BitWriter<'a, u32, DPLLCTRL_SPEC, bool, 2>;
49#[doc = "Reference Clock Selection Control\n\nValue on reset: 0"]
50#[derive(Clone, Copy, Debug, PartialEq)]
51#[repr(u8)]
52pub enum REFSEL_A {
53    #[doc = "0: HFXO selected"]
54    HFXO = 0,
55    #[doc = "1: LFXO selected"]
56    LFXO = 1,
57    #[doc = "2: USHFRCO selected"]
58    USHFRCO = 2,
59    #[doc = "3: CLKIN0 selected"]
60    CLKIN0 = 3,
61}
62impl From<REFSEL_A> for u8 {
63    #[inline(always)]
64    fn from(variant: REFSEL_A) -> Self {
65        variant as _
66    }
67}
68#[doc = "Field `REFSEL` reader - Reference Clock Selection Control"]
69pub type REFSEL_R = crate::FieldReader<u8, REFSEL_A>;
70impl REFSEL_R {
71    #[doc = "Get enumerated values variant"]
72    #[inline(always)]
73    pub fn variant(&self) -> REFSEL_A {
74        match self.bits {
75            0 => REFSEL_A::HFXO,
76            1 => REFSEL_A::LFXO,
77            2 => REFSEL_A::USHFRCO,
78            3 => REFSEL_A::CLKIN0,
79            _ => unreachable!(),
80        }
81    }
82    #[doc = "Checks if the value of the field is `HFXO`"]
83    #[inline(always)]
84    pub fn is_hfxo(&self) -> bool {
85        *self == REFSEL_A::HFXO
86    }
87    #[doc = "Checks if the value of the field is `LFXO`"]
88    #[inline(always)]
89    pub fn is_lfxo(&self) -> bool {
90        *self == REFSEL_A::LFXO
91    }
92    #[doc = "Checks if the value of the field is `USHFRCO`"]
93    #[inline(always)]
94    pub fn is_ushfrco(&self) -> bool {
95        *self == REFSEL_A::USHFRCO
96    }
97    #[doc = "Checks if the value of the field is `CLKIN0`"]
98    #[inline(always)]
99    pub fn is_clkin0(&self) -> bool {
100        *self == REFSEL_A::CLKIN0
101    }
102}
103#[doc = "Field `REFSEL` writer - Reference Clock Selection Control"]
104pub type REFSEL_W<'a> = crate::FieldWriterSafe<'a, u32, DPLLCTRL_SPEC, u8, REFSEL_A, 2, 3>;
105impl<'a> REFSEL_W<'a> {
106    #[doc = "HFXO selected"]
107    #[inline(always)]
108    pub fn hfxo(self) -> &'a mut W {
109        self.variant(REFSEL_A::HFXO)
110    }
111    #[doc = "LFXO selected"]
112    #[inline(always)]
113    pub fn lfxo(self) -> &'a mut W {
114        self.variant(REFSEL_A::LFXO)
115    }
116    #[doc = "USHFRCO selected"]
117    #[inline(always)]
118    pub fn ushfrco(self) -> &'a mut W {
119        self.variant(REFSEL_A::USHFRCO)
120    }
121    #[doc = "CLKIN0 selected"]
122    #[inline(always)]
123    pub fn clkin0(self) -> &'a mut W {
124        self.variant(REFSEL_A::CLKIN0)
125    }
126}
127#[doc = "Field `DITHEN` reader - Dither Enable Control"]
128pub type DITHEN_R = crate::BitReader<bool>;
129#[doc = "Field `DITHEN` writer - Dither Enable Control"]
130pub type DITHEN_W<'a> = crate::BitWriter<'a, u32, DPLLCTRL_SPEC, bool, 6>;
131impl R {
132    #[doc = "Bit 0 - Operating Mode Control"]
133    #[inline(always)]
134    pub fn mode(&self) -> MODE_R {
135        MODE_R::new((self.bits & 1) != 0)
136    }
137    #[doc = "Bit 1 - Reference Edge Select"]
138    #[inline(always)]
139    pub fn edgesel(&self) -> EDGESEL_R {
140        EDGESEL_R::new(((self.bits >> 1) & 1) != 0)
141    }
142    #[doc = "Bit 2 - Automatic Recovery Ctrl"]
143    #[inline(always)]
144    pub fn autorecover(&self) -> AUTORECOVER_R {
145        AUTORECOVER_R::new(((self.bits >> 2) & 1) != 0)
146    }
147    #[doc = "Bits 3:4 - Reference Clock Selection Control"]
148    #[inline(always)]
149    pub fn refsel(&self) -> REFSEL_R {
150        REFSEL_R::new(((self.bits >> 3) & 3) as u8)
151    }
152    #[doc = "Bit 6 - Dither Enable Control"]
153    #[inline(always)]
154    pub fn dithen(&self) -> DITHEN_R {
155        DITHEN_R::new(((self.bits >> 6) & 1) != 0)
156    }
157}
158impl W {
159    #[doc = "Bit 0 - Operating Mode Control"]
160    #[inline(always)]
161    pub fn mode(&mut self) -> MODE_W {
162        MODE_W::new(self)
163    }
164    #[doc = "Bit 1 - Reference Edge Select"]
165    #[inline(always)]
166    pub fn edgesel(&mut self) -> EDGESEL_W {
167        EDGESEL_W::new(self)
168    }
169    #[doc = "Bit 2 - Automatic Recovery Ctrl"]
170    #[inline(always)]
171    pub fn autorecover(&mut self) -> AUTORECOVER_W {
172        AUTORECOVER_W::new(self)
173    }
174    #[doc = "Bits 3:4 - Reference Clock Selection Control"]
175    #[inline(always)]
176    pub fn refsel(&mut self) -> REFSEL_W {
177        REFSEL_W::new(self)
178    }
179    #[doc = "Bit 6 - Dither Enable Control"]
180    #[inline(always)]
181    pub fn dithen(&mut self) -> DITHEN_W {
182        DITHEN_W::new(self)
183    }
184    #[doc = "Writes raw bits to the register."]
185    #[inline(always)]
186    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
187        self.0.bits(bits);
188        self
189    }
190}
191#[doc = "DPLL Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrl](index.html) module"]
192pub struct DPLLCTRL_SPEC;
193impl crate::RegisterSpec for DPLLCTRL_SPEC {
194    type Ux = u32;
195}
196#[doc = "`read()` method returns [dpllctrl::R](R) reader structure"]
197impl crate::Readable for DPLLCTRL_SPEC {
198    type Reader = R;
199}
200#[doc = "`write(|w| ..)` method takes [dpllctrl::W](W) writer structure"]
201impl crate::Writable for DPLLCTRL_SPEC {
202    type Writer = W;
203}
204#[doc = "`reset()` method sets DPLLCTRL to value 0"]
205impl crate::Resettable for DPLLCTRL_SPEC {
206    #[inline(always)]
207    fn reset_value() -> Self::Ux {
208        0
209    }
210}
efm32gg11b820_pac/cmu/dpllctrl.rs

efm32gg11b820_pac/cmu/
dpllctrl.rs
