efm32gg11b820_pac/cmu/
hfbusclken0.rs1#[doc = "Register `HFBUSCLKEN0` reader"]
2pub struct R(crate::R<HFBUSCLKEN0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<HFBUSCLKEN0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<HFBUSCLKEN0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<HFBUSCLKEN0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `HFBUSCLKEN0` writer"]
17pub struct W(crate::W<HFBUSCLKEN0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<HFBUSCLKEN0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<HFBUSCLKEN0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<HFBUSCLKEN0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `LE` reader - Low Energy Peripheral Interface Clock Enable"]
38pub type LE_R = crate::BitReader<bool>;
39#[doc = "Field `LE` writer - Low Energy Peripheral Interface Clock Enable"]
40pub type LE_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 0>;
41#[doc = "Field `CRYPTO0` reader - Advanced Encryption Standard Accelerator Clock Enable"]
42pub type CRYPTO0_R = crate::BitReader<bool>;
43#[doc = "Field `CRYPTO0` writer - Advanced Encryption Standard Accelerator Clock Enable"]
44pub type CRYPTO0_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 1>;
45#[doc = "Field `EBI` reader - External Bus Interface Clock Enable"]
46pub type EBI_R = crate::BitReader<bool>;
47#[doc = "Field `EBI` writer - External Bus Interface Clock Enable"]
48pub type EBI_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 2>;
49#[doc = "Field `ETH` reader - Ethernet Controller Clock Enable"]
50pub type ETH_R = crate::BitReader<bool>;
51#[doc = "Field `ETH` writer - Ethernet Controller Clock Enable"]
52pub type ETH_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 3>;
53#[doc = "Field `SDIO` reader - SDIO Controller Clock Enable"]
54pub type SDIO_R = crate::BitReader<bool>;
55#[doc = "Field `SDIO` writer - SDIO Controller Clock Enable"]
56pub type SDIO_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 4>;
57#[doc = "Field `GPIO` reader - General purpose Input/Output Clock Enable"]
58pub type GPIO_R = crate::BitReader<bool>;
59#[doc = "Field `GPIO` writer - General purpose Input/Output Clock Enable"]
60pub type GPIO_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 5>;
61#[doc = "Field `PRS` reader - Peripheral Reflex System Clock Enable"]
62pub type PRS_R = crate::BitReader<bool>;
63#[doc = "Field `PRS` writer - Peripheral Reflex System Clock Enable"]
64pub type PRS_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 6>;
65#[doc = "Field `LDMA` reader - Linked Direct Memory Access Controller Clock Enable"]
66pub type LDMA_R = crate::BitReader<bool>;
67#[doc = "Field `LDMA` writer - Linked Direct Memory Access Controller Clock Enable"]
68pub type LDMA_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 7>;
69#[doc = "Field `GPCRC` reader - General Purpose CRC Clock Enable"]
70pub type GPCRC_R = crate::BitReader<bool>;
71#[doc = "Field `GPCRC` writer - General Purpose CRC Clock Enable"]
72pub type GPCRC_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 8>;
73#[doc = "Field `QSPI0` reader - Quad-SPI Clock Enable"]
74pub type QSPI0_R = crate::BitReader<bool>;
75#[doc = "Field `QSPI0` writer - Quad-SPI Clock Enable"]
76pub type QSPI0_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 9>;
77#[doc = "Field `USB` reader - Universal Serial Bus Interface Clock Enable"]
78pub type USB_R = crate::BitReader<bool>;
79#[doc = "Field `USB` writer - Universal Serial Bus Interface Clock Enable"]
80pub type USB_W<'a> = crate::BitWriter<'a, u32, HFBUSCLKEN0_SPEC, bool, 10>;
81impl R {
82 #[doc = "Bit 0 - Low Energy Peripheral Interface Clock Enable"]
83 #[inline(always)]
84 pub fn le(&self) -> LE_R {
85 LE_R::new((self.bits & 1) != 0)
86 }
87 #[doc = "Bit 1 - Advanced Encryption Standard Accelerator Clock Enable"]
88 #[inline(always)]
89 pub fn crypto0(&self) -> CRYPTO0_R {
90 CRYPTO0_R::new(((self.bits >> 1) & 1) != 0)
91 }
92 #[doc = "Bit 2 - External Bus Interface Clock Enable"]
93 #[inline(always)]
94 pub fn ebi(&self) -> EBI_R {
95 EBI_R::new(((self.bits >> 2) & 1) != 0)
96 }
97 #[doc = "Bit 3 - Ethernet Controller Clock Enable"]
98 #[inline(always)]
99 pub fn eth(&self) -> ETH_R {
100 ETH_R::new(((self.bits >> 3) & 1) != 0)
101 }
102 #[doc = "Bit 4 - SDIO Controller Clock Enable"]
103 #[inline(always)]
104 pub fn sdio(&self) -> SDIO_R {
105 SDIO_R::new(((self.bits >> 4) & 1) != 0)
106 }
107 #[doc = "Bit 5 - General purpose Input/Output Clock Enable"]
108 #[inline(always)]
109 pub fn gpio(&self) -> GPIO_R {
110 GPIO_R::new(((self.bits >> 5) & 1) != 0)
111 }
112 #[doc = "Bit 6 - Peripheral Reflex System Clock Enable"]
113 #[inline(always)]
114 pub fn prs(&self) -> PRS_R {
115 PRS_R::new(((self.bits >> 6) & 1) != 0)
116 }
117 #[doc = "Bit 7 - Linked Direct Memory Access Controller Clock Enable"]
118 #[inline(always)]
119 pub fn ldma(&self) -> LDMA_R {
120 LDMA_R::new(((self.bits >> 7) & 1) != 0)
121 }
122 #[doc = "Bit 8 - General Purpose CRC Clock Enable"]
123 #[inline(always)]
124 pub fn gpcrc(&self) -> GPCRC_R {
125 GPCRC_R::new(((self.bits >> 8) & 1) != 0)
126 }
127 #[doc = "Bit 9 - Quad-SPI Clock Enable"]
128 #[inline(always)]
129 pub fn qspi0(&self) -> QSPI0_R {
130 QSPI0_R::new(((self.bits >> 9) & 1) != 0)
131 }
132 #[doc = "Bit 10 - Universal Serial Bus Interface Clock Enable"]
133 #[inline(always)]
134 pub fn usb(&self) -> USB_R {
135 USB_R::new(((self.bits >> 10) & 1) != 0)
136 }
137}
138impl W {
139 #[doc = "Bit 0 - Low Energy Peripheral Interface Clock Enable"]
140 #[inline(always)]
141 pub fn le(&mut self) -> LE_W {
142 LE_W::new(self)
143 }
144 #[doc = "Bit 1 - Advanced Encryption Standard Accelerator Clock Enable"]
145 #[inline(always)]
146 pub fn crypto0(&mut self) -> CRYPTO0_W {
147 CRYPTO0_W::new(self)
148 }
149 #[doc = "Bit 2 - External Bus Interface Clock Enable"]
150 #[inline(always)]
151 pub fn ebi(&mut self) -> EBI_W {
152 EBI_W::new(self)
153 }
154 #[doc = "Bit 3 - Ethernet Controller Clock Enable"]
155 #[inline(always)]
156 pub fn eth(&mut self) -> ETH_W {
157 ETH_W::new(self)
158 }
159 #[doc = "Bit 4 - SDIO Controller Clock Enable"]
160 #[inline(always)]
161 pub fn sdio(&mut self) -> SDIO_W {
162 SDIO_W::new(self)
163 }
164 #[doc = "Bit 5 - General purpose Input/Output Clock Enable"]
165 #[inline(always)]
166 pub fn gpio(&mut self) -> GPIO_W {
167 GPIO_W::new(self)
168 }
169 #[doc = "Bit 6 - Peripheral Reflex System Clock Enable"]
170 #[inline(always)]
171 pub fn prs(&mut self) -> PRS_W {
172 PRS_W::new(self)
173 }
174 #[doc = "Bit 7 - Linked Direct Memory Access Controller Clock Enable"]
175 #[inline(always)]
176 pub fn ldma(&mut self) -> LDMA_W {
177 LDMA_W::new(self)
178 }
179 #[doc = "Bit 8 - General Purpose CRC Clock Enable"]
180 #[inline(always)]
181 pub fn gpcrc(&mut self) -> GPCRC_W {
182 GPCRC_W::new(self)
183 }
184 #[doc = "Bit 9 - Quad-SPI Clock Enable"]
185 #[inline(always)]
186 pub fn qspi0(&mut self) -> QSPI0_W {
187 QSPI0_W::new(self)
188 }
189 #[doc = "Bit 10 - Universal Serial Bus Interface Clock Enable"]
190 #[inline(always)]
191 pub fn usb(&mut self) -> USB_W {
192 USB_W::new(self)
193 }
194 #[doc = "Writes raw bits to the register."]
195 #[inline(always)]
196 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
197 self.0.bits(bits);
198 self
199 }
200}
201#[doc = "High Frequency Bus Clock Enable Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfbusclken0](index.html) module"]
202pub struct HFBUSCLKEN0_SPEC;
203impl crate::RegisterSpec for HFBUSCLKEN0_SPEC {
204 type Ux = u32;
205}
206#[doc = "`read()` method returns [hfbusclken0::R](R) reader structure"]
207impl crate::Readable for HFBUSCLKEN0_SPEC {
208 type Reader = R;
209}
210#[doc = "`write(|w| ..)` method takes [hfbusclken0::W](W) writer structure"]
211impl crate::Writable for HFBUSCLKEN0_SPEC {
212 type Writer = W;
213}
214#[doc = "`reset()` method sets HFBUSCLKEN0 to value 0"]
215impl crate::Resettable for HFBUSCLKEN0_SPEC {
216 #[inline(always)]
217 fn reset_value() -> Self::Ux {
218 0
219 }
220}