efm32gg11b510_pac/vdac0/
if_.rs

1#[doc = "Register `IF` reader"]
2pub struct R(crate::R<IF_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<IF_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<IF_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<IF_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `CH0CD` reader - Channel 0 Conversion Done Interrupt Flag"]
17pub type CH0CD_R = crate::BitReader<bool>;
18#[doc = "Field `CH1CD` reader - Channel 1 Conversion Done Interrupt Flag"]
19pub type CH1CD_R = crate::BitReader<bool>;
20#[doc = "Field `CH0OF` reader - Channel 0 Data Overflow Interrupt Flag"]
21pub type CH0OF_R = crate::BitReader<bool>;
22#[doc = "Field `CH1OF` reader - Channel 1 Data Overflow Interrupt Flag"]
23pub type CH1OF_R = crate::BitReader<bool>;
24#[doc = "Field `CH0UF` reader - Channel 0 Data Underflow Interrupt Flag"]
25pub type CH0UF_R = crate::BitReader<bool>;
26#[doc = "Field `CH1UF` reader - Channel 1 Data Underflow Interrupt Flag"]
27pub type CH1UF_R = crate::BitReader<bool>;
28#[doc = "Field `CH0BL` reader - Channel 0 Buffer Level Interrupt Flag"]
29pub type CH0BL_R = crate::BitReader<bool>;
30#[doc = "Field `CH1BL` reader - Channel 1 Buffer Level Interrupt Flag"]
31pub type CH1BL_R = crate::BitReader<bool>;
32#[doc = "Field `EM23ERR` reader - EM2/3 Entry Error Flag"]
33pub type EM23ERR_R = crate::BitReader<bool>;
34#[doc = "Field `OPA0APORTCONFLICT` reader - OPA0 Bus Conflict Output Interrupt Flag"]
35pub type OPA0APORTCONFLICT_R = crate::BitReader<bool>;
36#[doc = "Field `OPA1APORTCONFLICT` reader - OPA1 Bus Conflict Output Interrupt Flag"]
37pub type OPA1APORTCONFLICT_R = crate::BitReader<bool>;
38#[doc = "Field `OPA2APORTCONFLICT` reader - OPA2 Bus Conflict Output Interrupt Flag"]
39pub type OPA2APORTCONFLICT_R = crate::BitReader<bool>;
40#[doc = "Field `OPA3APORTCONFLICT` reader - OPA3 Bus Conflict Output Interrupt Flag"]
41pub type OPA3APORTCONFLICT_R = crate::BitReader<bool>;
42#[doc = "Field `OPA0PRSTIMEDERR` reader - OPA0 PRS Trigger Mode Error Interrupt Flag"]
43pub type OPA0PRSTIMEDERR_R = crate::BitReader<bool>;
44#[doc = "Field `OPA1PRSTIMEDERR` reader - OPA1 PRS Trigger Mode Error Interrupt Flag"]
45pub type OPA1PRSTIMEDERR_R = crate::BitReader<bool>;
46#[doc = "Field `OPA2PRSTIMEDERR` reader - OPA2 PRS Trigger Mode Error Interrupt Flag"]
47pub type OPA2PRSTIMEDERR_R = crate::BitReader<bool>;
48#[doc = "Field `OPA3PRSTIMEDERR` reader - OPA3 PRS Trigger Mode Error Interrupt Flag"]
49pub type OPA3PRSTIMEDERR_R = crate::BitReader<bool>;
50#[doc = "Field `OPA0OUTVALID` reader - OPA0 Output Valid Interrupt Flag"]
51pub type OPA0OUTVALID_R = crate::BitReader<bool>;
52#[doc = "Field `OPA1OUTVALID` reader - OPA1 Output Valid Interrupt Flag"]
53pub type OPA1OUTVALID_R = crate::BitReader<bool>;
54#[doc = "Field `OPA2OUTVALID` reader - OPA3 Output Valid Interrupt Flag"]
55pub type OPA2OUTVALID_R = crate::BitReader<bool>;
56#[doc = "Field `OPA3OUTVALID` reader - OPA3 Output Valid Interrupt Flag"]
57pub type OPA3OUTVALID_R = crate::BitReader<bool>;
58impl R {
59    #[doc = "Bit 0 - Channel 0 Conversion Done Interrupt Flag"]
60    #[inline(always)]
61    pub fn ch0cd(&self) -> CH0CD_R {
62        CH0CD_R::new((self.bits & 1) != 0)
63    }
64    #[doc = "Bit 1 - Channel 1 Conversion Done Interrupt Flag"]
65    #[inline(always)]
66    pub fn ch1cd(&self) -> CH1CD_R {
67        CH1CD_R::new(((self.bits >> 1) & 1) != 0)
68    }
69    #[doc = "Bit 2 - Channel 0 Data Overflow Interrupt Flag"]
70    #[inline(always)]
71    pub fn ch0of(&self) -> CH0OF_R {
72        CH0OF_R::new(((self.bits >> 2) & 1) != 0)
73    }
74    #[doc = "Bit 3 - Channel 1 Data Overflow Interrupt Flag"]
75    #[inline(always)]
76    pub fn ch1of(&self) -> CH1OF_R {
77        CH1OF_R::new(((self.bits >> 3) & 1) != 0)
78    }
79    #[doc = "Bit 4 - Channel 0 Data Underflow Interrupt Flag"]
80    #[inline(always)]
81    pub fn ch0uf(&self) -> CH0UF_R {
82        CH0UF_R::new(((self.bits >> 4) & 1) != 0)
83    }
84    #[doc = "Bit 5 - Channel 1 Data Underflow Interrupt Flag"]
85    #[inline(always)]
86    pub fn ch1uf(&self) -> CH1UF_R {
87        CH1UF_R::new(((self.bits >> 5) & 1) != 0)
88    }
89    #[doc = "Bit 6 - Channel 0 Buffer Level Interrupt Flag"]
90    #[inline(always)]
91    pub fn ch0bl(&self) -> CH0BL_R {
92        CH0BL_R::new(((self.bits >> 6) & 1) != 0)
93    }
94    #[doc = "Bit 7 - Channel 1 Buffer Level Interrupt Flag"]
95    #[inline(always)]
96    pub fn ch1bl(&self) -> CH1BL_R {
97        CH1BL_R::new(((self.bits >> 7) & 1) != 0)
98    }
99    #[doc = "Bit 15 - EM2/3 Entry Error Flag"]
100    #[inline(always)]
101    pub fn em23err(&self) -> EM23ERR_R {
102        EM23ERR_R::new(((self.bits >> 15) & 1) != 0)
103    }
104    #[doc = "Bit 16 - OPA0 Bus Conflict Output Interrupt Flag"]
105    #[inline(always)]
106    pub fn opa0aportconflict(&self) -> OPA0APORTCONFLICT_R {
107        OPA0APORTCONFLICT_R::new(((self.bits >> 16) & 1) != 0)
108    }
109    #[doc = "Bit 17 - OPA1 Bus Conflict Output Interrupt Flag"]
110    #[inline(always)]
111    pub fn opa1aportconflict(&self) -> OPA1APORTCONFLICT_R {
112        OPA1APORTCONFLICT_R::new(((self.bits >> 17) & 1) != 0)
113    }
114    #[doc = "Bit 18 - OPA2 Bus Conflict Output Interrupt Flag"]
115    #[inline(always)]
116    pub fn opa2aportconflict(&self) -> OPA2APORTCONFLICT_R {
117        OPA2APORTCONFLICT_R::new(((self.bits >> 18) & 1) != 0)
118    }
119    #[doc = "Bit 19 - OPA3 Bus Conflict Output Interrupt Flag"]
120    #[inline(always)]
121    pub fn opa3aportconflict(&self) -> OPA3APORTCONFLICT_R {
122        OPA3APORTCONFLICT_R::new(((self.bits >> 19) & 1) != 0)
123    }
124    #[doc = "Bit 20 - OPA0 PRS Trigger Mode Error Interrupt Flag"]
125    #[inline(always)]
126    pub fn opa0prstimederr(&self) -> OPA0PRSTIMEDERR_R {
127        OPA0PRSTIMEDERR_R::new(((self.bits >> 20) & 1) != 0)
128    }
129    #[doc = "Bit 21 - OPA1 PRS Trigger Mode Error Interrupt Flag"]
130    #[inline(always)]
131    pub fn opa1prstimederr(&self) -> OPA1PRSTIMEDERR_R {
132        OPA1PRSTIMEDERR_R::new(((self.bits >> 21) & 1) != 0)
133    }
134    #[doc = "Bit 22 - OPA2 PRS Trigger Mode Error Interrupt Flag"]
135    #[inline(always)]
136    pub fn opa2prstimederr(&self) -> OPA2PRSTIMEDERR_R {
137        OPA2PRSTIMEDERR_R::new(((self.bits >> 22) & 1) != 0)
138    }
139    #[doc = "Bit 23 - OPA3 PRS Trigger Mode Error Interrupt Flag"]
140    #[inline(always)]
141    pub fn opa3prstimederr(&self) -> OPA3PRSTIMEDERR_R {
142        OPA3PRSTIMEDERR_R::new(((self.bits >> 23) & 1) != 0)
143    }
144    #[doc = "Bit 28 - OPA0 Output Valid Interrupt Flag"]
145    #[inline(always)]
146    pub fn opa0outvalid(&self) -> OPA0OUTVALID_R {
147        OPA0OUTVALID_R::new(((self.bits >> 28) & 1) != 0)
148    }
149    #[doc = "Bit 29 - OPA1 Output Valid Interrupt Flag"]
150    #[inline(always)]
151    pub fn opa1outvalid(&self) -> OPA1OUTVALID_R {
152        OPA1OUTVALID_R::new(((self.bits >> 29) & 1) != 0)
153    }
154    #[doc = "Bit 30 - OPA3 Output Valid Interrupt Flag"]
155    #[inline(always)]
156    pub fn opa2outvalid(&self) -> OPA2OUTVALID_R {
157        OPA2OUTVALID_R::new(((self.bits >> 30) & 1) != 0)
158    }
159    #[doc = "Bit 31 - OPA3 Output Valid Interrupt Flag"]
160    #[inline(always)]
161    pub fn opa3outvalid(&self) -> OPA3OUTVALID_R {
162        OPA3OUTVALID_R::new(((self.bits >> 31) & 1) != 0)
163    }
164}
165#[doc = "Interrupt Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [if_](index.html) module"]
166pub struct IF_SPEC;
167impl crate::RegisterSpec for IF_SPEC {
168    type Ux = u32;
169}
170#[doc = "`read()` method returns [if_::R](R) reader structure"]
171impl crate::Readable for IF_SPEC {
172    type Reader = R;
173}
174#[doc = "`reset()` method sets IF to value 0xc0"]
175impl crate::Resettable for IF_SPEC {
176    #[inline(always)]
177    fn reset_value() -> Self::Ux {
178        0xc0
179    }
180}
efm32gg11b510_pac/vdac0/if_.rs

efm32gg11b510_pac/vdac0/
if_.rs
