1#[doc = "Register `PPUPATD0` reader"]
2pub struct R(crate::R<PPUPATD0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<PPUPATD0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<PPUPATD0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<PPUPATD0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `PPUPATD0` writer"]
17pub struct W(crate::W<PPUPATD0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<PPUPATD0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<PPUPATD0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<PPUPATD0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `ACMP0` reader - Analog Comparator 0 access control bit"]
38pub type ACMP0_R = crate::BitReader<bool>;
39#[doc = "Field `ACMP0` writer - Analog Comparator 0 access control bit"]
40pub type ACMP0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 0>;
41#[doc = "Field `ACMP1` reader - Analog Comparator 1 access control bit"]
42pub type ACMP1_R = crate::BitReader<bool>;
43#[doc = "Field `ACMP1` writer - Analog Comparator 1 access control bit"]
44pub type ACMP1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 1>;
45#[doc = "Field `ACMP2` reader - Analog Comparator 1 access control bit"]
46pub type ACMP2_R = crate::BitReader<bool>;
47#[doc = "Field `ACMP2` writer - Analog Comparator 1 access control bit"]
48pub type ACMP2_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 2>;
49#[doc = "Field `ACMP3` reader - Analog Comparator 3 access control bit"]
50pub type ACMP3_R = crate::BitReader<bool>;
51#[doc = "Field `ACMP3` writer - Analog Comparator 3 access control bit"]
52pub type ACMP3_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 3>;
53#[doc = "Field `ADC0` reader - Analog to Digital Converter 0 access control bit"]
54pub type ADC0_R = crate::BitReader<bool>;
55#[doc = "Field `ADC0` writer - Analog to Digital Converter 0 access control bit"]
56pub type ADC0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 4>;
57#[doc = "Field `ADC1` reader - Analog to Digital Converter 0 access control bit"]
58pub type ADC1_R = crate::BitReader<bool>;
59#[doc = "Field `ADC1` writer - Analog to Digital Converter 0 access control bit"]
60pub type ADC1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 5>;
61#[doc = "Field `CAN0` reader - CAN 0 access control bit"]
62pub type CAN0_R = crate::BitReader<bool>;
63#[doc = "Field `CAN0` writer - CAN 0 access control bit"]
64pub type CAN0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 6>;
65#[doc = "Field `CAN1` reader - CAN 1 access control bit"]
66pub type CAN1_R = crate::BitReader<bool>;
67#[doc = "Field `CAN1` writer - CAN 1 access control bit"]
68pub type CAN1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 7>;
69#[doc = "Field `CMU` reader - Clock Management Unit access control bit"]
70pub type CMU_R = crate::BitReader<bool>;
71#[doc = "Field `CMU` writer - Clock Management Unit access control bit"]
72pub type CMU_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 8>;
73#[doc = "Field `CRYOTIMER` reader - CRYOTIMER access control bit"]
74pub type CRYOTIMER_R = crate::BitReader<bool>;
75#[doc = "Field `CRYOTIMER` writer - CRYOTIMER access control bit"]
76pub type CRYOTIMER_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 9>;
77#[doc = "Field `CRYPTO0` reader - Advanced Encryption Standard Accelerator access control bit"]
78pub type CRYPTO0_R = crate::BitReader<bool>;
79#[doc = "Field `CRYPTO0` writer - Advanced Encryption Standard Accelerator access control bit"]
80pub type CRYPTO0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 10>;
81#[doc = "Field `CSEN` reader - Capacitive touch sense module access control bit"]
82pub type CSEN_R = crate::BitReader<bool>;
83#[doc = "Field `CSEN` writer - Capacitive touch sense module access control bit"]
84pub type CSEN_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 11>;
85#[doc = "Field `VDAC0` reader - Digital to Analog Converter 0 access control bit"]
86pub type VDAC0_R = crate::BitReader<bool>;
87#[doc = "Field `VDAC0` writer - Digital to Analog Converter 0 access control bit"]
88pub type VDAC0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 12>;
89#[doc = "Field `PRS` reader - Peripheral Reflex System access control bit"]
90pub type PRS_R = crate::BitReader<bool>;
91#[doc = "Field `PRS` writer - Peripheral Reflex System access control bit"]
92pub type PRS_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 13>;
93#[doc = "Field `EBI` reader - External Bus Interface access control bit"]
94pub type EBI_R = crate::BitReader<bool>;
95#[doc = "Field `EBI` writer - External Bus Interface access control bit"]
96pub type EBI_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 14>;
97#[doc = "Field `EMU` reader - Energy Management Unit access control bit"]
98pub type EMU_R = crate::BitReader<bool>;
99#[doc = "Field `EMU` writer - Energy Management Unit access control bit"]
100pub type EMU_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 15>;
101#[doc = "Field `FPUEH` reader - FPU Exception Handler access control bit"]
102pub type FPUEH_R = crate::BitReader<bool>;
103#[doc = "Field `FPUEH` writer - FPU Exception Handler access control bit"]
104pub type FPUEH_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 17>;
105#[doc = "Field `GPCRC` reader - General Purpose CRC access control bit"]
106pub type GPCRC_R = crate::BitReader<bool>;
107#[doc = "Field `GPCRC` writer - General Purpose CRC access control bit"]
108pub type GPCRC_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 18>;
109#[doc = "Field `GPIO` reader - General purpose Input/Output access control bit"]
110pub type GPIO_R = crate::BitReader<bool>;
111#[doc = "Field `GPIO` writer - General purpose Input/Output access control bit"]
112pub type GPIO_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 19>;
113#[doc = "Field `I2C0` reader - I2C 0 access control bit"]
114pub type I2C0_R = crate::BitReader<bool>;
115#[doc = "Field `I2C0` writer - I2C 0 access control bit"]
116pub type I2C0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 20>;
117#[doc = "Field `I2C1` reader - I2C 1 access control bit"]
118pub type I2C1_R = crate::BitReader<bool>;
119#[doc = "Field `I2C1` writer - I2C 1 access control bit"]
120pub type I2C1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 21>;
121#[doc = "Field `I2C2` reader - I2C 2 access control bit"]
122pub type I2C2_R = crate::BitReader<bool>;
123#[doc = "Field `I2C2` writer - I2C 2 access control bit"]
124pub type I2C2_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 22>;
125#[doc = "Field `IDAC0` reader - Current Digital to Analog Converter 0 access control bit"]
126pub type IDAC0_R = crate::BitReader<bool>;
127#[doc = "Field `IDAC0` writer - Current Digital to Analog Converter 0 access control bit"]
128pub type IDAC0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 23>;
129#[doc = "Field `MSC` reader - Memory System Controller access control bit"]
130pub type MSC_R = crate::BitReader<bool>;
131#[doc = "Field `MSC` writer - Memory System Controller access control bit"]
132pub type MSC_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 24>;
133#[doc = "Field `LCD` reader - Liquid Crystal Display Controller access control bit"]
134pub type LCD_R = crate::BitReader<bool>;
135#[doc = "Field `LCD` writer - Liquid Crystal Display Controller access control bit"]
136pub type LCD_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 25>;
137#[doc = "Field `LDMA` reader - Linked Direct Memory Access Controller access control bit"]
138pub type LDMA_R = crate::BitReader<bool>;
139#[doc = "Field `LDMA` writer - Linked Direct Memory Access Controller access control bit"]
140pub type LDMA_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 26>;
141#[doc = "Field `LESENSE` reader - Low Energy Sensor Interface access control bit"]
142pub type LESENSE_R = crate::BitReader<bool>;
143#[doc = "Field `LESENSE` writer - Low Energy Sensor Interface access control bit"]
144pub type LESENSE_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 27>;
145#[doc = "Field `LETIMER0` reader - Low Energy Timer 0 access control bit"]
146pub type LETIMER0_R = crate::BitReader<bool>;
147#[doc = "Field `LETIMER0` writer - Low Energy Timer 0 access control bit"]
148pub type LETIMER0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 28>;
149#[doc = "Field `LETIMER1` reader - Low Energy Timer 1 access control bit"]
150pub type LETIMER1_R = crate::BitReader<bool>;
151#[doc = "Field `LETIMER1` writer - Low Energy Timer 1 access control bit"]
152pub type LETIMER1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 29>;
153#[doc = "Field `LEUART0` reader - Low Energy UART 0 access control bit"]
154pub type LEUART0_R = crate::BitReader<bool>;
155#[doc = "Field `LEUART0` writer - Low Energy UART 0 access control bit"]
156pub type LEUART0_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 30>;
157#[doc = "Field `LEUART1` reader - Low Energy UART 1 access control bit"]
158pub type LEUART1_R = crate::BitReader<bool>;
159#[doc = "Field `LEUART1` writer - Low Energy UART 1 access control bit"]
160pub type LEUART1_W<'a> = crate::BitWriter<'a, u32, PPUPATD0_SPEC, bool, 31>;
161impl R {
162 #[doc = "Bit 0 - Analog Comparator 0 access control bit"]
163 #[inline(always)]
164 pub fn acmp0(&self) -> ACMP0_R {
165 ACMP0_R::new((self.bits & 1) != 0)
166 }
167 #[doc = "Bit 1 - Analog Comparator 1 access control bit"]
168 #[inline(always)]
169 pub fn acmp1(&self) -> ACMP1_R {
170 ACMP1_R::new(((self.bits >> 1) & 1) != 0)
171 }
172 #[doc = "Bit 2 - Analog Comparator 1 access control bit"]
173 #[inline(always)]
174 pub fn acmp2(&self) -> ACMP2_R {
175 ACMP2_R::new(((self.bits >> 2) & 1) != 0)
176 }
177 #[doc = "Bit 3 - Analog Comparator 3 access control bit"]
178 #[inline(always)]
179 pub fn acmp3(&self) -> ACMP3_R {
180 ACMP3_R::new(((self.bits >> 3) & 1) != 0)
181 }
182 #[doc = "Bit 4 - Analog to Digital Converter 0 access control bit"]
183 #[inline(always)]
184 pub fn adc0(&self) -> ADC0_R {
185 ADC0_R::new(((self.bits >> 4) & 1) != 0)
186 }
187 #[doc = "Bit 5 - Analog to Digital Converter 0 access control bit"]
188 #[inline(always)]
189 pub fn adc1(&self) -> ADC1_R {
190 ADC1_R::new(((self.bits >> 5) & 1) != 0)
191 }
192 #[doc = "Bit 6 - CAN 0 access control bit"]
193 #[inline(always)]
194 pub fn can0(&self) -> CAN0_R {
195 CAN0_R::new(((self.bits >> 6) & 1) != 0)
196 }
197 #[doc = "Bit 7 - CAN 1 access control bit"]
198 #[inline(always)]
199 pub fn can1(&self) -> CAN1_R {
200 CAN1_R::new(((self.bits >> 7) & 1) != 0)
201 }
202 #[doc = "Bit 8 - Clock Management Unit access control bit"]
203 #[inline(always)]
204 pub fn cmu(&self) -> CMU_R {
205 CMU_R::new(((self.bits >> 8) & 1) != 0)
206 }
207 #[doc = "Bit 9 - CRYOTIMER access control bit"]
208 #[inline(always)]
209 pub fn cryotimer(&self) -> CRYOTIMER_R {
210 CRYOTIMER_R::new(((self.bits >> 9) & 1) != 0)
211 }
212 #[doc = "Bit 10 - Advanced Encryption Standard Accelerator access control bit"]
213 #[inline(always)]
214 pub fn crypto0(&self) -> CRYPTO0_R {
215 CRYPTO0_R::new(((self.bits >> 10) & 1) != 0)
216 }
217 #[doc = "Bit 11 - Capacitive touch sense module access control bit"]
218 #[inline(always)]
219 pub fn csen(&self) -> CSEN_R {
220 CSEN_R::new(((self.bits >> 11) & 1) != 0)
221 }
222 #[doc = "Bit 12 - Digital to Analog Converter 0 access control bit"]
223 #[inline(always)]
224 pub fn vdac0(&self) -> VDAC0_R {
225 VDAC0_R::new(((self.bits >> 12) & 1) != 0)
226 }
227 #[doc = "Bit 13 - Peripheral Reflex System access control bit"]
228 #[inline(always)]
229 pub fn prs(&self) -> PRS_R {
230 PRS_R::new(((self.bits >> 13) & 1) != 0)
231 }
232 #[doc = "Bit 14 - External Bus Interface access control bit"]
233 #[inline(always)]
234 pub fn ebi(&self) -> EBI_R {
235 EBI_R::new(((self.bits >> 14) & 1) != 0)
236 }
237 #[doc = "Bit 15 - Energy Management Unit access control bit"]
238 #[inline(always)]
239 pub fn emu(&self) -> EMU_R {
240 EMU_R::new(((self.bits >> 15) & 1) != 0)
241 }
242 #[doc = "Bit 17 - FPU Exception Handler access control bit"]
243 #[inline(always)]
244 pub fn fpueh(&self) -> FPUEH_R {
245 FPUEH_R::new(((self.bits >> 17) & 1) != 0)
246 }
247 #[doc = "Bit 18 - General Purpose CRC access control bit"]
248 #[inline(always)]
249 pub fn gpcrc(&self) -> GPCRC_R {
250 GPCRC_R::new(((self.bits >> 18) & 1) != 0)
251 }
252 #[doc = "Bit 19 - General purpose Input/Output access control bit"]
253 #[inline(always)]
254 pub fn gpio(&self) -> GPIO_R {
255 GPIO_R::new(((self.bits >> 19) & 1) != 0)
256 }
257 #[doc = "Bit 20 - I2C 0 access control bit"]
258 #[inline(always)]
259 pub fn i2c0(&self) -> I2C0_R {
260 I2C0_R::new(((self.bits >> 20) & 1) != 0)
261 }
262 #[doc = "Bit 21 - I2C 1 access control bit"]
263 #[inline(always)]
264 pub fn i2c1(&self) -> I2C1_R {
265 I2C1_R::new(((self.bits >> 21) & 1) != 0)
266 }
267 #[doc = "Bit 22 - I2C 2 access control bit"]
268 #[inline(always)]
269 pub fn i2c2(&self) -> I2C2_R {
270 I2C2_R::new(((self.bits >> 22) & 1) != 0)
271 }
272 #[doc = "Bit 23 - Current Digital to Analog Converter 0 access control bit"]
273 #[inline(always)]
274 pub fn idac0(&self) -> IDAC0_R {
275 IDAC0_R::new(((self.bits >> 23) & 1) != 0)
276 }
277 #[doc = "Bit 24 - Memory System Controller access control bit"]
278 #[inline(always)]
279 pub fn msc(&self) -> MSC_R {
280 MSC_R::new(((self.bits >> 24) & 1) != 0)
281 }
282 #[doc = "Bit 25 - Liquid Crystal Display Controller access control bit"]
283 #[inline(always)]
284 pub fn lcd(&self) -> LCD_R {
285 LCD_R::new(((self.bits >> 25) & 1) != 0)
286 }
287 #[doc = "Bit 26 - Linked Direct Memory Access Controller access control bit"]
288 #[inline(always)]
289 pub fn ldma(&self) -> LDMA_R {
290 LDMA_R::new(((self.bits >> 26) & 1) != 0)
291 }
292 #[doc = "Bit 27 - Low Energy Sensor Interface access control bit"]
293 #[inline(always)]
294 pub fn lesense(&self) -> LESENSE_R {
295 LESENSE_R::new(((self.bits >> 27) & 1) != 0)
296 }
297 #[doc = "Bit 28 - Low Energy Timer 0 access control bit"]
298 #[inline(always)]
299 pub fn letimer0(&self) -> LETIMER0_R {
300 LETIMER0_R::new(((self.bits >> 28) & 1) != 0)
301 }
302 #[doc = "Bit 29 - Low Energy Timer 1 access control bit"]
303 #[inline(always)]
304 pub fn letimer1(&self) -> LETIMER1_R {
305 LETIMER1_R::new(((self.bits >> 29) & 1) != 0)
306 }
307 #[doc = "Bit 30 - Low Energy UART 0 access control bit"]
308 #[inline(always)]
309 pub fn leuart0(&self) -> LEUART0_R {
310 LEUART0_R::new(((self.bits >> 30) & 1) != 0)
311 }
312 #[doc = "Bit 31 - Low Energy UART 1 access control bit"]
313 #[inline(always)]
314 pub fn leuart1(&self) -> LEUART1_R {
315 LEUART1_R::new(((self.bits >> 31) & 1) != 0)
316 }
317}
318impl W {
319 #[doc = "Bit 0 - Analog Comparator 0 access control bit"]
320 #[inline(always)]
321 pub fn acmp0(&mut self) -> ACMP0_W {
322 ACMP0_W::new(self)
323 }
324 #[doc = "Bit 1 - Analog Comparator 1 access control bit"]
325 #[inline(always)]
326 pub fn acmp1(&mut self) -> ACMP1_W {
327 ACMP1_W::new(self)
328 }
329 #[doc = "Bit 2 - Analog Comparator 1 access control bit"]
330 #[inline(always)]
331 pub fn acmp2(&mut self) -> ACMP2_W {
332 ACMP2_W::new(self)
333 }
334 #[doc = "Bit 3 - Analog Comparator 3 access control bit"]
335 #[inline(always)]
336 pub fn acmp3(&mut self) -> ACMP3_W {
337 ACMP3_W::new(self)
338 }
339 #[doc = "Bit 4 - Analog to Digital Converter 0 access control bit"]
340 #[inline(always)]
341 pub fn adc0(&mut self) -> ADC0_W {
342 ADC0_W::new(self)
343 }
344 #[doc = "Bit 5 - Analog to Digital Converter 0 access control bit"]
345 #[inline(always)]
346 pub fn adc1(&mut self) -> ADC1_W {
347 ADC1_W::new(self)
348 }
349 #[doc = "Bit 6 - CAN 0 access control bit"]
350 #[inline(always)]
351 pub fn can0(&mut self) -> CAN0_W {
352 CAN0_W::new(self)
353 }
354 #[doc = "Bit 7 - CAN 1 access control bit"]
355 #[inline(always)]
356 pub fn can1(&mut self) -> CAN1_W {
357 CAN1_W::new(self)
358 }
359 #[doc = "Bit 8 - Clock Management Unit access control bit"]
360 #[inline(always)]
361 pub fn cmu(&mut self) -> CMU_W {
362 CMU_W::new(self)
363 }
364 #[doc = "Bit 9 - CRYOTIMER access control bit"]
365 #[inline(always)]
366 pub fn cryotimer(&mut self) -> CRYOTIMER_W {
367 CRYOTIMER_W::new(self)
368 }
369 #[doc = "Bit 10 - Advanced Encryption Standard Accelerator access control bit"]
370 #[inline(always)]
371 pub fn crypto0(&mut self) -> CRYPTO0_W {
372 CRYPTO0_W::new(self)
373 }
374 #[doc = "Bit 11 - Capacitive touch sense module access control bit"]
375 #[inline(always)]
376 pub fn csen(&mut self) -> CSEN_W {
377 CSEN_W::new(self)
378 }
379 #[doc = "Bit 12 - Digital to Analog Converter 0 access control bit"]
380 #[inline(always)]
381 pub fn vdac0(&mut self) -> VDAC0_W {
382 VDAC0_W::new(self)
383 }
384 #[doc = "Bit 13 - Peripheral Reflex System access control bit"]
385 #[inline(always)]
386 pub fn prs(&mut self) -> PRS_W {
387 PRS_W::new(self)
388 }
389 #[doc = "Bit 14 - External Bus Interface access control bit"]
390 #[inline(always)]
391 pub fn ebi(&mut self) -> EBI_W {
392 EBI_W::new(self)
393 }
394 #[doc = "Bit 15 - Energy Management Unit access control bit"]
395 #[inline(always)]
396 pub fn emu(&mut self) -> EMU_W {
397 EMU_W::new(self)
398 }
399 #[doc = "Bit 17 - FPU Exception Handler access control bit"]
400 #[inline(always)]
401 pub fn fpueh(&mut self) -> FPUEH_W {
402 FPUEH_W::new(self)
403 }
404 #[doc = "Bit 18 - General Purpose CRC access control bit"]
405 #[inline(always)]
406 pub fn gpcrc(&mut self) -> GPCRC_W {
407 GPCRC_W::new(self)
408 }
409 #[doc = "Bit 19 - General purpose Input/Output access control bit"]
410 #[inline(always)]
411 pub fn gpio(&mut self) -> GPIO_W {
412 GPIO_W::new(self)
413 }
414 #[doc = "Bit 20 - I2C 0 access control bit"]
415 #[inline(always)]
416 pub fn i2c0(&mut self) -> I2C0_W {
417 I2C0_W::new(self)
418 }
419 #[doc = "Bit 21 - I2C 1 access control bit"]
420 #[inline(always)]
421 pub fn i2c1(&mut self) -> I2C1_W {
422 I2C1_W::new(self)
423 }
424 #[doc = "Bit 22 - I2C 2 access control bit"]
425 #[inline(always)]
426 pub fn i2c2(&mut self) -> I2C2_W {
427 I2C2_W::new(self)
428 }
429 #[doc = "Bit 23 - Current Digital to Analog Converter 0 access control bit"]
430 #[inline(always)]
431 pub fn idac0(&mut self) -> IDAC0_W {
432 IDAC0_W::new(self)
433 }
434 #[doc = "Bit 24 - Memory System Controller access control bit"]
435 #[inline(always)]
436 pub fn msc(&mut self) -> MSC_W {
437 MSC_W::new(self)
438 }
439 #[doc = "Bit 25 - Liquid Crystal Display Controller access control bit"]
440 #[inline(always)]
441 pub fn lcd(&mut self) -> LCD_W {
442 LCD_W::new(self)
443 }
444 #[doc = "Bit 26 - Linked Direct Memory Access Controller access control bit"]
445 #[inline(always)]
446 pub fn ldma(&mut self) -> LDMA_W {
447 LDMA_W::new(self)
448 }
449 #[doc = "Bit 27 - Low Energy Sensor Interface access control bit"]
450 #[inline(always)]
451 pub fn lesense(&mut self) -> LESENSE_W {
452 LESENSE_W::new(self)
453 }
454 #[doc = "Bit 28 - Low Energy Timer 0 access control bit"]
455 #[inline(always)]
456 pub fn letimer0(&mut self) -> LETIMER0_W {
457 LETIMER0_W::new(self)
458 }
459 #[doc = "Bit 29 - Low Energy Timer 1 access control bit"]
460 #[inline(always)]
461 pub fn letimer1(&mut self) -> LETIMER1_W {
462 LETIMER1_W::new(self)
463 }
464 #[doc = "Bit 30 - Low Energy UART 0 access control bit"]
465 #[inline(always)]
466 pub fn leuart0(&mut self) -> LEUART0_W {
467 LEUART0_W::new(self)
468 }
469 #[doc = "Bit 31 - Low Energy UART 1 access control bit"]
470 #[inline(always)]
471 pub fn leuart1(&mut self) -> LEUART1_W {
472 LEUART1_W::new(self)
473 }
474 #[doc = "Writes raw bits to the register."]
475 #[inline(always)]
476 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
477 self.0.bits(bits);
478 self
479 }
480}
481#[doc = "PPU Privilege Access Type Descriptor 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ppupatd0](index.html) module"]
482pub struct PPUPATD0_SPEC;
483impl crate::RegisterSpec for PPUPATD0_SPEC {
484 type Ux = u32;
485}
486#[doc = "`read()` method returns [ppupatd0::R](R) reader structure"]
487impl crate::Readable for PPUPATD0_SPEC {
488 type Reader = R;
489}
490#[doc = "`write(|w| ..)` method takes [ppupatd0::W](W) writer structure"]
491impl crate::Writable for PPUPATD0_SPEC {
492 type Writer = W;
493}
494#[doc = "`reset()` method sets PPUPATD0 to value 0"]
495impl crate::Resettable for PPUPATD0_SPEC {
496 #[inline(always)]
497 fn reset_value() -> Self::Ux {
498 0
499 }
500}