efm32gg11b510_pac/msc/
cacheconfig0.rs

1#[doc = "Register `CACHECONFIG0` reader"]
2pub struct R(crate::R<CACHECONFIG0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CACHECONFIG0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CACHECONFIG0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CACHECONFIG0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CACHECONFIG0` writer"]
17pub struct W(crate::W<CACHECONFIG0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CACHECONFIG0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CACHECONFIG0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CACHECONFIG0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Instruction Cache Low-Power Level\n\nValue on reset: 3"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum CACHELPLEVEL_A {
41    #[doc = "0: Base instruction cache functionality."]
42    BASE = 0,
43    #[doc = "1: Advanced buffering mode, where the cache uses the fetch pattern to predict highly accessed data and store it in low-energy memory."]
44    ADVANCED = 1,
45    #[doc = "3: Minimum activity mode, which allows the cache to minimize activity in logic that it predicts has a low probability being used. This mode can introduce wait-states into the instruction fetch stream when the cache exits one of its low-activity states. The number of wait-states introduced is small, but users running with 0-wait-state memory and wishing to reduce the variability that the cache might introduce with additional wait-states may wish to lower the cache low-power level. Note, this mode includes the advanced buffering mode functionality."]
46    MINACTIVITY = 3,
47}
48impl From<CACHELPLEVEL_A> for u8 {
49    #[inline(always)]
50    fn from(variant: CACHELPLEVEL_A) -> Self {
51        variant as _
52    }
53}
54#[doc = "Field `CACHELPLEVEL` reader - Instruction Cache Low-Power Level"]
55pub type CACHELPLEVEL_R = crate::FieldReader<u8, CACHELPLEVEL_A>;
56impl CACHELPLEVEL_R {
57    #[doc = "Get enumerated values variant"]
58    #[inline(always)]
59    pub fn variant(&self) -> Option<CACHELPLEVEL_A> {
60        match self.bits {
61            0 => Some(CACHELPLEVEL_A::BASE),
62            1 => Some(CACHELPLEVEL_A::ADVANCED),
63            3 => Some(CACHELPLEVEL_A::MINACTIVITY),
64            _ => None,
65        }
66    }
67    #[doc = "Checks if the value of the field is `BASE`"]
68    #[inline(always)]
69    pub fn is_base(&self) -> bool {
70        *self == CACHELPLEVEL_A::BASE
71    }
72    #[doc = "Checks if the value of the field is `ADVANCED`"]
73    #[inline(always)]
74    pub fn is_advanced(&self) -> bool {
75        *self == CACHELPLEVEL_A::ADVANCED
76    }
77    #[doc = "Checks if the value of the field is `MINACTIVITY`"]
78    #[inline(always)]
79    pub fn is_minactivity(&self) -> bool {
80        *self == CACHELPLEVEL_A::MINACTIVITY
81    }
82}
83#[doc = "Field `CACHELPLEVEL` writer - Instruction Cache Low-Power Level"]
84pub type CACHELPLEVEL_W<'a> =
85    crate::FieldWriter<'a, u32, CACHECONFIG0_SPEC, u8, CACHELPLEVEL_A, 2, 0>;
86impl<'a> CACHELPLEVEL_W<'a> {
87    #[doc = "Base instruction cache functionality."]
88    #[inline(always)]
89    pub fn base(self) -> &'a mut W {
90        self.variant(CACHELPLEVEL_A::BASE)
91    }
92    #[doc = "Advanced buffering mode, where the cache uses the fetch pattern to predict highly accessed data and store it in low-energy memory."]
93    #[inline(always)]
94    pub fn advanced(self) -> &'a mut W {
95        self.variant(CACHELPLEVEL_A::ADVANCED)
96    }
97    #[doc = "Minimum activity mode, which allows the cache to minimize activity in logic that it predicts has a low probability being used. This mode can introduce wait-states into the instruction fetch stream when the cache exits one of its low-activity states. The number of wait-states introduced is small, but users running with 0-wait-state memory and wishing to reduce the variability that the cache might introduce with additional wait-states may wish to lower the cache low-power level. Note, this mode includes the advanced buffering mode functionality."]
98    #[inline(always)]
99    pub fn minactivity(self) -> &'a mut W {
100        self.variant(CACHELPLEVEL_A::MINACTIVITY)
101    }
102}
103impl R {
104    #[doc = "Bits 0:1 - Instruction Cache Low-Power Level"]
105    #[inline(always)]
106    pub fn cachelplevel(&self) -> CACHELPLEVEL_R {
107        CACHELPLEVEL_R::new((self.bits & 3) as u8)
108    }
109}
110impl W {
111    #[doc = "Bits 0:1 - Instruction Cache Low-Power Level"]
112    #[inline(always)]
113    pub fn cachelplevel(&mut self) -> CACHELPLEVEL_W {
114        CACHELPLEVEL_W::new(self)
115    }
116    #[doc = "Writes raw bits to the register."]
117    #[inline(always)]
118    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
119        self.0.bits(bits);
120        self
121    }
122}
123#[doc = "Cache Configuration Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cacheconfig0](index.html) module"]
124pub struct CACHECONFIG0_SPEC;
125impl crate::RegisterSpec for CACHECONFIG0_SPEC {
126    type Ux = u32;
127}
128#[doc = "`read()` method returns [cacheconfig0::R](R) reader structure"]
129impl crate::Readable for CACHECONFIG0_SPEC {
130    type Reader = R;
131}
132#[doc = "`write(|w| ..)` method takes [cacheconfig0::W](W) writer structure"]
133impl crate::Writable for CACHECONFIG0_SPEC {
134    type Writer = W;
135}
136#[doc = "`reset()` method sets CACHECONFIG0 to value 0x03"]
137impl crate::Resettable for CACHECONFIG0_SPEC {
138    #[inline(always)]
139    fn reset_value() -> Self::Ux {
140        0x03
141    }
142}
efm32gg11b510_pac/msc/cacheconfig0.rs

efm32gg11b510_pac/msc/
cacheconfig0.rs
