1#[doc = "Register `HFPERCLKEN0` reader"]
2pub struct R(crate::R<HFPERCLKEN0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<HFPERCLKEN0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<HFPERCLKEN0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<HFPERCLKEN0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `HFPERCLKEN0` writer"]
17pub struct W(crate::W<HFPERCLKEN0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<HFPERCLKEN0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<HFPERCLKEN0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<HFPERCLKEN0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `TIMER0` reader - Timer 0 Clock Enable"]
38pub type TIMER0_R = crate::BitReader<bool>;
39#[doc = "Field `TIMER0` writer - Timer 0 Clock Enable"]
40pub type TIMER0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 0>;
41#[doc = "Field `TIMER1` reader - Timer 1 Clock Enable"]
42pub type TIMER1_R = crate::BitReader<bool>;
43#[doc = "Field `TIMER1` writer - Timer 1 Clock Enable"]
44pub type TIMER1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 1>;
45#[doc = "Field `TIMER2` reader - Timer 2 Clock Enable"]
46pub type TIMER2_R = crate::BitReader<bool>;
47#[doc = "Field `TIMER2` writer - Timer 2 Clock Enable"]
48pub type TIMER2_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 2>;
49#[doc = "Field `TIMER3` reader - Timer 3 Clock Enable"]
50pub type TIMER3_R = crate::BitReader<bool>;
51#[doc = "Field `TIMER3` writer - Timer 3 Clock Enable"]
52pub type TIMER3_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 3>;
53#[doc = "Field `TIMER4` reader - Timer 4 Clock Enable"]
54pub type TIMER4_R = crate::BitReader<bool>;
55#[doc = "Field `TIMER4` writer - Timer 4 Clock Enable"]
56pub type TIMER4_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 4>;
57#[doc = "Field `TIMER5` reader - Timer 5 Clock Enable"]
58pub type TIMER5_R = crate::BitReader<bool>;
59#[doc = "Field `TIMER5` writer - Timer 5 Clock Enable"]
60pub type TIMER5_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 5>;
61#[doc = "Field `TIMER6` reader - Timer 6 Clock Enable"]
62pub type TIMER6_R = crate::BitReader<bool>;
63#[doc = "Field `TIMER6` writer - Timer 6 Clock Enable"]
64pub type TIMER6_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 6>;
65#[doc = "Field `USART0` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
66pub type USART0_R = crate::BitReader<bool>;
67#[doc = "Field `USART0` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
68pub type USART0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 7>;
69#[doc = "Field `USART1` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
70pub type USART1_R = crate::BitReader<bool>;
71#[doc = "Field `USART1` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
72pub type USART1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 8>;
73#[doc = "Field `USART2` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
74pub type USART2_R = crate::BitReader<bool>;
75#[doc = "Field `USART2` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
76pub type USART2_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 9>;
77#[doc = "Field `USART3` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable"]
78pub type USART3_R = crate::BitReader<bool>;
79#[doc = "Field `USART3` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable"]
80pub type USART3_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 10>;
81#[doc = "Field `USART4` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable"]
82pub type USART4_R = crate::BitReader<bool>;
83#[doc = "Field `USART4` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable"]
84pub type USART4_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 11>;
85#[doc = "Field `USART5` reader - Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable"]
86pub type USART5_R = crate::BitReader<bool>;
87#[doc = "Field `USART5` writer - Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable"]
88pub type USART5_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 12>;
89#[doc = "Field `ACMP0` reader - Analog Comparator 0 Clock Enable"]
90pub type ACMP0_R = crate::BitReader<bool>;
91#[doc = "Field `ACMP0` writer - Analog Comparator 0 Clock Enable"]
92pub type ACMP0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 13>;
93#[doc = "Field `ACMP1` reader - Analog Comparator 1 Clock Enable"]
94pub type ACMP1_R = crate::BitReader<bool>;
95#[doc = "Field `ACMP1` writer - Analog Comparator 1 Clock Enable"]
96pub type ACMP1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 14>;
97#[doc = "Field `ACMP2` reader - Analog Comparator 1 Clock Enable"]
98pub type ACMP2_R = crate::BitReader<bool>;
99#[doc = "Field `ACMP2` writer - Analog Comparator 1 Clock Enable"]
100pub type ACMP2_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 15>;
101#[doc = "Field `ACMP3` reader - Analog Comparator 3 Clock Enable"]
102pub type ACMP3_R = crate::BitReader<bool>;
103#[doc = "Field `ACMP3` writer - Analog Comparator 3 Clock Enable"]
104pub type ACMP3_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 16>;
105#[doc = "Field `I2C0` reader - I2C 0 Clock Enable"]
106pub type I2C0_R = crate::BitReader<bool>;
107#[doc = "Field `I2C0` writer - I2C 0 Clock Enable"]
108pub type I2C0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 17>;
109#[doc = "Field `I2C1` reader - I2C 1 Clock Enable"]
110pub type I2C1_R = crate::BitReader<bool>;
111#[doc = "Field `I2C1` writer - I2C 1 Clock Enable"]
112pub type I2C1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 18>;
113#[doc = "Field `I2C2` reader - I2C 2 Clock Enable"]
114pub type I2C2_R = crate::BitReader<bool>;
115#[doc = "Field `I2C2` writer - I2C 2 Clock Enable"]
116pub type I2C2_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 19>;
117#[doc = "Field `ADC0` reader - Analog to Digital Converter 0 Clock Enable"]
118pub type ADC0_R = crate::BitReader<bool>;
119#[doc = "Field `ADC0` writer - Analog to Digital Converter 0 Clock Enable"]
120pub type ADC0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 20>;
121#[doc = "Field `ADC1` reader - Analog to Digital Converter 0 Clock Enable"]
122pub type ADC1_R = crate::BitReader<bool>;
123#[doc = "Field `ADC1` writer - Analog to Digital Converter 0 Clock Enable"]
124pub type ADC1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 21>;
125#[doc = "Field `CRYOTIMER` reader - CRYOTIMER Clock Enable"]
126pub type CRYOTIMER_R = crate::BitReader<bool>;
127#[doc = "Field `CRYOTIMER` writer - CRYOTIMER Clock Enable"]
128pub type CRYOTIMER_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 22>;
129#[doc = "Field `IDAC0` reader - Current Digital to Analog Converter 0 Clock Enable"]
130pub type IDAC0_R = crate::BitReader<bool>;
131#[doc = "Field `IDAC0` writer - Current Digital to Analog Converter 0 Clock Enable"]
132pub type IDAC0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 23>;
133#[doc = "Field `TRNG0` reader - True Random Number Generator 0 Clock Enable"]
134pub type TRNG0_R = crate::BitReader<bool>;
135#[doc = "Field `TRNG0` writer - True Random Number Generator 0 Clock Enable"]
136pub type TRNG0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN0_SPEC, bool, 24>;
137impl R {
138 #[doc = "Bit 0 - Timer 0 Clock Enable"]
139 #[inline(always)]
140 pub fn timer0(&self) -> TIMER0_R {
141 TIMER0_R::new((self.bits & 1) != 0)
142 }
143 #[doc = "Bit 1 - Timer 1 Clock Enable"]
144 #[inline(always)]
145 pub fn timer1(&self) -> TIMER1_R {
146 TIMER1_R::new(((self.bits >> 1) & 1) != 0)
147 }
148 #[doc = "Bit 2 - Timer 2 Clock Enable"]
149 #[inline(always)]
150 pub fn timer2(&self) -> TIMER2_R {
151 TIMER2_R::new(((self.bits >> 2) & 1) != 0)
152 }
153 #[doc = "Bit 3 - Timer 3 Clock Enable"]
154 #[inline(always)]
155 pub fn timer3(&self) -> TIMER3_R {
156 TIMER3_R::new(((self.bits >> 3) & 1) != 0)
157 }
158 #[doc = "Bit 4 - Timer 4 Clock Enable"]
159 #[inline(always)]
160 pub fn timer4(&self) -> TIMER4_R {
161 TIMER4_R::new(((self.bits >> 4) & 1) != 0)
162 }
163 #[doc = "Bit 5 - Timer 5 Clock Enable"]
164 #[inline(always)]
165 pub fn timer5(&self) -> TIMER5_R {
166 TIMER5_R::new(((self.bits >> 5) & 1) != 0)
167 }
168 #[doc = "Bit 6 - Timer 6 Clock Enable"]
169 #[inline(always)]
170 pub fn timer6(&self) -> TIMER6_R {
171 TIMER6_R::new(((self.bits >> 6) & 1) != 0)
172 }
173 #[doc = "Bit 7 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
174 #[inline(always)]
175 pub fn usart0(&self) -> USART0_R {
176 USART0_R::new(((self.bits >> 7) & 1) != 0)
177 }
178 #[doc = "Bit 8 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
179 #[inline(always)]
180 pub fn usart1(&self) -> USART1_R {
181 USART1_R::new(((self.bits >> 8) & 1) != 0)
182 }
183 #[doc = "Bit 9 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
184 #[inline(always)]
185 pub fn usart2(&self) -> USART2_R {
186 USART2_R::new(((self.bits >> 9) & 1) != 0)
187 }
188 #[doc = "Bit 10 - Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable"]
189 #[inline(always)]
190 pub fn usart3(&self) -> USART3_R {
191 USART3_R::new(((self.bits >> 10) & 1) != 0)
192 }
193 #[doc = "Bit 11 - Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable"]
194 #[inline(always)]
195 pub fn usart4(&self) -> USART4_R {
196 USART4_R::new(((self.bits >> 11) & 1) != 0)
197 }
198 #[doc = "Bit 12 - Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable"]
199 #[inline(always)]
200 pub fn usart5(&self) -> USART5_R {
201 USART5_R::new(((self.bits >> 12) & 1) != 0)
202 }
203 #[doc = "Bit 13 - Analog Comparator 0 Clock Enable"]
204 #[inline(always)]
205 pub fn acmp0(&self) -> ACMP0_R {
206 ACMP0_R::new(((self.bits >> 13) & 1) != 0)
207 }
208 #[doc = "Bit 14 - Analog Comparator 1 Clock Enable"]
209 #[inline(always)]
210 pub fn acmp1(&self) -> ACMP1_R {
211 ACMP1_R::new(((self.bits >> 14) & 1) != 0)
212 }
213 #[doc = "Bit 15 - Analog Comparator 1 Clock Enable"]
214 #[inline(always)]
215 pub fn acmp2(&self) -> ACMP2_R {
216 ACMP2_R::new(((self.bits >> 15) & 1) != 0)
217 }
218 #[doc = "Bit 16 - Analog Comparator 3 Clock Enable"]
219 #[inline(always)]
220 pub fn acmp3(&self) -> ACMP3_R {
221 ACMP3_R::new(((self.bits >> 16) & 1) != 0)
222 }
223 #[doc = "Bit 17 - I2C 0 Clock Enable"]
224 #[inline(always)]
225 pub fn i2c0(&self) -> I2C0_R {
226 I2C0_R::new(((self.bits >> 17) & 1) != 0)
227 }
228 #[doc = "Bit 18 - I2C 1 Clock Enable"]
229 #[inline(always)]
230 pub fn i2c1(&self) -> I2C1_R {
231 I2C1_R::new(((self.bits >> 18) & 1) != 0)
232 }
233 #[doc = "Bit 19 - I2C 2 Clock Enable"]
234 #[inline(always)]
235 pub fn i2c2(&self) -> I2C2_R {
236 I2C2_R::new(((self.bits >> 19) & 1) != 0)
237 }
238 #[doc = "Bit 20 - Analog to Digital Converter 0 Clock Enable"]
239 #[inline(always)]
240 pub fn adc0(&self) -> ADC0_R {
241 ADC0_R::new(((self.bits >> 20) & 1) != 0)
242 }
243 #[doc = "Bit 21 - Analog to Digital Converter 0 Clock Enable"]
244 #[inline(always)]
245 pub fn adc1(&self) -> ADC1_R {
246 ADC1_R::new(((self.bits >> 21) & 1) != 0)
247 }
248 #[doc = "Bit 22 - CRYOTIMER Clock Enable"]
249 #[inline(always)]
250 pub fn cryotimer(&self) -> CRYOTIMER_R {
251 CRYOTIMER_R::new(((self.bits >> 22) & 1) != 0)
252 }
253 #[doc = "Bit 23 - Current Digital to Analog Converter 0 Clock Enable"]
254 #[inline(always)]
255 pub fn idac0(&self) -> IDAC0_R {
256 IDAC0_R::new(((self.bits >> 23) & 1) != 0)
257 }
258 #[doc = "Bit 24 - True Random Number Generator 0 Clock Enable"]
259 #[inline(always)]
260 pub fn trng0(&self) -> TRNG0_R {
261 TRNG0_R::new(((self.bits >> 24) & 1) != 0)
262 }
263}
264impl W {
265 #[doc = "Bit 0 - Timer 0 Clock Enable"]
266 #[inline(always)]
267 pub fn timer0(&mut self) -> TIMER0_W {
268 TIMER0_W::new(self)
269 }
270 #[doc = "Bit 1 - Timer 1 Clock Enable"]
271 #[inline(always)]
272 pub fn timer1(&mut self) -> TIMER1_W {
273 TIMER1_W::new(self)
274 }
275 #[doc = "Bit 2 - Timer 2 Clock Enable"]
276 #[inline(always)]
277 pub fn timer2(&mut self) -> TIMER2_W {
278 TIMER2_W::new(self)
279 }
280 #[doc = "Bit 3 - Timer 3 Clock Enable"]
281 #[inline(always)]
282 pub fn timer3(&mut self) -> TIMER3_W {
283 TIMER3_W::new(self)
284 }
285 #[doc = "Bit 4 - Timer 4 Clock Enable"]
286 #[inline(always)]
287 pub fn timer4(&mut self) -> TIMER4_W {
288 TIMER4_W::new(self)
289 }
290 #[doc = "Bit 5 - Timer 5 Clock Enable"]
291 #[inline(always)]
292 pub fn timer5(&mut self) -> TIMER5_W {
293 TIMER5_W::new(self)
294 }
295 #[doc = "Bit 6 - Timer 6 Clock Enable"]
296 #[inline(always)]
297 pub fn timer6(&mut self) -> TIMER6_W {
298 TIMER6_W::new(self)
299 }
300 #[doc = "Bit 7 - Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable"]
301 #[inline(always)]
302 pub fn usart0(&mut self) -> USART0_W {
303 USART0_W::new(self)
304 }
305 #[doc = "Bit 8 - Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable"]
306 #[inline(always)]
307 pub fn usart1(&mut self) -> USART1_W {
308 USART1_W::new(self)
309 }
310 #[doc = "Bit 9 - Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable"]
311 #[inline(always)]
312 pub fn usart2(&mut self) -> USART2_W {
313 USART2_W::new(self)
314 }
315 #[doc = "Bit 10 - Universal Synchronous/Asynchronous Receiver/Transmitter 3 Clock Enable"]
316 #[inline(always)]
317 pub fn usart3(&mut self) -> USART3_W {
318 USART3_W::new(self)
319 }
320 #[doc = "Bit 11 - Universal Synchronous/Asynchronous Receiver/Transmitter 4 Clock Enable"]
321 #[inline(always)]
322 pub fn usart4(&mut self) -> USART4_W {
323 USART4_W::new(self)
324 }
325 #[doc = "Bit 12 - Universal Synchronous/Asynchronous Receiver/Transmitter 5 Clock Enable"]
326 #[inline(always)]
327 pub fn usart5(&mut self) -> USART5_W {
328 USART5_W::new(self)
329 }
330 #[doc = "Bit 13 - Analog Comparator 0 Clock Enable"]
331 #[inline(always)]
332 pub fn acmp0(&mut self) -> ACMP0_W {
333 ACMP0_W::new(self)
334 }
335 #[doc = "Bit 14 - Analog Comparator 1 Clock Enable"]
336 #[inline(always)]
337 pub fn acmp1(&mut self) -> ACMP1_W {
338 ACMP1_W::new(self)
339 }
340 #[doc = "Bit 15 - Analog Comparator 1 Clock Enable"]
341 #[inline(always)]
342 pub fn acmp2(&mut self) -> ACMP2_W {
343 ACMP2_W::new(self)
344 }
345 #[doc = "Bit 16 - Analog Comparator 3 Clock Enable"]
346 #[inline(always)]
347 pub fn acmp3(&mut self) -> ACMP3_W {
348 ACMP3_W::new(self)
349 }
350 #[doc = "Bit 17 - I2C 0 Clock Enable"]
351 #[inline(always)]
352 pub fn i2c0(&mut self) -> I2C0_W {
353 I2C0_W::new(self)
354 }
355 #[doc = "Bit 18 - I2C 1 Clock Enable"]
356 #[inline(always)]
357 pub fn i2c1(&mut self) -> I2C1_W {
358 I2C1_W::new(self)
359 }
360 #[doc = "Bit 19 - I2C 2 Clock Enable"]
361 #[inline(always)]
362 pub fn i2c2(&mut self) -> I2C2_W {
363 I2C2_W::new(self)
364 }
365 #[doc = "Bit 20 - Analog to Digital Converter 0 Clock Enable"]
366 #[inline(always)]
367 pub fn adc0(&mut self) -> ADC0_W {
368 ADC0_W::new(self)
369 }
370 #[doc = "Bit 21 - Analog to Digital Converter 0 Clock Enable"]
371 #[inline(always)]
372 pub fn adc1(&mut self) -> ADC1_W {
373 ADC1_W::new(self)
374 }
375 #[doc = "Bit 22 - CRYOTIMER Clock Enable"]
376 #[inline(always)]
377 pub fn cryotimer(&mut self) -> CRYOTIMER_W {
378 CRYOTIMER_W::new(self)
379 }
380 #[doc = "Bit 23 - Current Digital to Analog Converter 0 Clock Enable"]
381 #[inline(always)]
382 pub fn idac0(&mut self) -> IDAC0_W {
383 IDAC0_W::new(self)
384 }
385 #[doc = "Bit 24 - True Random Number Generator 0 Clock Enable"]
386 #[inline(always)]
387 pub fn trng0(&mut self) -> TRNG0_W {
388 TRNG0_W::new(self)
389 }
390 #[doc = "Writes raw bits to the register."]
391 #[inline(always)]
392 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
393 self.0.bits(bits);
394 self
395 }
396}
397#[doc = "High Frequency Peripheral Clock Enable Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfperclken0](index.html) module"]
398pub struct HFPERCLKEN0_SPEC;
399impl crate::RegisterSpec for HFPERCLKEN0_SPEC {
400 type Ux = u32;
401}
402#[doc = "`read()` method returns [hfperclken0::R](R) reader structure"]
403impl crate::Readable for HFPERCLKEN0_SPEC {
404 type Reader = R;
405}
406#[doc = "`write(|w| ..)` method takes [hfperclken0::W](W) writer structure"]
407impl crate::Writable for HFPERCLKEN0_SPEC {
408 type Writer = W;
409}
410#[doc = "`reset()` method sets HFPERCLKEN0 to value 0"]
411impl crate::Resettable for HFPERCLKEN0_SPEC {
412 #[inline(always)]
413 fn reset_value() -> Self::Ux {
414 0
415 }
416}