efm32gg11b510_pac/cmu/
hfperclken1.rs1#[doc = "Register `HFPERCLKEN1` reader"]
2pub struct R(crate::R<HFPERCLKEN1_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<HFPERCLKEN1_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<HFPERCLKEN1_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<HFPERCLKEN1_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `HFPERCLKEN1` writer"]
17pub struct W(crate::W<HFPERCLKEN1_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<HFPERCLKEN1_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<HFPERCLKEN1_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<HFPERCLKEN1_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `WTIMER0` reader - Wide Timer 0 Clock Enable"]
38pub type WTIMER0_R = crate::BitReader<bool>;
39#[doc = "Field `WTIMER0` writer - Wide Timer 0 Clock Enable"]
40pub type WTIMER0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 0>;
41#[doc = "Field `WTIMER1` reader - Wide Timer 0 Clock Enable"]
42pub type WTIMER1_R = crate::BitReader<bool>;
43#[doc = "Field `WTIMER1` writer - Wide Timer 0 Clock Enable"]
44pub type WTIMER1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 1>;
45#[doc = "Field `WTIMER2` reader - Wide Timer 2 Clock Enable"]
46pub type WTIMER2_R = crate::BitReader<bool>;
47#[doc = "Field `WTIMER2` writer - Wide Timer 2 Clock Enable"]
48pub type WTIMER2_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 2>;
49#[doc = "Field `WTIMER3` reader - Wide Timer 3 Clock Enable"]
50pub type WTIMER3_R = crate::BitReader<bool>;
51#[doc = "Field `WTIMER3` writer - Wide Timer 3 Clock Enable"]
52pub type WTIMER3_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 3>;
53#[doc = "Field `UART0` reader - Universal Asynchronous Receiver/Transmitter 0 Clock Enable"]
54pub type UART0_R = crate::BitReader<bool>;
55#[doc = "Field `UART0` writer - Universal Asynchronous Receiver/Transmitter 0 Clock Enable"]
56pub type UART0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 4>;
57#[doc = "Field `UART1` reader - Universal Asynchronous Receiver/Transmitter 1 Clock Enable"]
58pub type UART1_R = crate::BitReader<bool>;
59#[doc = "Field `UART1` writer - Universal Asynchronous Receiver/Transmitter 1 Clock Enable"]
60pub type UART1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 5>;
61#[doc = "Field `CAN0` reader - CAN 0 Clock Enable"]
62pub type CAN0_R = crate::BitReader<bool>;
63#[doc = "Field `CAN0` writer - CAN 0 Clock Enable"]
64pub type CAN0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 6>;
65#[doc = "Field `CAN1` reader - CAN 1 Clock Enable"]
66pub type CAN1_R = crate::BitReader<bool>;
67#[doc = "Field `CAN1` writer - CAN 1 Clock Enable"]
68pub type CAN1_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 7>;
69#[doc = "Field `VDAC0` reader - Digital to Analog Converter 0 Clock Enable"]
70pub type VDAC0_R = crate::BitReader<bool>;
71#[doc = "Field `VDAC0` writer - Digital to Analog Converter 0 Clock Enable"]
72pub type VDAC0_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 8>;
73#[doc = "Field `CSEN` reader - Capacitive touch sense module Clock Enable"]
74pub type CSEN_R = crate::BitReader<bool>;
75#[doc = "Field `CSEN` writer - Capacitive touch sense module Clock Enable"]
76pub type CSEN_W<'a> = crate::BitWriter<'a, u32, HFPERCLKEN1_SPEC, bool, 9>;
77impl R {
78 #[doc = "Bit 0 - Wide Timer 0 Clock Enable"]
79 #[inline(always)]
80 pub fn wtimer0(&self) -> WTIMER0_R {
81 WTIMER0_R::new((self.bits & 1) != 0)
82 }
83 #[doc = "Bit 1 - Wide Timer 0 Clock Enable"]
84 #[inline(always)]
85 pub fn wtimer1(&self) -> WTIMER1_R {
86 WTIMER1_R::new(((self.bits >> 1) & 1) != 0)
87 }
88 #[doc = "Bit 2 - Wide Timer 2 Clock Enable"]
89 #[inline(always)]
90 pub fn wtimer2(&self) -> WTIMER2_R {
91 WTIMER2_R::new(((self.bits >> 2) & 1) != 0)
92 }
93 #[doc = "Bit 3 - Wide Timer 3 Clock Enable"]
94 #[inline(always)]
95 pub fn wtimer3(&self) -> WTIMER3_R {
96 WTIMER3_R::new(((self.bits >> 3) & 1) != 0)
97 }
98 #[doc = "Bit 4 - Universal Asynchronous Receiver/Transmitter 0 Clock Enable"]
99 #[inline(always)]
100 pub fn uart0(&self) -> UART0_R {
101 UART0_R::new(((self.bits >> 4) & 1) != 0)
102 }
103 #[doc = "Bit 5 - Universal Asynchronous Receiver/Transmitter 1 Clock Enable"]
104 #[inline(always)]
105 pub fn uart1(&self) -> UART1_R {
106 UART1_R::new(((self.bits >> 5) & 1) != 0)
107 }
108 #[doc = "Bit 6 - CAN 0 Clock Enable"]
109 #[inline(always)]
110 pub fn can0(&self) -> CAN0_R {
111 CAN0_R::new(((self.bits >> 6) & 1) != 0)
112 }
113 #[doc = "Bit 7 - CAN 1 Clock Enable"]
114 #[inline(always)]
115 pub fn can1(&self) -> CAN1_R {
116 CAN1_R::new(((self.bits >> 7) & 1) != 0)
117 }
118 #[doc = "Bit 8 - Digital to Analog Converter 0 Clock Enable"]
119 #[inline(always)]
120 pub fn vdac0(&self) -> VDAC0_R {
121 VDAC0_R::new(((self.bits >> 8) & 1) != 0)
122 }
123 #[doc = "Bit 9 - Capacitive touch sense module Clock Enable"]
124 #[inline(always)]
125 pub fn csen(&self) -> CSEN_R {
126 CSEN_R::new(((self.bits >> 9) & 1) != 0)
127 }
128}
129impl W {
130 #[doc = "Bit 0 - Wide Timer 0 Clock Enable"]
131 #[inline(always)]
132 pub fn wtimer0(&mut self) -> WTIMER0_W {
133 WTIMER0_W::new(self)
134 }
135 #[doc = "Bit 1 - Wide Timer 0 Clock Enable"]
136 #[inline(always)]
137 pub fn wtimer1(&mut self) -> WTIMER1_W {
138 WTIMER1_W::new(self)
139 }
140 #[doc = "Bit 2 - Wide Timer 2 Clock Enable"]
141 #[inline(always)]
142 pub fn wtimer2(&mut self) -> WTIMER2_W {
143 WTIMER2_W::new(self)
144 }
145 #[doc = "Bit 3 - Wide Timer 3 Clock Enable"]
146 #[inline(always)]
147 pub fn wtimer3(&mut self) -> WTIMER3_W {
148 WTIMER3_W::new(self)
149 }
150 #[doc = "Bit 4 - Universal Asynchronous Receiver/Transmitter 0 Clock Enable"]
151 #[inline(always)]
152 pub fn uart0(&mut self) -> UART0_W {
153 UART0_W::new(self)
154 }
155 #[doc = "Bit 5 - Universal Asynchronous Receiver/Transmitter 1 Clock Enable"]
156 #[inline(always)]
157 pub fn uart1(&mut self) -> UART1_W {
158 UART1_W::new(self)
159 }
160 #[doc = "Bit 6 - CAN 0 Clock Enable"]
161 #[inline(always)]
162 pub fn can0(&mut self) -> CAN0_W {
163 CAN0_W::new(self)
164 }
165 #[doc = "Bit 7 - CAN 1 Clock Enable"]
166 #[inline(always)]
167 pub fn can1(&mut self) -> CAN1_W {
168 CAN1_W::new(self)
169 }
170 #[doc = "Bit 8 - Digital to Analog Converter 0 Clock Enable"]
171 #[inline(always)]
172 pub fn vdac0(&mut self) -> VDAC0_W {
173 VDAC0_W::new(self)
174 }
175 #[doc = "Bit 9 - Capacitive touch sense module Clock Enable"]
176 #[inline(always)]
177 pub fn csen(&mut self) -> CSEN_W {
178 CSEN_W::new(self)
179 }
180 #[doc = "Writes raw bits to the register."]
181 #[inline(always)]
182 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
183 self.0.bits(bits);
184 self
185 }
186}
187#[doc = "High Frequency Peripheral Clock Enable Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hfperclken1](index.html) module"]
188pub struct HFPERCLKEN1_SPEC;
189impl crate::RegisterSpec for HFPERCLKEN1_SPEC {
190 type Ux = u32;
191}
192#[doc = "`read()` method returns [hfperclken1::R](R) reader structure"]
193impl crate::Readable for HFPERCLKEN1_SPEC {
194 type Reader = R;
195}
196#[doc = "`write(|w| ..)` method takes [hfperclken1::W](W) writer structure"]
197impl crate::Writable for HFPERCLKEN1_SPEC {
198 type Writer = W;
199}
200#[doc = "`reset()` method sets HFPERCLKEN1 to value 0"]
201impl crate::Resettable for HFPERCLKEN1_SPEC {
202 #[inline(always)]
203 fn reset_value() -> Self::Ux {
204 0
205 }
206}