efm32gg11b420_pac/prs/
ch14_ctrl.rs

1#[doc = "Register `CH14_CTRL` reader"]
2pub struct R(crate::R<CH14_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH14_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH14_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH14_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH14_CTRL` writer"]
17pub struct W(crate::W<CH14_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH14_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH14_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH14_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH14_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Peripheral Reflex System"]
48    PRSL = 1,
49    #[doc = "2: Peripheral Reflex System"]
50    PRS = 2,
51    #[doc = "3: Peripheral Reflex System"]
52    PRSH = 3,
53    #[doc = "4: Analog Comparator 0"]
54    ACMP0 = 4,
55    #[doc = "5: Analog Comparator 1"]
56    ACMP1 = 5,
57    #[doc = "6: Analog to Digital Converter 0"]
58    ADC0 = 6,
59    #[doc = "7: Real-Time Counter"]
60    RTC = 7,
61    #[doc = "8: Real-Time Counter and Calendar"]
62    RTCC = 8,
63    #[doc = "9: General purpose Input/Output"]
64    GPIOL = 9,
65    #[doc = "10: General purpose Input/Output"]
66    GPIOH = 10,
67    #[doc = "11: Low Energy Timer 0"]
68    LETIMER0 = 11,
69    #[doc = "12: Low Energy Timer 1"]
70    LETIMER1 = 12,
71    #[doc = "13: Pulse Counter 0"]
72    PCNT0 = 13,
73    #[doc = "14: Pulse Counter 1"]
74    PCNT1 = 14,
75    #[doc = "15: Pulse Counter 2"]
76    PCNT2 = 15,
77    #[doc = "16: CRYOTIMER"]
78    CRYOTIMER = 16,
79    #[doc = "17: Clock Management Unit"]
80    CMU = 17,
81    #[doc = "23: Digital to Analog Converter 0"]
82    VDAC0 = 23,
83    #[doc = "24: Low Energy Sensor Interface"]
84    LESENSEL = 24,
85    #[doc = "25: Low Energy Sensor Interface"]
86    LESENSEH = 25,
87    #[doc = "26: Low Energy Sensor Interface"]
88    LESENSED = 26,
89    #[doc = "27: Low Energy Sensor Interface"]
90    LESENSE = 27,
91    #[doc = "28: Analog Comparator 1"]
92    ACMP2 = 28,
93    #[doc = "29: Analog Comparator 3"]
94    ACMP3 = 29,
95    #[doc = "30: Analog to Digital Converter 0"]
96    ADC1 = 30,
97    #[doc = "48: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
98    USART0 = 48,
99    #[doc = "49: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
100    USART1 = 49,
101    #[doc = "50: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
102    USART2 = 50,
103    #[doc = "51: Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
104    USART3 = 51,
105    #[doc = "52: Universal Synchronous/Asynchronous Receiver/Transmitter 4"]
106    USART4 = 52,
107    #[doc = "53: Universal Synchronous/Asynchronous Receiver/Transmitter 5"]
108    USART5 = 53,
109    #[doc = "54: Universal Asynchronous Receiver/Transmitter 0"]
110    UART0 = 54,
111    #[doc = "55: Universal Asynchronous Receiver/Transmitter 1"]
112    UART1 = 55,
113    #[doc = "60: Timer 0"]
114    TIMER0 = 60,
115    #[doc = "61: Timer 1"]
116    TIMER1 = 61,
117    #[doc = "62: Timer 2"]
118    TIMER2 = 62,
119    #[doc = "64: Universal Serial Bus Interface"]
120    USB = 64,
121    #[doc = "67: `1000011`"]
122    CM4 = 67,
123    #[doc = "80: Timer 3"]
124    TIMER3 = 80,
125    #[doc = "82: Wide Timer 0"]
126    WTIMER0 = 82,
127    #[doc = "83: Wide Timer 0"]
128    WTIMER1 = 83,
129    #[doc = "84: Wide Timer 2"]
130    WTIMER2 = 84,
131    #[doc = "85: Wide Timer 3"]
132    WTIMER3 = 85,
133    #[doc = "98: Timer 4"]
134    TIMER4 = 98,
135    #[doc = "99: Timer 5"]
136    TIMER5 = 99,
137    #[doc = "100: Timer 6"]
138    TIMER6 = 100,
139}
140impl From<SOURCESEL_A> for u8 {
141    #[inline(always)]
142    fn from(variant: SOURCESEL_A) -> Self {
143        variant as _
144    }
145}
146#[doc = "Field `SOURCESEL` reader - Source Select"]
147pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
148impl SOURCESEL_R {
149    #[doc = "Get enumerated values variant"]
150    #[inline(always)]
151    pub fn variant(&self) -> Option<SOURCESEL_A> {
152        match self.bits {
153            0 => Some(SOURCESEL_A::NONE),
154            1 => Some(SOURCESEL_A::PRSL),
155            2 => Some(SOURCESEL_A::PRS),
156            3 => Some(SOURCESEL_A::PRSH),
157            4 => Some(SOURCESEL_A::ACMP0),
158            5 => Some(SOURCESEL_A::ACMP1),
159            6 => Some(SOURCESEL_A::ADC0),
160            7 => Some(SOURCESEL_A::RTC),
161            8 => Some(SOURCESEL_A::RTCC),
162            9 => Some(SOURCESEL_A::GPIOL),
163            10 => Some(SOURCESEL_A::GPIOH),
164            11 => Some(SOURCESEL_A::LETIMER0),
165            12 => Some(SOURCESEL_A::LETIMER1),
166            13 => Some(SOURCESEL_A::PCNT0),
167            14 => Some(SOURCESEL_A::PCNT1),
168            15 => Some(SOURCESEL_A::PCNT2),
169            16 => Some(SOURCESEL_A::CRYOTIMER),
170            17 => Some(SOURCESEL_A::CMU),
171            23 => Some(SOURCESEL_A::VDAC0),
172            24 => Some(SOURCESEL_A::LESENSEL),
173            25 => Some(SOURCESEL_A::LESENSEH),
174            26 => Some(SOURCESEL_A::LESENSED),
175            27 => Some(SOURCESEL_A::LESENSE),
176            28 => Some(SOURCESEL_A::ACMP2),
177            29 => Some(SOURCESEL_A::ACMP3),
178            30 => Some(SOURCESEL_A::ADC1),
179            48 => Some(SOURCESEL_A::USART0),
180            49 => Some(SOURCESEL_A::USART1),
181            50 => Some(SOURCESEL_A::USART2),
182            51 => Some(SOURCESEL_A::USART3),
183            52 => Some(SOURCESEL_A::USART4),
184            53 => Some(SOURCESEL_A::USART5),
185            54 => Some(SOURCESEL_A::UART0),
186            55 => Some(SOURCESEL_A::UART1),
187            60 => Some(SOURCESEL_A::TIMER0),
188            61 => Some(SOURCESEL_A::TIMER1),
189            62 => Some(SOURCESEL_A::TIMER2),
190            64 => Some(SOURCESEL_A::USB),
191            67 => Some(SOURCESEL_A::CM4),
192            80 => Some(SOURCESEL_A::TIMER3),
193            82 => Some(SOURCESEL_A::WTIMER0),
194            83 => Some(SOURCESEL_A::WTIMER1),
195            84 => Some(SOURCESEL_A::WTIMER2),
196            85 => Some(SOURCESEL_A::WTIMER3),
197            98 => Some(SOURCESEL_A::TIMER4),
198            99 => Some(SOURCESEL_A::TIMER5),
199            100 => Some(SOURCESEL_A::TIMER6),
200            _ => None,
201        }
202    }
203    #[doc = "Checks if the value of the field is `NONE`"]
204    #[inline(always)]
205    pub fn is_none(&self) -> bool {
206        *self == SOURCESEL_A::NONE
207    }
208    #[doc = "Checks if the value of the field is `PRSL`"]
209    #[inline(always)]
210    pub fn is_prsl(&self) -> bool {
211        *self == SOURCESEL_A::PRSL
212    }
213    #[doc = "Checks if the value of the field is `PRS`"]
214    #[inline(always)]
215    pub fn is_prs(&self) -> bool {
216        *self == SOURCESEL_A::PRS
217    }
218    #[doc = "Checks if the value of the field is `PRSH`"]
219    #[inline(always)]
220    pub fn is_prsh(&self) -> bool {
221        *self == SOURCESEL_A::PRSH
222    }
223    #[doc = "Checks if the value of the field is `ACMP0`"]
224    #[inline(always)]
225    pub fn is_acmp0(&self) -> bool {
226        *self == SOURCESEL_A::ACMP0
227    }
228    #[doc = "Checks if the value of the field is `ACMP1`"]
229    #[inline(always)]
230    pub fn is_acmp1(&self) -> bool {
231        *self == SOURCESEL_A::ACMP1
232    }
233    #[doc = "Checks if the value of the field is `ADC0`"]
234    #[inline(always)]
235    pub fn is_adc0(&self) -> bool {
236        *self == SOURCESEL_A::ADC0
237    }
238    #[doc = "Checks if the value of the field is `RTC`"]
239    #[inline(always)]
240    pub fn is_rtc(&self) -> bool {
241        *self == SOURCESEL_A::RTC
242    }
243    #[doc = "Checks if the value of the field is `RTCC`"]
244    #[inline(always)]
245    pub fn is_rtcc(&self) -> bool {
246        *self == SOURCESEL_A::RTCC
247    }
248    #[doc = "Checks if the value of the field is `GPIOL`"]
249    #[inline(always)]
250    pub fn is_gpiol(&self) -> bool {
251        *self == SOURCESEL_A::GPIOL
252    }
253    #[doc = "Checks if the value of the field is `GPIOH`"]
254    #[inline(always)]
255    pub fn is_gpioh(&self) -> bool {
256        *self == SOURCESEL_A::GPIOH
257    }
258    #[doc = "Checks if the value of the field is `LETIMER0`"]
259    #[inline(always)]
260    pub fn is_letimer0(&self) -> bool {
261        *self == SOURCESEL_A::LETIMER0
262    }
263    #[doc = "Checks if the value of the field is `LETIMER1`"]
264    #[inline(always)]
265    pub fn is_letimer1(&self) -> bool {
266        *self == SOURCESEL_A::LETIMER1
267    }
268    #[doc = "Checks if the value of the field is `PCNT0`"]
269    #[inline(always)]
270    pub fn is_pcnt0(&self) -> bool {
271        *self == SOURCESEL_A::PCNT0
272    }
273    #[doc = "Checks if the value of the field is `PCNT1`"]
274    #[inline(always)]
275    pub fn is_pcnt1(&self) -> bool {
276        *self == SOURCESEL_A::PCNT1
277    }
278    #[doc = "Checks if the value of the field is `PCNT2`"]
279    #[inline(always)]
280    pub fn is_pcnt2(&self) -> bool {
281        *self == SOURCESEL_A::PCNT2
282    }
283    #[doc = "Checks if the value of the field is `CRYOTIMER`"]
284    #[inline(always)]
285    pub fn is_cryotimer(&self) -> bool {
286        *self == SOURCESEL_A::CRYOTIMER
287    }
288    #[doc = "Checks if the value of the field is `CMU`"]
289    #[inline(always)]
290    pub fn is_cmu(&self) -> bool {
291        *self == SOURCESEL_A::CMU
292    }
293    #[doc = "Checks if the value of the field is `VDAC0`"]
294    #[inline(always)]
295    pub fn is_vdac0(&self) -> bool {
296        *self == SOURCESEL_A::VDAC0
297    }
298    #[doc = "Checks if the value of the field is `LESENSEL`"]
299    #[inline(always)]
300    pub fn is_lesensel(&self) -> bool {
301        *self == SOURCESEL_A::LESENSEL
302    }
303    #[doc = "Checks if the value of the field is `LESENSEH`"]
304    #[inline(always)]
305    pub fn is_lesenseh(&self) -> bool {
306        *self == SOURCESEL_A::LESENSEH
307    }
308    #[doc = "Checks if the value of the field is `LESENSED`"]
309    #[inline(always)]
310    pub fn is_lesensed(&self) -> bool {
311        *self == SOURCESEL_A::LESENSED
312    }
313    #[doc = "Checks if the value of the field is `LESENSE`"]
314    #[inline(always)]
315    pub fn is_lesense(&self) -> bool {
316        *self == SOURCESEL_A::LESENSE
317    }
318    #[doc = "Checks if the value of the field is `ACMP2`"]
319    #[inline(always)]
320    pub fn is_acmp2(&self) -> bool {
321        *self == SOURCESEL_A::ACMP2
322    }
323    #[doc = "Checks if the value of the field is `ACMP3`"]
324    #[inline(always)]
325    pub fn is_acmp3(&self) -> bool {
326        *self == SOURCESEL_A::ACMP3
327    }
328    #[doc = "Checks if the value of the field is `ADC1`"]
329    #[inline(always)]
330    pub fn is_adc1(&self) -> bool {
331        *self == SOURCESEL_A::ADC1
332    }
333    #[doc = "Checks if the value of the field is `USART0`"]
334    #[inline(always)]
335    pub fn is_usart0(&self) -> bool {
336        *self == SOURCESEL_A::USART0
337    }
338    #[doc = "Checks if the value of the field is `USART1`"]
339    #[inline(always)]
340    pub fn is_usart1(&self) -> bool {
341        *self == SOURCESEL_A::USART1
342    }
343    #[doc = "Checks if the value of the field is `USART2`"]
344    #[inline(always)]
345    pub fn is_usart2(&self) -> bool {
346        *self == SOURCESEL_A::USART2
347    }
348    #[doc = "Checks if the value of the field is `USART3`"]
349    #[inline(always)]
350    pub fn is_usart3(&self) -> bool {
351        *self == SOURCESEL_A::USART3
352    }
353    #[doc = "Checks if the value of the field is `USART4`"]
354    #[inline(always)]
355    pub fn is_usart4(&self) -> bool {
356        *self == SOURCESEL_A::USART4
357    }
358    #[doc = "Checks if the value of the field is `USART5`"]
359    #[inline(always)]
360    pub fn is_usart5(&self) -> bool {
361        *self == SOURCESEL_A::USART5
362    }
363    #[doc = "Checks if the value of the field is `UART0`"]
364    #[inline(always)]
365    pub fn is_uart0(&self) -> bool {
366        *self == SOURCESEL_A::UART0
367    }
368    #[doc = "Checks if the value of the field is `UART1`"]
369    #[inline(always)]
370    pub fn is_uart1(&self) -> bool {
371        *self == SOURCESEL_A::UART1
372    }
373    #[doc = "Checks if the value of the field is `TIMER0`"]
374    #[inline(always)]
375    pub fn is_timer0(&self) -> bool {
376        *self == SOURCESEL_A::TIMER0
377    }
378    #[doc = "Checks if the value of the field is `TIMER1`"]
379    #[inline(always)]
380    pub fn is_timer1(&self) -> bool {
381        *self == SOURCESEL_A::TIMER1
382    }
383    #[doc = "Checks if the value of the field is `TIMER2`"]
384    #[inline(always)]
385    pub fn is_timer2(&self) -> bool {
386        *self == SOURCESEL_A::TIMER2
387    }
388    #[doc = "Checks if the value of the field is `USB`"]
389    #[inline(always)]
390    pub fn is_usb(&self) -> bool {
391        *self == SOURCESEL_A::USB
392    }
393    #[doc = "Checks if the value of the field is `CM4`"]
394    #[inline(always)]
395    pub fn is_cm4(&self) -> bool {
396        *self == SOURCESEL_A::CM4
397    }
398    #[doc = "Checks if the value of the field is `TIMER3`"]
399    #[inline(always)]
400    pub fn is_timer3(&self) -> bool {
401        *self == SOURCESEL_A::TIMER3
402    }
403    #[doc = "Checks if the value of the field is `WTIMER0`"]
404    #[inline(always)]
405    pub fn is_wtimer0(&self) -> bool {
406        *self == SOURCESEL_A::WTIMER0
407    }
408    #[doc = "Checks if the value of the field is `WTIMER1`"]
409    #[inline(always)]
410    pub fn is_wtimer1(&self) -> bool {
411        *self == SOURCESEL_A::WTIMER1
412    }
413    #[doc = "Checks if the value of the field is `WTIMER2`"]
414    #[inline(always)]
415    pub fn is_wtimer2(&self) -> bool {
416        *self == SOURCESEL_A::WTIMER2
417    }
418    #[doc = "Checks if the value of the field is `WTIMER3`"]
419    #[inline(always)]
420    pub fn is_wtimer3(&self) -> bool {
421        *self == SOURCESEL_A::WTIMER3
422    }
423    #[doc = "Checks if the value of the field is `TIMER4`"]
424    #[inline(always)]
425    pub fn is_timer4(&self) -> bool {
426        *self == SOURCESEL_A::TIMER4
427    }
428    #[doc = "Checks if the value of the field is `TIMER5`"]
429    #[inline(always)]
430    pub fn is_timer5(&self) -> bool {
431        *self == SOURCESEL_A::TIMER5
432    }
433    #[doc = "Checks if the value of the field is `TIMER6`"]
434    #[inline(always)]
435    pub fn is_timer6(&self) -> bool {
436        *self == SOURCESEL_A::TIMER6
437    }
438}
439#[doc = "Field `SOURCESEL` writer - Source Select"]
440pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH14_CTRL_SPEC, u8, SOURCESEL_A, 7, 8>;
441impl<'a> SOURCESEL_W<'a> {
442    #[doc = "No source selected"]
443    #[inline(always)]
444    pub fn none(self) -> &'a mut W {
445        self.variant(SOURCESEL_A::NONE)
446    }
447    #[doc = "Peripheral Reflex System"]
448    #[inline(always)]
449    pub fn prsl(self) -> &'a mut W {
450        self.variant(SOURCESEL_A::PRSL)
451    }
452    #[doc = "Peripheral Reflex System"]
453    #[inline(always)]
454    pub fn prs(self) -> &'a mut W {
455        self.variant(SOURCESEL_A::PRS)
456    }
457    #[doc = "Peripheral Reflex System"]
458    #[inline(always)]
459    pub fn prsh(self) -> &'a mut W {
460        self.variant(SOURCESEL_A::PRSH)
461    }
462    #[doc = "Analog Comparator 0"]
463    #[inline(always)]
464    pub fn acmp0(self) -> &'a mut W {
465        self.variant(SOURCESEL_A::ACMP0)
466    }
467    #[doc = "Analog Comparator 1"]
468    #[inline(always)]
469    pub fn acmp1(self) -> &'a mut W {
470        self.variant(SOURCESEL_A::ACMP1)
471    }
472    #[doc = "Analog to Digital Converter 0"]
473    #[inline(always)]
474    pub fn adc0(self) -> &'a mut W {
475        self.variant(SOURCESEL_A::ADC0)
476    }
477    #[doc = "Real-Time Counter"]
478    #[inline(always)]
479    pub fn rtc(self) -> &'a mut W {
480        self.variant(SOURCESEL_A::RTC)
481    }
482    #[doc = "Real-Time Counter and Calendar"]
483    #[inline(always)]
484    pub fn rtcc(self) -> &'a mut W {
485        self.variant(SOURCESEL_A::RTCC)
486    }
487    #[doc = "General purpose Input/Output"]
488    #[inline(always)]
489    pub fn gpiol(self) -> &'a mut W {
490        self.variant(SOURCESEL_A::GPIOL)
491    }
492    #[doc = "General purpose Input/Output"]
493    #[inline(always)]
494    pub fn gpioh(self) -> &'a mut W {
495        self.variant(SOURCESEL_A::GPIOH)
496    }
497    #[doc = "Low Energy Timer 0"]
498    #[inline(always)]
499    pub fn letimer0(self) -> &'a mut W {
500        self.variant(SOURCESEL_A::LETIMER0)
501    }
502    #[doc = "Low Energy Timer 1"]
503    #[inline(always)]
504    pub fn letimer1(self) -> &'a mut W {
505        self.variant(SOURCESEL_A::LETIMER1)
506    }
507    #[doc = "Pulse Counter 0"]
508    #[inline(always)]
509    pub fn pcnt0(self) -> &'a mut W {
510        self.variant(SOURCESEL_A::PCNT0)
511    }
512    #[doc = "Pulse Counter 1"]
513    #[inline(always)]
514    pub fn pcnt1(self) -> &'a mut W {
515        self.variant(SOURCESEL_A::PCNT1)
516    }
517    #[doc = "Pulse Counter 2"]
518    #[inline(always)]
519    pub fn pcnt2(self) -> &'a mut W {
520        self.variant(SOURCESEL_A::PCNT2)
521    }
522    #[doc = "CRYOTIMER"]
523    #[inline(always)]
524    pub fn cryotimer(self) -> &'a mut W {
525        self.variant(SOURCESEL_A::CRYOTIMER)
526    }
527    #[doc = "Clock Management Unit"]
528    #[inline(always)]
529    pub fn cmu(self) -> &'a mut W {
530        self.variant(SOURCESEL_A::CMU)
531    }
532    #[doc = "Digital to Analog Converter 0"]
533    #[inline(always)]
534    pub fn vdac0(self) -> &'a mut W {
535        self.variant(SOURCESEL_A::VDAC0)
536    }
537    #[doc = "Low Energy Sensor Interface"]
538    #[inline(always)]
539    pub fn lesensel(self) -> &'a mut W {
540        self.variant(SOURCESEL_A::LESENSEL)
541    }
542    #[doc = "Low Energy Sensor Interface"]
543    #[inline(always)]
544    pub fn lesenseh(self) -> &'a mut W {
545        self.variant(SOURCESEL_A::LESENSEH)
546    }
547    #[doc = "Low Energy Sensor Interface"]
548    #[inline(always)]
549    pub fn lesensed(self) -> &'a mut W {
550        self.variant(SOURCESEL_A::LESENSED)
551    }
552    #[doc = "Low Energy Sensor Interface"]
553    #[inline(always)]
554    pub fn lesense(self) -> &'a mut W {
555        self.variant(SOURCESEL_A::LESENSE)
556    }
557    #[doc = "Analog Comparator 1"]
558    #[inline(always)]
559    pub fn acmp2(self) -> &'a mut W {
560        self.variant(SOURCESEL_A::ACMP2)
561    }
562    #[doc = "Analog Comparator 3"]
563    #[inline(always)]
564    pub fn acmp3(self) -> &'a mut W {
565        self.variant(SOURCESEL_A::ACMP3)
566    }
567    #[doc = "Analog to Digital Converter 0"]
568    #[inline(always)]
569    pub fn adc1(self) -> &'a mut W {
570        self.variant(SOURCESEL_A::ADC1)
571    }
572    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
573    #[inline(always)]
574    pub fn usart0(self) -> &'a mut W {
575        self.variant(SOURCESEL_A::USART0)
576    }
577    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
578    #[inline(always)]
579    pub fn usart1(self) -> &'a mut W {
580        self.variant(SOURCESEL_A::USART1)
581    }
582    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
583    #[inline(always)]
584    pub fn usart2(self) -> &'a mut W {
585        self.variant(SOURCESEL_A::USART2)
586    }
587    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
588    #[inline(always)]
589    pub fn usart3(self) -> &'a mut W {
590        self.variant(SOURCESEL_A::USART3)
591    }
592    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 4"]
593    #[inline(always)]
594    pub fn usart4(self) -> &'a mut W {
595        self.variant(SOURCESEL_A::USART4)
596    }
597    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 5"]
598    #[inline(always)]
599    pub fn usart5(self) -> &'a mut W {
600        self.variant(SOURCESEL_A::USART5)
601    }
602    #[doc = "Universal Asynchronous Receiver/Transmitter 0"]
603    #[inline(always)]
604    pub fn uart0(self) -> &'a mut W {
605        self.variant(SOURCESEL_A::UART0)
606    }
607    #[doc = "Universal Asynchronous Receiver/Transmitter 1"]
608    #[inline(always)]
609    pub fn uart1(self) -> &'a mut W {
610        self.variant(SOURCESEL_A::UART1)
611    }
612    #[doc = "Timer 0"]
613    #[inline(always)]
614    pub fn timer0(self) -> &'a mut W {
615        self.variant(SOURCESEL_A::TIMER0)
616    }
617    #[doc = "Timer 1"]
618    #[inline(always)]
619    pub fn timer1(self) -> &'a mut W {
620        self.variant(SOURCESEL_A::TIMER1)
621    }
622    #[doc = "Timer 2"]
623    #[inline(always)]
624    pub fn timer2(self) -> &'a mut W {
625        self.variant(SOURCESEL_A::TIMER2)
626    }
627    #[doc = "Universal Serial Bus Interface"]
628    #[inline(always)]
629    pub fn usb(self) -> &'a mut W {
630        self.variant(SOURCESEL_A::USB)
631    }
632    #[doc = "`1000011`"]
633    #[inline(always)]
634    pub fn cm4(self) -> &'a mut W {
635        self.variant(SOURCESEL_A::CM4)
636    }
637    #[doc = "Timer 3"]
638    #[inline(always)]
639    pub fn timer3(self) -> &'a mut W {
640        self.variant(SOURCESEL_A::TIMER3)
641    }
642    #[doc = "Wide Timer 0"]
643    #[inline(always)]
644    pub fn wtimer0(self) -> &'a mut W {
645        self.variant(SOURCESEL_A::WTIMER0)
646    }
647    #[doc = "Wide Timer 0"]
648    #[inline(always)]
649    pub fn wtimer1(self) -> &'a mut W {
650        self.variant(SOURCESEL_A::WTIMER1)
651    }
652    #[doc = "Wide Timer 2"]
653    #[inline(always)]
654    pub fn wtimer2(self) -> &'a mut W {
655        self.variant(SOURCESEL_A::WTIMER2)
656    }
657    #[doc = "Wide Timer 3"]
658    #[inline(always)]
659    pub fn wtimer3(self) -> &'a mut W {
660        self.variant(SOURCESEL_A::WTIMER3)
661    }
662    #[doc = "Timer 4"]
663    #[inline(always)]
664    pub fn timer4(self) -> &'a mut W {
665        self.variant(SOURCESEL_A::TIMER4)
666    }
667    #[doc = "Timer 5"]
668    #[inline(always)]
669    pub fn timer5(self) -> &'a mut W {
670        self.variant(SOURCESEL_A::TIMER5)
671    }
672    #[doc = "Timer 6"]
673    #[inline(always)]
674    pub fn timer6(self) -> &'a mut W {
675        self.variant(SOURCESEL_A::TIMER6)
676    }
677}
678#[doc = "Edge Detect Select\n\nValue on reset: 0"]
679#[derive(Clone, Copy, Debug, PartialEq)]
680#[repr(u8)]
681pub enum EDSEL_A {
682    #[doc = "0: Signal is left as it is"]
683    OFF = 0,
684    #[doc = "1: A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
685    POSEDGE = 1,
686    #[doc = "2: A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
687    NEGEDGE = 2,
688    #[doc = "3: A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
689    BOTHEDGES = 3,
690}
691impl From<EDSEL_A> for u8 {
692    #[inline(always)]
693    fn from(variant: EDSEL_A) -> Self {
694        variant as _
695    }
696}
697#[doc = "Field `EDSEL` reader - Edge Detect Select"]
698pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
699impl EDSEL_R {
700    #[doc = "Get enumerated values variant"]
701    #[inline(always)]
702    pub fn variant(&self) -> EDSEL_A {
703        match self.bits {
704            0 => EDSEL_A::OFF,
705            1 => EDSEL_A::POSEDGE,
706            2 => EDSEL_A::NEGEDGE,
707            3 => EDSEL_A::BOTHEDGES,
708            _ => unreachable!(),
709        }
710    }
711    #[doc = "Checks if the value of the field is `OFF`"]
712    #[inline(always)]
713    pub fn is_off(&self) -> bool {
714        *self == EDSEL_A::OFF
715    }
716    #[doc = "Checks if the value of the field is `POSEDGE`"]
717    #[inline(always)]
718    pub fn is_posedge(&self) -> bool {
719        *self == EDSEL_A::POSEDGE
720    }
721    #[doc = "Checks if the value of the field is `NEGEDGE`"]
722    #[inline(always)]
723    pub fn is_negedge(&self) -> bool {
724        *self == EDSEL_A::NEGEDGE
725    }
726    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
727    #[inline(always)]
728    pub fn is_bothedges(&self) -> bool {
729        *self == EDSEL_A::BOTHEDGES
730    }
731}
732#[doc = "Field `EDSEL` writer - Edge Detect Select"]
733pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH14_CTRL_SPEC, u8, EDSEL_A, 2, 20>;
734impl<'a> EDSEL_W<'a> {
735    #[doc = "Signal is left as it is"]
736    #[inline(always)]
737    pub fn off(self) -> &'a mut W {
738        self.variant(EDSEL_A::OFF)
739    }
740    #[doc = "A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
741    #[inline(always)]
742    pub fn posedge(self) -> &'a mut W {
743        self.variant(EDSEL_A::POSEDGE)
744    }
745    #[doc = "A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
746    #[inline(always)]
747    pub fn negedge(self) -> &'a mut W {
748        self.variant(EDSEL_A::NEGEDGE)
749    }
750    #[doc = "A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
751    #[inline(always)]
752    pub fn bothedges(self) -> &'a mut W {
753        self.variant(EDSEL_A::BOTHEDGES)
754    }
755}
756#[doc = "Field `STRETCH` reader - Stretch Channel Output"]
757pub type STRETCH_R = crate::BitReader<bool>;
758#[doc = "Field `STRETCH` writer - Stretch Channel Output"]
759pub type STRETCH_W<'a> = crate::BitWriter<'a, u32, CH14_CTRL_SPEC, bool, 25>;
760#[doc = "Field `INV` reader - Invert Channel"]
761pub type INV_R = crate::BitReader<bool>;
762#[doc = "Field `INV` writer - Invert Channel"]
763pub type INV_W<'a> = crate::BitWriter<'a, u32, CH14_CTRL_SPEC, bool, 26>;
764#[doc = "Field `ORPREV` reader - Or Previous"]
765pub type ORPREV_R = crate::BitReader<bool>;
766#[doc = "Field `ORPREV` writer - Or Previous"]
767pub type ORPREV_W<'a> = crate::BitWriter<'a, u32, CH14_CTRL_SPEC, bool, 27>;
768#[doc = "Field `ANDNEXT` reader - And Next"]
769pub type ANDNEXT_R = crate::BitReader<bool>;
770#[doc = "Field `ANDNEXT` writer - And Next"]
771pub type ANDNEXT_W<'a> = crate::BitWriter<'a, u32, CH14_CTRL_SPEC, bool, 28>;
772#[doc = "Field `ASYNC` reader - Asynchronous Reflex"]
773pub type ASYNC_R = crate::BitReader<bool>;
774#[doc = "Field `ASYNC` writer - Asynchronous Reflex"]
775pub type ASYNC_W<'a> = crate::BitWriter<'a, u32, CH14_CTRL_SPEC, bool, 30>;
776impl R {
777    #[doc = "Bits 0:2 - Signal Select"]
778    #[inline(always)]
779    pub fn sigsel(&self) -> SIGSEL_R {
780        SIGSEL_R::new((self.bits & 7) as u8)
781    }
782    #[doc = "Bits 8:14 - Source Select"]
783    #[inline(always)]
784    pub fn sourcesel(&self) -> SOURCESEL_R {
785        SOURCESEL_R::new(((self.bits >> 8) & 0x7f) as u8)
786    }
787    #[doc = "Bits 20:21 - Edge Detect Select"]
788    #[inline(always)]
789    pub fn edsel(&self) -> EDSEL_R {
790        EDSEL_R::new(((self.bits >> 20) & 3) as u8)
791    }
792    #[doc = "Bit 25 - Stretch Channel Output"]
793    #[inline(always)]
794    pub fn stretch(&self) -> STRETCH_R {
795        STRETCH_R::new(((self.bits >> 25) & 1) != 0)
796    }
797    #[doc = "Bit 26 - Invert Channel"]
798    #[inline(always)]
799    pub fn inv(&self) -> INV_R {
800        INV_R::new(((self.bits >> 26) & 1) != 0)
801    }
802    #[doc = "Bit 27 - Or Previous"]
803    #[inline(always)]
804    pub fn orprev(&self) -> ORPREV_R {
805        ORPREV_R::new(((self.bits >> 27) & 1) != 0)
806    }
807    #[doc = "Bit 28 - And Next"]
808    #[inline(always)]
809    pub fn andnext(&self) -> ANDNEXT_R {
810        ANDNEXT_R::new(((self.bits >> 28) & 1) != 0)
811    }
812    #[doc = "Bit 30 - Asynchronous Reflex"]
813    #[inline(always)]
814    pub fn async_(&self) -> ASYNC_R {
815        ASYNC_R::new(((self.bits >> 30) & 1) != 0)
816    }
817}
818impl W {
819    #[doc = "Bits 0:2 - Signal Select"]
820    #[inline(always)]
821    pub fn sigsel(&mut self) -> SIGSEL_W {
822        SIGSEL_W::new(self)
823    }
824    #[doc = "Bits 8:14 - Source Select"]
825    #[inline(always)]
826    pub fn sourcesel(&mut self) -> SOURCESEL_W {
827        SOURCESEL_W::new(self)
828    }
829    #[doc = "Bits 20:21 - Edge Detect Select"]
830    #[inline(always)]
831    pub fn edsel(&mut self) -> EDSEL_W {
832        EDSEL_W::new(self)
833    }
834    #[doc = "Bit 25 - Stretch Channel Output"]
835    #[inline(always)]
836    pub fn stretch(&mut self) -> STRETCH_W {
837        STRETCH_W::new(self)
838    }
839    #[doc = "Bit 26 - Invert Channel"]
840    #[inline(always)]
841    pub fn inv(&mut self) -> INV_W {
842        INV_W::new(self)
843    }
844    #[doc = "Bit 27 - Or Previous"]
845    #[inline(always)]
846    pub fn orprev(&mut self) -> ORPREV_W {
847        ORPREV_W::new(self)
848    }
849    #[doc = "Bit 28 - And Next"]
850    #[inline(always)]
851    pub fn andnext(&mut self) -> ANDNEXT_W {
852        ANDNEXT_W::new(self)
853    }
854    #[doc = "Bit 30 - Asynchronous Reflex"]
855    #[inline(always)]
856    pub fn async_(&mut self) -> ASYNC_W {
857        ASYNC_W::new(self)
858    }
859    #[doc = "Writes raw bits to the register."]
860    #[inline(always)]
861    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
862        self.0.bits(bits);
863        self
864    }
865}
866#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch14_ctrl](index.html) module"]
867pub struct CH14_CTRL_SPEC;
868impl crate::RegisterSpec for CH14_CTRL_SPEC {
869    type Ux = u32;
870}
871#[doc = "`read()` method returns [ch14_ctrl::R](R) reader structure"]
872impl crate::Readable for CH14_CTRL_SPEC {
873    type Reader = R;
874}
875#[doc = "`write(|w| ..)` method takes [ch14_ctrl::W](W) writer structure"]
876impl crate::Writable for CH14_CTRL_SPEC {
877    type Writer = W;
878}
879#[doc = "`reset()` method sets CH14_CTRL to value 0"]
880impl crate::Resettable for CH14_CTRL_SPEC {
881    #[inline(always)]
882    fn reset_value() -> Self::Ux {
883        0
884    }
885}
efm32gg11b420_pac/prs/ch14_ctrl.rs

efm32gg11b420_pac/prs/
ch14_ctrl.rs
