efm32gg11b420_pac/sdio/
ctrl.rs1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `ITAPDLYEN` reader - Selective Tap Delay Line Enable on Rxclk_in"]
38pub type ITAPDLYEN_R = crate::BitReader<bool>;
39#[doc = "Field `ITAPDLYEN` writer - Selective Tap Delay Line Enable on Rxclk_in"]
40pub type ITAPDLYEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 0>;
41#[doc = "Field `ITAPDLYSEL` reader - Selects One of 32 Taps on the Rxclk_in Line"]
42pub type ITAPDLYSEL_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `ITAPDLYSEL` writer - Selects One of 32 Taps on the Rxclk_in Line"]
44pub type ITAPDLYSEL_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, u8, 5, 1>;
45#[doc = "Field `ITAPCHGWIN` reader - Gating Signal for Tap Delay Change"]
46pub type ITAPCHGWIN_R = crate::BitReader<bool>;
47#[doc = "Field `ITAPCHGWIN` writer - Gating Signal for Tap Delay Change"]
48pub type ITAPCHGWIN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 6>;
49#[doc = "Field `OTAPDLYEN` reader - Selective Tap Delay Line Enable on SDIO_CLK Pin"]
50pub type OTAPDLYEN_R = crate::BitReader<bool>;
51#[doc = "Field `OTAPDLYEN` writer - Selective Tap Delay Line Enable on SDIO_CLK Pin"]
52pub type OTAPDLYEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 7>;
53#[doc = "Field `OTAPDLYSEL` reader - Selects One of 32 Taps on the SDIO_CLK Pin"]
54pub type OTAPDLYSEL_R = crate::FieldReader<u8, u8>;
55#[doc = "Field `OTAPDLYSEL` writer - Selects One of 32 Taps on the SDIO_CLK Pin"]
56pub type OTAPDLYSEL_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, u8, 4, 8>;
57#[doc = "Field `TXDLYMUXSEL` reader - TX Delay Mux Selection"]
58pub type TXDLYMUXSEL_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `TXDLYMUXSEL` writer - TX Delay Mux Selection"]
60pub type TXDLYMUXSEL_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, u8, 2, 16>;
61impl R {
62 #[doc = "Bit 0 - Selective Tap Delay Line Enable on Rxclk_in"]
63 #[inline(always)]
64 pub fn itapdlyen(&self) -> ITAPDLYEN_R {
65 ITAPDLYEN_R::new((self.bits & 1) != 0)
66 }
67 #[doc = "Bits 1:5 - Selects One of 32 Taps on the Rxclk_in Line"]
68 #[inline(always)]
69 pub fn itapdlysel(&self) -> ITAPDLYSEL_R {
70 ITAPDLYSEL_R::new(((self.bits >> 1) & 0x1f) as u8)
71 }
72 #[doc = "Bit 6 - Gating Signal for Tap Delay Change"]
73 #[inline(always)]
74 pub fn itapchgwin(&self) -> ITAPCHGWIN_R {
75 ITAPCHGWIN_R::new(((self.bits >> 6) & 1) != 0)
76 }
77 #[doc = "Bit 7 - Selective Tap Delay Line Enable on SDIO_CLK Pin"]
78 #[inline(always)]
79 pub fn otapdlyen(&self) -> OTAPDLYEN_R {
80 OTAPDLYEN_R::new(((self.bits >> 7) & 1) != 0)
81 }
82 #[doc = "Bits 8:11 - Selects One of 32 Taps on the SDIO_CLK Pin"]
83 #[inline(always)]
84 pub fn otapdlysel(&self) -> OTAPDLYSEL_R {
85 OTAPDLYSEL_R::new(((self.bits >> 8) & 0x0f) as u8)
86 }
87 #[doc = "Bits 16:17 - TX Delay Mux Selection"]
88 #[inline(always)]
89 pub fn txdlymuxsel(&self) -> TXDLYMUXSEL_R {
90 TXDLYMUXSEL_R::new(((self.bits >> 16) & 3) as u8)
91 }
92}
93impl W {
94 #[doc = "Bit 0 - Selective Tap Delay Line Enable on Rxclk_in"]
95 #[inline(always)]
96 pub fn itapdlyen(&mut self) -> ITAPDLYEN_W {
97 ITAPDLYEN_W::new(self)
98 }
99 #[doc = "Bits 1:5 - Selects One of 32 Taps on the Rxclk_in Line"]
100 #[inline(always)]
101 pub fn itapdlysel(&mut self) -> ITAPDLYSEL_W {
102 ITAPDLYSEL_W::new(self)
103 }
104 #[doc = "Bit 6 - Gating Signal for Tap Delay Change"]
105 #[inline(always)]
106 pub fn itapchgwin(&mut self) -> ITAPCHGWIN_W {
107 ITAPCHGWIN_W::new(self)
108 }
109 #[doc = "Bit 7 - Selective Tap Delay Line Enable on SDIO_CLK Pin"]
110 #[inline(always)]
111 pub fn otapdlyen(&mut self) -> OTAPDLYEN_W {
112 OTAPDLYEN_W::new(self)
113 }
114 #[doc = "Bits 8:11 - Selects One of 32 Taps on the SDIO_CLK Pin"]
115 #[inline(always)]
116 pub fn otapdlysel(&mut self) -> OTAPDLYSEL_W {
117 OTAPDLYSEL_W::new(self)
118 }
119 #[doc = "Bits 16:17 - TX Delay Mux Selection"]
120 #[inline(always)]
121 pub fn txdlymuxsel(&mut self) -> TXDLYMUXSEL_W {
122 TXDLYMUXSEL_W::new(self)
123 }
124 #[doc = "Writes raw bits to the register."]
125 #[inline(always)]
126 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
127 self.0.bits(bits);
128 self
129 }
130}
131#[doc = "Core Control Signals\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
132pub struct CTRL_SPEC;
133impl crate::RegisterSpec for CTRL_SPEC {
134 type Ux = u32;
135}
136#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
137impl crate::Readable for CTRL_SPEC {
138 type Reader = R;
139}
140#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
141impl crate::Writable for CTRL_SPEC {
142 type Writer = W;
143}
144#[doc = "`reset()` method sets CTRL to value 0"]
145impl crate::Resettable for CTRL_SPEC {
146 #[inline(always)]
147 fn reset_value() -> Self::Ux {
148 0
149 }
150}