efm32gg11b420_pac/qspi0/
routepen.rs

1#[doc = "Register `ROUTEPEN` reader"]
2pub struct R(crate::R<ROUTEPEN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ROUTEPEN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ROUTEPEN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ROUTEPEN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ROUTEPEN` writer"]
17pub struct W(crate::W<ROUTEPEN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ROUTEPEN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ROUTEPEN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ROUTEPEN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SCLKPEN` reader - SCLK Pin Enable"]
38pub type SCLKPEN_R = crate::BitReader<bool>;
39#[doc = "Field `SCLKPEN` writer - SCLK Pin Enable"]
40pub type SCLKPEN_W<'a> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, 0>;
41#[doc = "Field `CS0PEN` reader - CS0 Pin Enable"]
42pub type CS0PEN_R = crate::BitReader<bool>;
43#[doc = "Field `CS0PEN` writer - CS0 Pin Enable"]
44pub type CS0PEN_W<'a> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, 1>;
45#[doc = "Field `CS1PEN` reader - CS1 Pin Enable"]
46pub type CS1PEN_R = crate::BitReader<bool>;
47#[doc = "Field `CS1PEN` writer - CS1 Pin Enable"]
48pub type CS1PEN_W<'a> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, 2>;
49#[doc = "Field `DQ0PEN` reader - DQ0 Pin Enable"]
50pub type DQ0PEN_R = crate::BitReader<bool>;
51#[doc = "Field `DQ0PEN` writer - DQ0 Pin Enable"]
52pub type DQ0PEN_W<'a> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, 5>;
53#[doc = "Field `DQ1PEN` reader - DQ1 Pin Enable"]
54pub type DQ1PEN_R = crate::BitReader<bool>;
55#[doc = "Field `DQ1PEN` writer - DQ1 Pin Enable"]
56pub type DQ1PEN_W<'a> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, 6>;
57#[doc = "Field `DQ2PEN` reader - DQ2 Pin Enable"]
58pub type DQ2PEN_R = crate::BitReader<bool>;
59#[doc = "Field `DQ2PEN` writer - DQ2 Pin Enable"]
60pub type DQ2PEN_W<'a> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, 7>;
61#[doc = "Field `DQ3PEN` reader - DQ3 Pin Enable"]
62pub type DQ3PEN_R = crate::BitReader<bool>;
63#[doc = "Field `DQ3PEN` writer - DQ3 Pin Enable"]
64pub type DQ3PEN_W<'a> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, 8>;
65#[doc = "Field `DQ4PEN` reader - DQ4 Pin Enable"]
66pub type DQ4PEN_R = crate::BitReader<bool>;
67#[doc = "Field `DQ4PEN` writer - DQ4 Pin Enable"]
68pub type DQ4PEN_W<'a> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, 9>;
69#[doc = "Field `DQ5PEN` reader - DQ5 Pin Enable"]
70pub type DQ5PEN_R = crate::BitReader<bool>;
71#[doc = "Field `DQ5PEN` writer - DQ5 Pin Enable"]
72pub type DQ5PEN_W<'a> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, 10>;
73#[doc = "Field `DQ6PEN` reader - DQ6 Pin Enable"]
74pub type DQ6PEN_R = crate::BitReader<bool>;
75#[doc = "Field `DQ6PEN` writer - DQ6 Pin Enable"]
76pub type DQ6PEN_W<'a> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, 11>;
77#[doc = "Field `DQ7PEN` reader - DQ7 Pin Enable"]
78pub type DQ7PEN_R = crate::BitReader<bool>;
79#[doc = "Field `DQ7PEN` writer - DQ7 Pin Enable"]
80pub type DQ7PEN_W<'a> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, 12>;
81#[doc = "Field `DQSPEN` reader - DQS Pin Enable"]
82pub type DQSPEN_R = crate::BitReader<bool>;
83#[doc = "Field `DQSPEN` writer - DQS Pin Enable"]
84pub type DQSPEN_W<'a> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, 13>;
85#[doc = "Field `SCLKINPEN` reader - SCLKIN Pin Enable"]
86pub type SCLKINPEN_R = crate::BitReader<bool>;
87#[doc = "Field `SCLKINPEN` writer - SCLKIN Pin Enable"]
88pub type SCLKINPEN_W<'a> = crate::BitWriter<'a, u32, ROUTEPEN_SPEC, bool, 14>;
89impl R {
90    #[doc = "Bit 0 - SCLK Pin Enable"]
91    #[inline(always)]
92    pub fn sclkpen(&self) -> SCLKPEN_R {
93        SCLKPEN_R::new((self.bits & 1) != 0)
94    }
95    #[doc = "Bit 1 - CS0 Pin Enable"]
96    #[inline(always)]
97    pub fn cs0pen(&self) -> CS0PEN_R {
98        CS0PEN_R::new(((self.bits >> 1) & 1) != 0)
99    }
100    #[doc = "Bit 2 - CS1 Pin Enable"]
101    #[inline(always)]
102    pub fn cs1pen(&self) -> CS1PEN_R {
103        CS1PEN_R::new(((self.bits >> 2) & 1) != 0)
104    }
105    #[doc = "Bit 5 - DQ0 Pin Enable"]
106    #[inline(always)]
107    pub fn dq0pen(&self) -> DQ0PEN_R {
108        DQ0PEN_R::new(((self.bits >> 5) & 1) != 0)
109    }
110    #[doc = "Bit 6 - DQ1 Pin Enable"]
111    #[inline(always)]
112    pub fn dq1pen(&self) -> DQ1PEN_R {
113        DQ1PEN_R::new(((self.bits >> 6) & 1) != 0)
114    }
115    #[doc = "Bit 7 - DQ2 Pin Enable"]
116    #[inline(always)]
117    pub fn dq2pen(&self) -> DQ2PEN_R {
118        DQ2PEN_R::new(((self.bits >> 7) & 1) != 0)
119    }
120    #[doc = "Bit 8 - DQ3 Pin Enable"]
121    #[inline(always)]
122    pub fn dq3pen(&self) -> DQ3PEN_R {
123        DQ3PEN_R::new(((self.bits >> 8) & 1) != 0)
124    }
125    #[doc = "Bit 9 - DQ4 Pin Enable"]
126    #[inline(always)]
127    pub fn dq4pen(&self) -> DQ4PEN_R {
128        DQ4PEN_R::new(((self.bits >> 9) & 1) != 0)
129    }
130    #[doc = "Bit 10 - DQ5 Pin Enable"]
131    #[inline(always)]
132    pub fn dq5pen(&self) -> DQ5PEN_R {
133        DQ5PEN_R::new(((self.bits >> 10) & 1) != 0)
134    }
135    #[doc = "Bit 11 - DQ6 Pin Enable"]
136    #[inline(always)]
137    pub fn dq6pen(&self) -> DQ6PEN_R {
138        DQ6PEN_R::new(((self.bits >> 11) & 1) != 0)
139    }
140    #[doc = "Bit 12 - DQ7 Pin Enable"]
141    #[inline(always)]
142    pub fn dq7pen(&self) -> DQ7PEN_R {
143        DQ7PEN_R::new(((self.bits >> 12) & 1) != 0)
144    }
145    #[doc = "Bit 13 - DQS Pin Enable"]
146    #[inline(always)]
147    pub fn dqspen(&self) -> DQSPEN_R {
148        DQSPEN_R::new(((self.bits >> 13) & 1) != 0)
149    }
150    #[doc = "Bit 14 - SCLKIN Pin Enable"]
151    #[inline(always)]
152    pub fn sclkinpen(&self) -> SCLKINPEN_R {
153        SCLKINPEN_R::new(((self.bits >> 14) & 1) != 0)
154    }
155}
156impl W {
157    #[doc = "Bit 0 - SCLK Pin Enable"]
158    #[inline(always)]
159    pub fn sclkpen(&mut self) -> SCLKPEN_W {
160        SCLKPEN_W::new(self)
161    }
162    #[doc = "Bit 1 - CS0 Pin Enable"]
163    #[inline(always)]
164    pub fn cs0pen(&mut self) -> CS0PEN_W {
165        CS0PEN_W::new(self)
166    }
167    #[doc = "Bit 2 - CS1 Pin Enable"]
168    #[inline(always)]
169    pub fn cs1pen(&mut self) -> CS1PEN_W {
170        CS1PEN_W::new(self)
171    }
172    #[doc = "Bit 5 - DQ0 Pin Enable"]
173    #[inline(always)]
174    pub fn dq0pen(&mut self) -> DQ0PEN_W {
175        DQ0PEN_W::new(self)
176    }
177    #[doc = "Bit 6 - DQ1 Pin Enable"]
178    #[inline(always)]
179    pub fn dq1pen(&mut self) -> DQ1PEN_W {
180        DQ1PEN_W::new(self)
181    }
182    #[doc = "Bit 7 - DQ2 Pin Enable"]
183    #[inline(always)]
184    pub fn dq2pen(&mut self) -> DQ2PEN_W {
185        DQ2PEN_W::new(self)
186    }
187    #[doc = "Bit 8 - DQ3 Pin Enable"]
188    #[inline(always)]
189    pub fn dq3pen(&mut self) -> DQ3PEN_W {
190        DQ3PEN_W::new(self)
191    }
192    #[doc = "Bit 9 - DQ4 Pin Enable"]
193    #[inline(always)]
194    pub fn dq4pen(&mut self) -> DQ4PEN_W {
195        DQ4PEN_W::new(self)
196    }
197    #[doc = "Bit 10 - DQ5 Pin Enable"]
198    #[inline(always)]
199    pub fn dq5pen(&mut self) -> DQ5PEN_W {
200        DQ5PEN_W::new(self)
201    }
202    #[doc = "Bit 11 - DQ6 Pin Enable"]
203    #[inline(always)]
204    pub fn dq6pen(&mut self) -> DQ6PEN_W {
205        DQ6PEN_W::new(self)
206    }
207    #[doc = "Bit 12 - DQ7 Pin Enable"]
208    #[inline(always)]
209    pub fn dq7pen(&mut self) -> DQ7PEN_W {
210        DQ7PEN_W::new(self)
211    }
212    #[doc = "Bit 13 - DQS Pin Enable"]
213    #[inline(always)]
214    pub fn dqspen(&mut self) -> DQSPEN_W {
215        DQSPEN_W::new(self)
216    }
217    #[doc = "Bit 14 - SCLKIN Pin Enable"]
218    #[inline(always)]
219    pub fn sclkinpen(&mut self) -> SCLKINPEN_W {
220        SCLKINPEN_W::new(self)
221    }
222    #[doc = "Writes raw bits to the register."]
223    #[inline(always)]
224    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
225        self.0.bits(bits);
226        self
227    }
228}
229#[doc = "I/O Routing Pin Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [routepen](index.html) module"]
230pub struct ROUTEPEN_SPEC;
231impl crate::RegisterSpec for ROUTEPEN_SPEC {
232    type Ux = u32;
233}
234#[doc = "`read()` method returns [routepen::R](R) reader structure"]
235impl crate::Readable for ROUTEPEN_SPEC {
236    type Reader = R;
237}
238#[doc = "`write(|w| ..)` method takes [routepen::W](W) writer structure"]
239impl crate::Writable for ROUTEPEN_SPEC {
240    type Writer = W;
241}
242#[doc = "`reset()` method sets ROUTEPEN to value 0"]
243impl crate::Resettable for ROUTEPEN_SPEC {
244    #[inline(always)]
245    fn reset_value() -> Self::Ux {
246        0
247    }
248}
efm32gg11b420_pac/qspi0/routepen.rs

efm32gg11b420_pac/qspi0/
routepen.rs
