efm32gg11b420_pac/msc/
ifs.rs

1#[doc = "Register `IFS` writer"]
2pub struct W(crate::W<IFS_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<IFS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<IFS_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<IFS_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `ERASE` writer - Set ERASE Interrupt Flag"]
23pub type ERASE_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 0>;
24#[doc = "Field `WRITE` writer - Set WRITE Interrupt Flag"]
25pub type WRITE_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 1>;
26#[doc = "Field `CHOF` writer - Set CHOF Interrupt Flag"]
27pub type CHOF_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 2>;
28#[doc = "Field `CMOF` writer - Set CMOF Interrupt Flag"]
29pub type CMOF_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 3>;
30#[doc = "Field `PWRUPF` writer - Set PWRUPF Interrupt Flag"]
31pub type PWRUPF_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 4>;
32#[doc = "Field `ICACHERR` writer - Set ICACHERR Interrupt Flag"]
33pub type ICACHERR_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 5>;
34#[doc = "Field `WDATAOV` writer - Set WDATAOV Interrupt Flag"]
35pub type WDATAOV_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 6>;
36#[doc = "Field `LVEWRITE` writer - Set LVEWRITE Interrupt Flag"]
37pub type LVEWRITE_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 8>;
38#[doc = "Field `RAMERR1B` writer - Set RAMERR1B Interrupt Flag"]
39pub type RAMERR1B_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 16>;
40#[doc = "Field `RAMERR2B` writer - Set RAMERR2B Interrupt Flag"]
41pub type RAMERR2B_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 17>;
42#[doc = "Field `RAM1ERR1B` writer - Set RAM1ERR1B Interrupt Flag"]
43pub type RAM1ERR1B_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 18>;
44#[doc = "Field `RAM1ERR2B` writer - Set RAM1ERR2B Interrupt Flag"]
45pub type RAM1ERR2B_W<'a> = crate::BitWriter<'a, u32, IFS_SPEC, bool, 19>;
46impl W {
47    #[doc = "Bit 0 - Set ERASE Interrupt Flag"]
48    #[inline(always)]
49    pub fn erase(&mut self) -> ERASE_W {
50        ERASE_W::new(self)
51    }
52    #[doc = "Bit 1 - Set WRITE Interrupt Flag"]
53    #[inline(always)]
54    pub fn write(&mut self) -> WRITE_W {
55        WRITE_W::new(self)
56    }
57    #[doc = "Bit 2 - Set CHOF Interrupt Flag"]
58    #[inline(always)]
59    pub fn chof(&mut self) -> CHOF_W {
60        CHOF_W::new(self)
61    }
62    #[doc = "Bit 3 - Set CMOF Interrupt Flag"]
63    #[inline(always)]
64    pub fn cmof(&mut self) -> CMOF_W {
65        CMOF_W::new(self)
66    }
67    #[doc = "Bit 4 - Set PWRUPF Interrupt Flag"]
68    #[inline(always)]
69    pub fn pwrupf(&mut self) -> PWRUPF_W {
70        PWRUPF_W::new(self)
71    }
72    #[doc = "Bit 5 - Set ICACHERR Interrupt Flag"]
73    #[inline(always)]
74    pub fn icacherr(&mut self) -> ICACHERR_W {
75        ICACHERR_W::new(self)
76    }
77    #[doc = "Bit 6 - Set WDATAOV Interrupt Flag"]
78    #[inline(always)]
79    pub fn wdataov(&mut self) -> WDATAOV_W {
80        WDATAOV_W::new(self)
81    }
82    #[doc = "Bit 8 - Set LVEWRITE Interrupt Flag"]
83    #[inline(always)]
84    pub fn lvewrite(&mut self) -> LVEWRITE_W {
85        LVEWRITE_W::new(self)
86    }
87    #[doc = "Bit 16 - Set RAMERR1B Interrupt Flag"]
88    #[inline(always)]
89    pub fn ramerr1b(&mut self) -> RAMERR1B_W {
90        RAMERR1B_W::new(self)
91    }
92    #[doc = "Bit 17 - Set RAMERR2B Interrupt Flag"]
93    #[inline(always)]
94    pub fn ramerr2b(&mut self) -> RAMERR2B_W {
95        RAMERR2B_W::new(self)
96    }
97    #[doc = "Bit 18 - Set RAM1ERR1B Interrupt Flag"]
98    #[inline(always)]
99    pub fn ram1err1b(&mut self) -> RAM1ERR1B_W {
100        RAM1ERR1B_W::new(self)
101    }
102    #[doc = "Bit 19 - Set RAM1ERR2B Interrupt Flag"]
103    #[inline(always)]
104    pub fn ram1err2b(&mut self) -> RAM1ERR2B_W {
105        RAM1ERR2B_W::new(self)
106    }
107    #[doc = "Writes raw bits to the register."]
108    #[inline(always)]
109    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
110        self.0.bits(bits);
111        self
112    }
113}
114#[doc = "Interrupt Flag Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifs](index.html) module"]
115pub struct IFS_SPEC;
116impl crate::RegisterSpec for IFS_SPEC {
117    type Ux = u32;
118}
119#[doc = "`write(|w| ..)` method takes [ifs::W](W) writer structure"]
120impl crate::Writable for IFS_SPEC {
121    type Writer = W;
122}
123#[doc = "`reset()` method sets IFS to value 0"]
124impl crate::Resettable for IFS_SPEC {
125    #[inline(always)]
126    fn reset_value() -> Self::Ux {
127        0
128    }
129}
efm32gg11b420_pac/msc/ifs.rs

efm32gg11b420_pac/msc/
ifs.rs
