efm32gg11b310_pac/emu/
r5vsync.rs

1#[doc = "Register `R5VSYNC` reader"]
2pub struct R(crate::R<R5VSYNC_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<R5VSYNC_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<R5VSYNC_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<R5VSYNC_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `OUTLEVELBUSY` reader - 5V Regulator Voltage Register Transfer Busy"]
17pub type OUTLEVELBUSY_R = crate::BitReader<bool>;
18impl R {
19    #[doc = "Bit 0 - 5V Regulator Voltage Register Transfer Busy"]
20    #[inline(always)]
21    pub fn outlevelbusy(&self) -> OUTLEVELBUSY_R {
22        OUTLEVELBUSY_R::new((self.bits & 1) != 0)
23    }
24}
25#[doc = "5V Read Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [r5vsync](index.html) module"]
26pub struct R5VSYNC_SPEC;
27impl crate::RegisterSpec for R5VSYNC_SPEC {
28    type Ux = u32;
29}
30#[doc = "`read()` method returns [r5vsync::R](R) reader structure"]
31impl crate::Readable for R5VSYNC_SPEC {
32    type Reader = R;
33}
34#[doc = "`reset()` method sets R5VSYNC to value 0"]
35impl crate::Resettable for R5VSYNC_SPEC {
36    #[inline(always)]
37    fn reset_value() -> Self::Ux {
38        0
39    }
40}
efm32gg11b310_pac/emu/r5vsync.rs

efm32gg11b310_pac/emu/
r5vsync.rs
