1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `SYNC` reader - USART Synchronous Mode"]
38pub type SYNC_R = crate::BitReader<bool>;
39#[doc = "Field `SYNC` writer - USART Synchronous Mode"]
40pub type SYNC_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 0>;
41#[doc = "Field `LOOPBK` reader - Loopback Enable"]
42pub type LOOPBK_R = crate::BitReader<bool>;
43#[doc = "Field `LOOPBK` writer - Loopback Enable"]
44pub type LOOPBK_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 1>;
45#[doc = "Field `CCEN` reader - Collision Check Enable"]
46pub type CCEN_R = crate::BitReader<bool>;
47#[doc = "Field `CCEN` writer - Collision Check Enable"]
48pub type CCEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 2>;
49#[doc = "Field `MPM` reader - Multi-Processor Mode"]
50pub type MPM_R = crate::BitReader<bool>;
51#[doc = "Field `MPM` writer - Multi-Processor Mode"]
52pub type MPM_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 3>;
53#[doc = "Field `MPAB` reader - Multi-Processor Address-Bit"]
54pub type MPAB_R = crate::BitReader<bool>;
55#[doc = "Field `MPAB` writer - Multi-Processor Address-Bit"]
56pub type MPAB_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 4>;
57#[doc = "Oversampling\n\nValue on reset: 0"]
58#[derive(Clone, Copy, Debug, PartialEq)]
59#[repr(u8)]
60pub enum OVS_A {
61 #[doc = "0: Regular UART mode with 16X oversampling in asynchronous mode"]
62 X16 = 0,
63 #[doc = "1: Double speed with 8X oversampling in asynchronous mode"]
64 X8 = 1,
65 #[doc = "2: 6X oversampling in asynchronous mode"]
66 X6 = 2,
67 #[doc = "3: Quadruple speed with 4X oversampling in asynchronous mode"]
68 X4 = 3,
69}
70impl From<OVS_A> for u8 {
71 #[inline(always)]
72 fn from(variant: OVS_A) -> Self {
73 variant as _
74 }
75}
76#[doc = "Field `OVS` reader - Oversampling"]
77pub type OVS_R = crate::FieldReader<u8, OVS_A>;
78impl OVS_R {
79 #[doc = "Get enumerated values variant"]
80 #[inline(always)]
81 pub fn variant(&self) -> OVS_A {
82 match self.bits {
83 0 => OVS_A::X16,
84 1 => OVS_A::X8,
85 2 => OVS_A::X6,
86 3 => OVS_A::X4,
87 _ => unreachable!(),
88 }
89 }
90 #[doc = "Checks if the value of the field is `X16`"]
91 #[inline(always)]
92 pub fn is_x16(&self) -> bool {
93 *self == OVS_A::X16
94 }
95 #[doc = "Checks if the value of the field is `X8`"]
96 #[inline(always)]
97 pub fn is_x8(&self) -> bool {
98 *self == OVS_A::X8
99 }
100 #[doc = "Checks if the value of the field is `X6`"]
101 #[inline(always)]
102 pub fn is_x6(&self) -> bool {
103 *self == OVS_A::X6
104 }
105 #[doc = "Checks if the value of the field is `X4`"]
106 #[inline(always)]
107 pub fn is_x4(&self) -> bool {
108 *self == OVS_A::X4
109 }
110}
111#[doc = "Field `OVS` writer - Oversampling"]
112pub type OVS_W<'a> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, OVS_A, 2, 5>;
113impl<'a> OVS_W<'a> {
114 #[doc = "Regular UART mode with 16X oversampling in asynchronous mode"]
115 #[inline(always)]
116 pub fn x16(self) -> &'a mut W {
117 self.variant(OVS_A::X16)
118 }
119 #[doc = "Double speed with 8X oversampling in asynchronous mode"]
120 #[inline(always)]
121 pub fn x8(self) -> &'a mut W {
122 self.variant(OVS_A::X8)
123 }
124 #[doc = "6X oversampling in asynchronous mode"]
125 #[inline(always)]
126 pub fn x6(self) -> &'a mut W {
127 self.variant(OVS_A::X6)
128 }
129 #[doc = "Quadruple speed with 4X oversampling in asynchronous mode"]
130 #[inline(always)]
131 pub fn x4(self) -> &'a mut W {
132 self.variant(OVS_A::X4)
133 }
134}
135#[doc = "Field `CLKPOL` reader - Clock Polarity"]
136pub type CLKPOL_R = crate::BitReader<bool>;
137#[doc = "Field `CLKPOL` writer - Clock Polarity"]
138pub type CLKPOL_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 8>;
139#[doc = "Field `CLKPHA` reader - Clock Edge for Setup/Sample"]
140pub type CLKPHA_R = crate::BitReader<bool>;
141#[doc = "Field `CLKPHA` writer - Clock Edge for Setup/Sample"]
142pub type CLKPHA_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 9>;
143#[doc = "Field `MSBF` reader - Most Significant Bit First"]
144pub type MSBF_R = crate::BitReader<bool>;
145#[doc = "Field `MSBF` writer - Most Significant Bit First"]
146pub type MSBF_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 10>;
147#[doc = "Field `CSMA` reader - Action on Slave-Select in Master Mode"]
148pub type CSMA_R = crate::BitReader<bool>;
149#[doc = "Field `CSMA` writer - Action on Slave-Select in Master Mode"]
150pub type CSMA_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 11>;
151#[doc = "Field `TXBIL` reader - TX Buffer Interrupt Level"]
152pub type TXBIL_R = crate::BitReader<bool>;
153#[doc = "Field `TXBIL` writer - TX Buffer Interrupt Level"]
154pub type TXBIL_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 12>;
155#[doc = "Field `RXINV` reader - Receiver Input Invert"]
156pub type RXINV_R = crate::BitReader<bool>;
157#[doc = "Field `RXINV` writer - Receiver Input Invert"]
158pub type RXINV_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 13>;
159#[doc = "Field `TXINV` reader - Transmitter Output Invert"]
160pub type TXINV_R = crate::BitReader<bool>;
161#[doc = "Field `TXINV` writer - Transmitter Output Invert"]
162pub type TXINV_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 14>;
163#[doc = "Field `CSINV` reader - Chip Select Invert"]
164pub type CSINV_R = crate::BitReader<bool>;
165#[doc = "Field `CSINV` writer - Chip Select Invert"]
166pub type CSINV_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 15>;
167#[doc = "Field `AUTOCS` reader - Automatic Chip Select"]
168pub type AUTOCS_R = crate::BitReader<bool>;
169#[doc = "Field `AUTOCS` writer - Automatic Chip Select"]
170pub type AUTOCS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 16>;
171#[doc = "Field `AUTOTRI` reader - Automatic TX Tristate"]
172pub type AUTOTRI_R = crate::BitReader<bool>;
173#[doc = "Field `AUTOTRI` writer - Automatic TX Tristate"]
174pub type AUTOTRI_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 17>;
175#[doc = "Field `SCMODE` reader - SmartCard Mode"]
176pub type SCMODE_R = crate::BitReader<bool>;
177#[doc = "Field `SCMODE` writer - SmartCard Mode"]
178pub type SCMODE_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 18>;
179#[doc = "Field `SCRETRANS` reader - SmartCard Retransmit"]
180pub type SCRETRANS_R = crate::BitReader<bool>;
181#[doc = "Field `SCRETRANS` writer - SmartCard Retransmit"]
182pub type SCRETRANS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 19>;
183#[doc = "Field `SKIPPERRF` reader - Skip Parity Error Frames"]
184pub type SKIPPERRF_R = crate::BitReader<bool>;
185#[doc = "Field `SKIPPERRF` writer - Skip Parity Error Frames"]
186pub type SKIPPERRF_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 20>;
187#[doc = "Field `BIT8DV` reader - Bit 8 Default Value"]
188pub type BIT8DV_R = crate::BitReader<bool>;
189#[doc = "Field `BIT8DV` writer - Bit 8 Default Value"]
190pub type BIT8DV_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 21>;
191#[doc = "Field `ERRSDMA` reader - Halt DMA on Error"]
192pub type ERRSDMA_R = crate::BitReader<bool>;
193#[doc = "Field `ERRSDMA` writer - Halt DMA on Error"]
194pub type ERRSDMA_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 22>;
195#[doc = "Field `ERRSRX` reader - Disable RX on Error"]
196pub type ERRSRX_R = crate::BitReader<bool>;
197#[doc = "Field `ERRSRX` writer - Disable RX on Error"]
198pub type ERRSRX_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 23>;
199#[doc = "Field `ERRSTX` reader - Disable TX on Error"]
200pub type ERRSTX_R = crate::BitReader<bool>;
201#[doc = "Field `ERRSTX` writer - Disable TX on Error"]
202pub type ERRSTX_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 24>;
203#[doc = "Field `SSSEARLY` reader - Synchronous Slave Setup Early"]
204pub type SSSEARLY_R = crate::BitReader<bool>;
205#[doc = "Field `SSSEARLY` writer - Synchronous Slave Setup Early"]
206pub type SSSEARLY_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 25>;
207#[doc = "Field `BYTESWAP` reader - Byteswap in Double Accesses"]
208pub type BYTESWAP_R = crate::BitReader<bool>;
209#[doc = "Field `BYTESWAP` writer - Byteswap in Double Accesses"]
210pub type BYTESWAP_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 28>;
211#[doc = "Field `AUTOTX` reader - Always Transmit When RX Not Full"]
212pub type AUTOTX_R = crate::BitReader<bool>;
213#[doc = "Field `AUTOTX` writer - Always Transmit When RX Not Full"]
214pub type AUTOTX_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 29>;
215#[doc = "Field `MVDIS` reader - Majority Vote Disable"]
216pub type MVDIS_R = crate::BitReader<bool>;
217#[doc = "Field `MVDIS` writer - Majority Vote Disable"]
218pub type MVDIS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 30>;
219#[doc = "Field `SMSDELAY` reader - Synchronous Master Sample Delay"]
220pub type SMSDELAY_R = crate::BitReader<bool>;
221#[doc = "Field `SMSDELAY` writer - Synchronous Master Sample Delay"]
222pub type SMSDELAY_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 31>;
223impl R {
224 #[doc = "Bit 0 - USART Synchronous Mode"]
225 #[inline(always)]
226 pub fn sync(&self) -> SYNC_R {
227 SYNC_R::new((self.bits & 1) != 0)
228 }
229 #[doc = "Bit 1 - Loopback Enable"]
230 #[inline(always)]
231 pub fn loopbk(&self) -> LOOPBK_R {
232 LOOPBK_R::new(((self.bits >> 1) & 1) != 0)
233 }
234 #[doc = "Bit 2 - Collision Check Enable"]
235 #[inline(always)]
236 pub fn ccen(&self) -> CCEN_R {
237 CCEN_R::new(((self.bits >> 2) & 1) != 0)
238 }
239 #[doc = "Bit 3 - Multi-Processor Mode"]
240 #[inline(always)]
241 pub fn mpm(&self) -> MPM_R {
242 MPM_R::new(((self.bits >> 3) & 1) != 0)
243 }
244 #[doc = "Bit 4 - Multi-Processor Address-Bit"]
245 #[inline(always)]
246 pub fn mpab(&self) -> MPAB_R {
247 MPAB_R::new(((self.bits >> 4) & 1) != 0)
248 }
249 #[doc = "Bits 5:6 - Oversampling"]
250 #[inline(always)]
251 pub fn ovs(&self) -> OVS_R {
252 OVS_R::new(((self.bits >> 5) & 3) as u8)
253 }
254 #[doc = "Bit 8 - Clock Polarity"]
255 #[inline(always)]
256 pub fn clkpol(&self) -> CLKPOL_R {
257 CLKPOL_R::new(((self.bits >> 8) & 1) != 0)
258 }
259 #[doc = "Bit 9 - Clock Edge for Setup/Sample"]
260 #[inline(always)]
261 pub fn clkpha(&self) -> CLKPHA_R {
262 CLKPHA_R::new(((self.bits >> 9) & 1) != 0)
263 }
264 #[doc = "Bit 10 - Most Significant Bit First"]
265 #[inline(always)]
266 pub fn msbf(&self) -> MSBF_R {
267 MSBF_R::new(((self.bits >> 10) & 1) != 0)
268 }
269 #[doc = "Bit 11 - Action on Slave-Select in Master Mode"]
270 #[inline(always)]
271 pub fn csma(&self) -> CSMA_R {
272 CSMA_R::new(((self.bits >> 11) & 1) != 0)
273 }
274 #[doc = "Bit 12 - TX Buffer Interrupt Level"]
275 #[inline(always)]
276 pub fn txbil(&self) -> TXBIL_R {
277 TXBIL_R::new(((self.bits >> 12) & 1) != 0)
278 }
279 #[doc = "Bit 13 - Receiver Input Invert"]
280 #[inline(always)]
281 pub fn rxinv(&self) -> RXINV_R {
282 RXINV_R::new(((self.bits >> 13) & 1) != 0)
283 }
284 #[doc = "Bit 14 - Transmitter Output Invert"]
285 #[inline(always)]
286 pub fn txinv(&self) -> TXINV_R {
287 TXINV_R::new(((self.bits >> 14) & 1) != 0)
288 }
289 #[doc = "Bit 15 - Chip Select Invert"]
290 #[inline(always)]
291 pub fn csinv(&self) -> CSINV_R {
292 CSINV_R::new(((self.bits >> 15) & 1) != 0)
293 }
294 #[doc = "Bit 16 - Automatic Chip Select"]
295 #[inline(always)]
296 pub fn autocs(&self) -> AUTOCS_R {
297 AUTOCS_R::new(((self.bits >> 16) & 1) != 0)
298 }
299 #[doc = "Bit 17 - Automatic TX Tristate"]
300 #[inline(always)]
301 pub fn autotri(&self) -> AUTOTRI_R {
302 AUTOTRI_R::new(((self.bits >> 17) & 1) != 0)
303 }
304 #[doc = "Bit 18 - SmartCard Mode"]
305 #[inline(always)]
306 pub fn scmode(&self) -> SCMODE_R {
307 SCMODE_R::new(((self.bits >> 18) & 1) != 0)
308 }
309 #[doc = "Bit 19 - SmartCard Retransmit"]
310 #[inline(always)]
311 pub fn scretrans(&self) -> SCRETRANS_R {
312 SCRETRANS_R::new(((self.bits >> 19) & 1) != 0)
313 }
314 #[doc = "Bit 20 - Skip Parity Error Frames"]
315 #[inline(always)]
316 pub fn skipperrf(&self) -> SKIPPERRF_R {
317 SKIPPERRF_R::new(((self.bits >> 20) & 1) != 0)
318 }
319 #[doc = "Bit 21 - Bit 8 Default Value"]
320 #[inline(always)]
321 pub fn bit8dv(&self) -> BIT8DV_R {
322 BIT8DV_R::new(((self.bits >> 21) & 1) != 0)
323 }
324 #[doc = "Bit 22 - Halt DMA on Error"]
325 #[inline(always)]
326 pub fn errsdma(&self) -> ERRSDMA_R {
327 ERRSDMA_R::new(((self.bits >> 22) & 1) != 0)
328 }
329 #[doc = "Bit 23 - Disable RX on Error"]
330 #[inline(always)]
331 pub fn errsrx(&self) -> ERRSRX_R {
332 ERRSRX_R::new(((self.bits >> 23) & 1) != 0)
333 }
334 #[doc = "Bit 24 - Disable TX on Error"]
335 #[inline(always)]
336 pub fn errstx(&self) -> ERRSTX_R {
337 ERRSTX_R::new(((self.bits >> 24) & 1) != 0)
338 }
339 #[doc = "Bit 25 - Synchronous Slave Setup Early"]
340 #[inline(always)]
341 pub fn sssearly(&self) -> SSSEARLY_R {
342 SSSEARLY_R::new(((self.bits >> 25) & 1) != 0)
343 }
344 #[doc = "Bit 28 - Byteswap in Double Accesses"]
345 #[inline(always)]
346 pub fn byteswap(&self) -> BYTESWAP_R {
347 BYTESWAP_R::new(((self.bits >> 28) & 1) != 0)
348 }
349 #[doc = "Bit 29 - Always Transmit When RX Not Full"]
350 #[inline(always)]
351 pub fn autotx(&self) -> AUTOTX_R {
352 AUTOTX_R::new(((self.bits >> 29) & 1) != 0)
353 }
354 #[doc = "Bit 30 - Majority Vote Disable"]
355 #[inline(always)]
356 pub fn mvdis(&self) -> MVDIS_R {
357 MVDIS_R::new(((self.bits >> 30) & 1) != 0)
358 }
359 #[doc = "Bit 31 - Synchronous Master Sample Delay"]
360 #[inline(always)]
361 pub fn smsdelay(&self) -> SMSDELAY_R {
362 SMSDELAY_R::new(((self.bits >> 31) & 1) != 0)
363 }
364}
365impl W {
366 #[doc = "Bit 0 - USART Synchronous Mode"]
367 #[inline(always)]
368 pub fn sync(&mut self) -> SYNC_W {
369 SYNC_W::new(self)
370 }
371 #[doc = "Bit 1 - Loopback Enable"]
372 #[inline(always)]
373 pub fn loopbk(&mut self) -> LOOPBK_W {
374 LOOPBK_W::new(self)
375 }
376 #[doc = "Bit 2 - Collision Check Enable"]
377 #[inline(always)]
378 pub fn ccen(&mut self) -> CCEN_W {
379 CCEN_W::new(self)
380 }
381 #[doc = "Bit 3 - Multi-Processor Mode"]
382 #[inline(always)]
383 pub fn mpm(&mut self) -> MPM_W {
384 MPM_W::new(self)
385 }
386 #[doc = "Bit 4 - Multi-Processor Address-Bit"]
387 #[inline(always)]
388 pub fn mpab(&mut self) -> MPAB_W {
389 MPAB_W::new(self)
390 }
391 #[doc = "Bits 5:6 - Oversampling"]
392 #[inline(always)]
393 pub fn ovs(&mut self) -> OVS_W {
394 OVS_W::new(self)
395 }
396 #[doc = "Bit 8 - Clock Polarity"]
397 #[inline(always)]
398 pub fn clkpol(&mut self) -> CLKPOL_W {
399 CLKPOL_W::new(self)
400 }
401 #[doc = "Bit 9 - Clock Edge for Setup/Sample"]
402 #[inline(always)]
403 pub fn clkpha(&mut self) -> CLKPHA_W {
404 CLKPHA_W::new(self)
405 }
406 #[doc = "Bit 10 - Most Significant Bit First"]
407 #[inline(always)]
408 pub fn msbf(&mut self) -> MSBF_W {
409 MSBF_W::new(self)
410 }
411 #[doc = "Bit 11 - Action on Slave-Select in Master Mode"]
412 #[inline(always)]
413 pub fn csma(&mut self) -> CSMA_W {
414 CSMA_W::new(self)
415 }
416 #[doc = "Bit 12 - TX Buffer Interrupt Level"]
417 #[inline(always)]
418 pub fn txbil(&mut self) -> TXBIL_W {
419 TXBIL_W::new(self)
420 }
421 #[doc = "Bit 13 - Receiver Input Invert"]
422 #[inline(always)]
423 pub fn rxinv(&mut self) -> RXINV_W {
424 RXINV_W::new(self)
425 }
426 #[doc = "Bit 14 - Transmitter Output Invert"]
427 #[inline(always)]
428 pub fn txinv(&mut self) -> TXINV_W {
429 TXINV_W::new(self)
430 }
431 #[doc = "Bit 15 - Chip Select Invert"]
432 #[inline(always)]
433 pub fn csinv(&mut self) -> CSINV_W {
434 CSINV_W::new(self)
435 }
436 #[doc = "Bit 16 - Automatic Chip Select"]
437 #[inline(always)]
438 pub fn autocs(&mut self) -> AUTOCS_W {
439 AUTOCS_W::new(self)
440 }
441 #[doc = "Bit 17 - Automatic TX Tristate"]
442 #[inline(always)]
443 pub fn autotri(&mut self) -> AUTOTRI_W {
444 AUTOTRI_W::new(self)
445 }
446 #[doc = "Bit 18 - SmartCard Mode"]
447 #[inline(always)]
448 pub fn scmode(&mut self) -> SCMODE_W {
449 SCMODE_W::new(self)
450 }
451 #[doc = "Bit 19 - SmartCard Retransmit"]
452 #[inline(always)]
453 pub fn scretrans(&mut self) -> SCRETRANS_W {
454 SCRETRANS_W::new(self)
455 }
456 #[doc = "Bit 20 - Skip Parity Error Frames"]
457 #[inline(always)]
458 pub fn skipperrf(&mut self) -> SKIPPERRF_W {
459 SKIPPERRF_W::new(self)
460 }
461 #[doc = "Bit 21 - Bit 8 Default Value"]
462 #[inline(always)]
463 pub fn bit8dv(&mut self) -> BIT8DV_W {
464 BIT8DV_W::new(self)
465 }
466 #[doc = "Bit 22 - Halt DMA on Error"]
467 #[inline(always)]
468 pub fn errsdma(&mut self) -> ERRSDMA_W {
469 ERRSDMA_W::new(self)
470 }
471 #[doc = "Bit 23 - Disable RX on Error"]
472 #[inline(always)]
473 pub fn errsrx(&mut self) -> ERRSRX_W {
474 ERRSRX_W::new(self)
475 }
476 #[doc = "Bit 24 - Disable TX on Error"]
477 #[inline(always)]
478 pub fn errstx(&mut self) -> ERRSTX_W {
479 ERRSTX_W::new(self)
480 }
481 #[doc = "Bit 25 - Synchronous Slave Setup Early"]
482 #[inline(always)]
483 pub fn sssearly(&mut self) -> SSSEARLY_W {
484 SSSEARLY_W::new(self)
485 }
486 #[doc = "Bit 28 - Byteswap in Double Accesses"]
487 #[inline(always)]
488 pub fn byteswap(&mut self) -> BYTESWAP_W {
489 BYTESWAP_W::new(self)
490 }
491 #[doc = "Bit 29 - Always Transmit When RX Not Full"]
492 #[inline(always)]
493 pub fn autotx(&mut self) -> AUTOTX_W {
494 AUTOTX_W::new(self)
495 }
496 #[doc = "Bit 30 - Majority Vote Disable"]
497 #[inline(always)]
498 pub fn mvdis(&mut self) -> MVDIS_W {
499 MVDIS_W::new(self)
500 }
501 #[doc = "Bit 31 - Synchronous Master Sample Delay"]
502 #[inline(always)]
503 pub fn smsdelay(&mut self) -> SMSDELAY_W {
504 SMSDELAY_W::new(self)
505 }
506 #[doc = "Writes raw bits to the register."]
507 #[inline(always)]
508 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
509 self.0.bits(bits);
510 self
511 }
512}
513#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
514pub struct CTRL_SPEC;
515impl crate::RegisterSpec for CTRL_SPEC {
516 type Ux = u32;
517}
518#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
519impl crate::Readable for CTRL_SPEC {
520 type Reader = R;
521}
522#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
523impl crate::Writable for CTRL_SPEC {
524 type Writer = W;
525}
526#[doc = "`reset()` method sets CTRL to value 0"]
527impl crate::Resettable for CTRL_SPEC {
528 #[inline(always)]
529 fn reset_value() -> Self::Ux {
530 0
531 }
532}