efm32gg11b310_pac/prs/
ch17_ctrl.rs

1#[doc = "Register `CH17_CTRL` reader"]
2pub struct R(crate::R<CH17_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH17_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH17_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH17_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH17_CTRL` writer"]
17pub struct W(crate::W<CH17_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH17_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH17_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH17_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH17_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Peripheral Reflex System"]
48    PRSL = 1,
49    #[doc = "2: Peripheral Reflex System"]
50    PRS = 2,
51    #[doc = "3: Peripheral Reflex System"]
52    PRSH = 3,
53    #[doc = "4: Analog Comparator 0"]
54    ACMP0 = 4,
55    #[doc = "5: Analog Comparator 1"]
56    ACMP1 = 5,
57    #[doc = "6: Analog to Digital Converter 0"]
58    ADC0 = 6,
59    #[doc = "7: Real-Time Counter"]
60    RTC = 7,
61    #[doc = "8: Real-Time Counter and Calendar"]
62    RTCC = 8,
63    #[doc = "9: General purpose Input/Output"]
64    GPIOL = 9,
65    #[doc = "10: General purpose Input/Output"]
66    GPIOH = 10,
67    #[doc = "11: Low Energy Timer 0"]
68    LETIMER0 = 11,
69    #[doc = "12: Low Energy Timer 1"]
70    LETIMER1 = 12,
71    #[doc = "13: Pulse Counter 0"]
72    PCNT0 = 13,
73    #[doc = "14: Pulse Counter 1"]
74    PCNT1 = 14,
75    #[doc = "15: Pulse Counter 2"]
76    PCNT2 = 15,
77    #[doc = "16: CRYOTIMER"]
78    CRYOTIMER = 16,
79    #[doc = "17: Clock Management Unit"]
80    CMU = 17,
81    #[doc = "23: Digital to Analog Converter 0"]
82    VDAC0 = 23,
83    #[doc = "24: Low Energy Sensor Interface"]
84    LESENSEL = 24,
85    #[doc = "25: Low Energy Sensor Interface"]
86    LESENSEH = 25,
87    #[doc = "26: Low Energy Sensor Interface"]
88    LESENSED = 26,
89    #[doc = "27: Low Energy Sensor Interface"]
90    LESENSE = 27,
91    #[doc = "28: Analog Comparator 1"]
92    ACMP2 = 28,
93    #[doc = "29: Analog Comparator 3"]
94    ACMP3 = 29,
95    #[doc = "30: Analog to Digital Converter 0"]
96    ADC1 = 30,
97    #[doc = "48: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
98    USART0 = 48,
99    #[doc = "49: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
100    USART1 = 49,
101    #[doc = "50: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
102    USART2 = 50,
103    #[doc = "51: Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
104    USART3 = 51,
105    #[doc = "52: Universal Synchronous/Asynchronous Receiver/Transmitter 4"]
106    USART4 = 52,
107    #[doc = "53: Universal Synchronous/Asynchronous Receiver/Transmitter 5"]
108    USART5 = 53,
109    #[doc = "54: Universal Asynchronous Receiver/Transmitter 0"]
110    UART0 = 54,
111    #[doc = "55: Universal Asynchronous Receiver/Transmitter 1"]
112    UART1 = 55,
113    #[doc = "60: Timer 0"]
114    TIMER0 = 60,
115    #[doc = "61: Timer 1"]
116    TIMER1 = 61,
117    #[doc = "62: Timer 2"]
118    TIMER2 = 62,
119    #[doc = "67: `1000011`"]
120    CM4 = 67,
121    #[doc = "80: Timer 3"]
122    TIMER3 = 80,
123    #[doc = "82: Wide Timer 0"]
124    WTIMER0 = 82,
125    #[doc = "83: Wide Timer 0"]
126    WTIMER1 = 83,
127    #[doc = "84: Wide Timer 2"]
128    WTIMER2 = 84,
129    #[doc = "85: Wide Timer 3"]
130    WTIMER3 = 85,
131    #[doc = "98: Timer 4"]
132    TIMER4 = 98,
133    #[doc = "99: Timer 5"]
134    TIMER5 = 99,
135    #[doc = "100: Timer 6"]
136    TIMER6 = 100,
137}
138impl From<SOURCESEL_A> for u8 {
139    #[inline(always)]
140    fn from(variant: SOURCESEL_A) -> Self {
141        variant as _
142    }
143}
144#[doc = "Field `SOURCESEL` reader - Source Select"]
145pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
146impl SOURCESEL_R {
147    #[doc = "Get enumerated values variant"]
148    #[inline(always)]
149    pub fn variant(&self) -> Option<SOURCESEL_A> {
150        match self.bits {
151            0 => Some(SOURCESEL_A::NONE),
152            1 => Some(SOURCESEL_A::PRSL),
153            2 => Some(SOURCESEL_A::PRS),
154            3 => Some(SOURCESEL_A::PRSH),
155            4 => Some(SOURCESEL_A::ACMP0),
156            5 => Some(SOURCESEL_A::ACMP1),
157            6 => Some(SOURCESEL_A::ADC0),
158            7 => Some(SOURCESEL_A::RTC),
159            8 => Some(SOURCESEL_A::RTCC),
160            9 => Some(SOURCESEL_A::GPIOL),
161            10 => Some(SOURCESEL_A::GPIOH),
162            11 => Some(SOURCESEL_A::LETIMER0),
163            12 => Some(SOURCESEL_A::LETIMER1),
164            13 => Some(SOURCESEL_A::PCNT0),
165            14 => Some(SOURCESEL_A::PCNT1),
166            15 => Some(SOURCESEL_A::PCNT2),
167            16 => Some(SOURCESEL_A::CRYOTIMER),
168            17 => Some(SOURCESEL_A::CMU),
169            23 => Some(SOURCESEL_A::VDAC0),
170            24 => Some(SOURCESEL_A::LESENSEL),
171            25 => Some(SOURCESEL_A::LESENSEH),
172            26 => Some(SOURCESEL_A::LESENSED),
173            27 => Some(SOURCESEL_A::LESENSE),
174            28 => Some(SOURCESEL_A::ACMP2),
175            29 => Some(SOURCESEL_A::ACMP3),
176            30 => Some(SOURCESEL_A::ADC1),
177            48 => Some(SOURCESEL_A::USART0),
178            49 => Some(SOURCESEL_A::USART1),
179            50 => Some(SOURCESEL_A::USART2),
180            51 => Some(SOURCESEL_A::USART3),
181            52 => Some(SOURCESEL_A::USART4),
182            53 => Some(SOURCESEL_A::USART5),
183            54 => Some(SOURCESEL_A::UART0),
184            55 => Some(SOURCESEL_A::UART1),
185            60 => Some(SOURCESEL_A::TIMER0),
186            61 => Some(SOURCESEL_A::TIMER1),
187            62 => Some(SOURCESEL_A::TIMER2),
188            67 => Some(SOURCESEL_A::CM4),
189            80 => Some(SOURCESEL_A::TIMER3),
190            82 => Some(SOURCESEL_A::WTIMER0),
191            83 => Some(SOURCESEL_A::WTIMER1),
192            84 => Some(SOURCESEL_A::WTIMER2),
193            85 => Some(SOURCESEL_A::WTIMER3),
194            98 => Some(SOURCESEL_A::TIMER4),
195            99 => Some(SOURCESEL_A::TIMER5),
196            100 => Some(SOURCESEL_A::TIMER6),
197            _ => None,
198        }
199    }
200    #[doc = "Checks if the value of the field is `NONE`"]
201    #[inline(always)]
202    pub fn is_none(&self) -> bool {
203        *self == SOURCESEL_A::NONE
204    }
205    #[doc = "Checks if the value of the field is `PRSL`"]
206    #[inline(always)]
207    pub fn is_prsl(&self) -> bool {
208        *self == SOURCESEL_A::PRSL
209    }
210    #[doc = "Checks if the value of the field is `PRS`"]
211    #[inline(always)]
212    pub fn is_prs(&self) -> bool {
213        *self == SOURCESEL_A::PRS
214    }
215    #[doc = "Checks if the value of the field is `PRSH`"]
216    #[inline(always)]
217    pub fn is_prsh(&self) -> bool {
218        *self == SOURCESEL_A::PRSH
219    }
220    #[doc = "Checks if the value of the field is `ACMP0`"]
221    #[inline(always)]
222    pub fn is_acmp0(&self) -> bool {
223        *self == SOURCESEL_A::ACMP0
224    }
225    #[doc = "Checks if the value of the field is `ACMP1`"]
226    #[inline(always)]
227    pub fn is_acmp1(&self) -> bool {
228        *self == SOURCESEL_A::ACMP1
229    }
230    #[doc = "Checks if the value of the field is `ADC0`"]
231    #[inline(always)]
232    pub fn is_adc0(&self) -> bool {
233        *self == SOURCESEL_A::ADC0
234    }
235    #[doc = "Checks if the value of the field is `RTC`"]
236    #[inline(always)]
237    pub fn is_rtc(&self) -> bool {
238        *self == SOURCESEL_A::RTC
239    }
240    #[doc = "Checks if the value of the field is `RTCC`"]
241    #[inline(always)]
242    pub fn is_rtcc(&self) -> bool {
243        *self == SOURCESEL_A::RTCC
244    }
245    #[doc = "Checks if the value of the field is `GPIOL`"]
246    #[inline(always)]
247    pub fn is_gpiol(&self) -> bool {
248        *self == SOURCESEL_A::GPIOL
249    }
250    #[doc = "Checks if the value of the field is `GPIOH`"]
251    #[inline(always)]
252    pub fn is_gpioh(&self) -> bool {
253        *self == SOURCESEL_A::GPIOH
254    }
255    #[doc = "Checks if the value of the field is `LETIMER0`"]
256    #[inline(always)]
257    pub fn is_letimer0(&self) -> bool {
258        *self == SOURCESEL_A::LETIMER0
259    }
260    #[doc = "Checks if the value of the field is `LETIMER1`"]
261    #[inline(always)]
262    pub fn is_letimer1(&self) -> bool {
263        *self == SOURCESEL_A::LETIMER1
264    }
265    #[doc = "Checks if the value of the field is `PCNT0`"]
266    #[inline(always)]
267    pub fn is_pcnt0(&self) -> bool {
268        *self == SOURCESEL_A::PCNT0
269    }
270    #[doc = "Checks if the value of the field is `PCNT1`"]
271    #[inline(always)]
272    pub fn is_pcnt1(&self) -> bool {
273        *self == SOURCESEL_A::PCNT1
274    }
275    #[doc = "Checks if the value of the field is `PCNT2`"]
276    #[inline(always)]
277    pub fn is_pcnt2(&self) -> bool {
278        *self == SOURCESEL_A::PCNT2
279    }
280    #[doc = "Checks if the value of the field is `CRYOTIMER`"]
281    #[inline(always)]
282    pub fn is_cryotimer(&self) -> bool {
283        *self == SOURCESEL_A::CRYOTIMER
284    }
285    #[doc = "Checks if the value of the field is `CMU`"]
286    #[inline(always)]
287    pub fn is_cmu(&self) -> bool {
288        *self == SOURCESEL_A::CMU
289    }
290    #[doc = "Checks if the value of the field is `VDAC0`"]
291    #[inline(always)]
292    pub fn is_vdac0(&self) -> bool {
293        *self == SOURCESEL_A::VDAC0
294    }
295    #[doc = "Checks if the value of the field is `LESENSEL`"]
296    #[inline(always)]
297    pub fn is_lesensel(&self) -> bool {
298        *self == SOURCESEL_A::LESENSEL
299    }
300    #[doc = "Checks if the value of the field is `LESENSEH`"]
301    #[inline(always)]
302    pub fn is_lesenseh(&self) -> bool {
303        *self == SOURCESEL_A::LESENSEH
304    }
305    #[doc = "Checks if the value of the field is `LESENSED`"]
306    #[inline(always)]
307    pub fn is_lesensed(&self) -> bool {
308        *self == SOURCESEL_A::LESENSED
309    }
310    #[doc = "Checks if the value of the field is `LESENSE`"]
311    #[inline(always)]
312    pub fn is_lesense(&self) -> bool {
313        *self == SOURCESEL_A::LESENSE
314    }
315    #[doc = "Checks if the value of the field is `ACMP2`"]
316    #[inline(always)]
317    pub fn is_acmp2(&self) -> bool {
318        *self == SOURCESEL_A::ACMP2
319    }
320    #[doc = "Checks if the value of the field is `ACMP3`"]
321    #[inline(always)]
322    pub fn is_acmp3(&self) -> bool {
323        *self == SOURCESEL_A::ACMP3
324    }
325    #[doc = "Checks if the value of the field is `ADC1`"]
326    #[inline(always)]
327    pub fn is_adc1(&self) -> bool {
328        *self == SOURCESEL_A::ADC1
329    }
330    #[doc = "Checks if the value of the field is `USART0`"]
331    #[inline(always)]
332    pub fn is_usart0(&self) -> bool {
333        *self == SOURCESEL_A::USART0
334    }
335    #[doc = "Checks if the value of the field is `USART1`"]
336    #[inline(always)]
337    pub fn is_usart1(&self) -> bool {
338        *self == SOURCESEL_A::USART1
339    }
340    #[doc = "Checks if the value of the field is `USART2`"]
341    #[inline(always)]
342    pub fn is_usart2(&self) -> bool {
343        *self == SOURCESEL_A::USART2
344    }
345    #[doc = "Checks if the value of the field is `USART3`"]
346    #[inline(always)]
347    pub fn is_usart3(&self) -> bool {
348        *self == SOURCESEL_A::USART3
349    }
350    #[doc = "Checks if the value of the field is `USART4`"]
351    #[inline(always)]
352    pub fn is_usart4(&self) -> bool {
353        *self == SOURCESEL_A::USART4
354    }
355    #[doc = "Checks if the value of the field is `USART5`"]
356    #[inline(always)]
357    pub fn is_usart5(&self) -> bool {
358        *self == SOURCESEL_A::USART5
359    }
360    #[doc = "Checks if the value of the field is `UART0`"]
361    #[inline(always)]
362    pub fn is_uart0(&self) -> bool {
363        *self == SOURCESEL_A::UART0
364    }
365    #[doc = "Checks if the value of the field is `UART1`"]
366    #[inline(always)]
367    pub fn is_uart1(&self) -> bool {
368        *self == SOURCESEL_A::UART1
369    }
370    #[doc = "Checks if the value of the field is `TIMER0`"]
371    #[inline(always)]
372    pub fn is_timer0(&self) -> bool {
373        *self == SOURCESEL_A::TIMER0
374    }
375    #[doc = "Checks if the value of the field is `TIMER1`"]
376    #[inline(always)]
377    pub fn is_timer1(&self) -> bool {
378        *self == SOURCESEL_A::TIMER1
379    }
380    #[doc = "Checks if the value of the field is `TIMER2`"]
381    #[inline(always)]
382    pub fn is_timer2(&self) -> bool {
383        *self == SOURCESEL_A::TIMER2
384    }
385    #[doc = "Checks if the value of the field is `CM4`"]
386    #[inline(always)]
387    pub fn is_cm4(&self) -> bool {
388        *self == SOURCESEL_A::CM4
389    }
390    #[doc = "Checks if the value of the field is `TIMER3`"]
391    #[inline(always)]
392    pub fn is_timer3(&self) -> bool {
393        *self == SOURCESEL_A::TIMER3
394    }
395    #[doc = "Checks if the value of the field is `WTIMER0`"]
396    #[inline(always)]
397    pub fn is_wtimer0(&self) -> bool {
398        *self == SOURCESEL_A::WTIMER0
399    }
400    #[doc = "Checks if the value of the field is `WTIMER1`"]
401    #[inline(always)]
402    pub fn is_wtimer1(&self) -> bool {
403        *self == SOURCESEL_A::WTIMER1
404    }
405    #[doc = "Checks if the value of the field is `WTIMER2`"]
406    #[inline(always)]
407    pub fn is_wtimer2(&self) -> bool {
408        *self == SOURCESEL_A::WTIMER2
409    }
410    #[doc = "Checks if the value of the field is `WTIMER3`"]
411    #[inline(always)]
412    pub fn is_wtimer3(&self) -> bool {
413        *self == SOURCESEL_A::WTIMER3
414    }
415    #[doc = "Checks if the value of the field is `TIMER4`"]
416    #[inline(always)]
417    pub fn is_timer4(&self) -> bool {
418        *self == SOURCESEL_A::TIMER4
419    }
420    #[doc = "Checks if the value of the field is `TIMER5`"]
421    #[inline(always)]
422    pub fn is_timer5(&self) -> bool {
423        *self == SOURCESEL_A::TIMER5
424    }
425    #[doc = "Checks if the value of the field is `TIMER6`"]
426    #[inline(always)]
427    pub fn is_timer6(&self) -> bool {
428        *self == SOURCESEL_A::TIMER6
429    }
430}
431#[doc = "Field `SOURCESEL` writer - Source Select"]
432pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH17_CTRL_SPEC, u8, SOURCESEL_A, 7, 8>;
433impl<'a> SOURCESEL_W<'a> {
434    #[doc = "No source selected"]
435    #[inline(always)]
436    pub fn none(self) -> &'a mut W {
437        self.variant(SOURCESEL_A::NONE)
438    }
439    #[doc = "Peripheral Reflex System"]
440    #[inline(always)]
441    pub fn prsl(self) -> &'a mut W {
442        self.variant(SOURCESEL_A::PRSL)
443    }
444    #[doc = "Peripheral Reflex System"]
445    #[inline(always)]
446    pub fn prs(self) -> &'a mut W {
447        self.variant(SOURCESEL_A::PRS)
448    }
449    #[doc = "Peripheral Reflex System"]
450    #[inline(always)]
451    pub fn prsh(self) -> &'a mut W {
452        self.variant(SOURCESEL_A::PRSH)
453    }
454    #[doc = "Analog Comparator 0"]
455    #[inline(always)]
456    pub fn acmp0(self) -> &'a mut W {
457        self.variant(SOURCESEL_A::ACMP0)
458    }
459    #[doc = "Analog Comparator 1"]
460    #[inline(always)]
461    pub fn acmp1(self) -> &'a mut W {
462        self.variant(SOURCESEL_A::ACMP1)
463    }
464    #[doc = "Analog to Digital Converter 0"]
465    #[inline(always)]
466    pub fn adc0(self) -> &'a mut W {
467        self.variant(SOURCESEL_A::ADC0)
468    }
469    #[doc = "Real-Time Counter"]
470    #[inline(always)]
471    pub fn rtc(self) -> &'a mut W {
472        self.variant(SOURCESEL_A::RTC)
473    }
474    #[doc = "Real-Time Counter and Calendar"]
475    #[inline(always)]
476    pub fn rtcc(self) -> &'a mut W {
477        self.variant(SOURCESEL_A::RTCC)
478    }
479    #[doc = "General purpose Input/Output"]
480    #[inline(always)]
481    pub fn gpiol(self) -> &'a mut W {
482        self.variant(SOURCESEL_A::GPIOL)
483    }
484    #[doc = "General purpose Input/Output"]
485    #[inline(always)]
486    pub fn gpioh(self) -> &'a mut W {
487        self.variant(SOURCESEL_A::GPIOH)
488    }
489    #[doc = "Low Energy Timer 0"]
490    #[inline(always)]
491    pub fn letimer0(self) -> &'a mut W {
492        self.variant(SOURCESEL_A::LETIMER0)
493    }
494    #[doc = "Low Energy Timer 1"]
495    #[inline(always)]
496    pub fn letimer1(self) -> &'a mut W {
497        self.variant(SOURCESEL_A::LETIMER1)
498    }
499    #[doc = "Pulse Counter 0"]
500    #[inline(always)]
501    pub fn pcnt0(self) -> &'a mut W {
502        self.variant(SOURCESEL_A::PCNT0)
503    }
504    #[doc = "Pulse Counter 1"]
505    #[inline(always)]
506    pub fn pcnt1(self) -> &'a mut W {
507        self.variant(SOURCESEL_A::PCNT1)
508    }
509    #[doc = "Pulse Counter 2"]
510    #[inline(always)]
511    pub fn pcnt2(self) -> &'a mut W {
512        self.variant(SOURCESEL_A::PCNT2)
513    }
514    #[doc = "CRYOTIMER"]
515    #[inline(always)]
516    pub fn cryotimer(self) -> &'a mut W {
517        self.variant(SOURCESEL_A::CRYOTIMER)
518    }
519    #[doc = "Clock Management Unit"]
520    #[inline(always)]
521    pub fn cmu(self) -> &'a mut W {
522        self.variant(SOURCESEL_A::CMU)
523    }
524    #[doc = "Digital to Analog Converter 0"]
525    #[inline(always)]
526    pub fn vdac0(self) -> &'a mut W {
527        self.variant(SOURCESEL_A::VDAC0)
528    }
529    #[doc = "Low Energy Sensor Interface"]
530    #[inline(always)]
531    pub fn lesensel(self) -> &'a mut W {
532        self.variant(SOURCESEL_A::LESENSEL)
533    }
534    #[doc = "Low Energy Sensor Interface"]
535    #[inline(always)]
536    pub fn lesenseh(self) -> &'a mut W {
537        self.variant(SOURCESEL_A::LESENSEH)
538    }
539    #[doc = "Low Energy Sensor Interface"]
540    #[inline(always)]
541    pub fn lesensed(self) -> &'a mut W {
542        self.variant(SOURCESEL_A::LESENSED)
543    }
544    #[doc = "Low Energy Sensor Interface"]
545    #[inline(always)]
546    pub fn lesense(self) -> &'a mut W {
547        self.variant(SOURCESEL_A::LESENSE)
548    }
549    #[doc = "Analog Comparator 1"]
550    #[inline(always)]
551    pub fn acmp2(self) -> &'a mut W {
552        self.variant(SOURCESEL_A::ACMP2)
553    }
554    #[doc = "Analog Comparator 3"]
555    #[inline(always)]
556    pub fn acmp3(self) -> &'a mut W {
557        self.variant(SOURCESEL_A::ACMP3)
558    }
559    #[doc = "Analog to Digital Converter 0"]
560    #[inline(always)]
561    pub fn adc1(self) -> &'a mut W {
562        self.variant(SOURCESEL_A::ADC1)
563    }
564    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
565    #[inline(always)]
566    pub fn usart0(self) -> &'a mut W {
567        self.variant(SOURCESEL_A::USART0)
568    }
569    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
570    #[inline(always)]
571    pub fn usart1(self) -> &'a mut W {
572        self.variant(SOURCESEL_A::USART1)
573    }
574    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
575    #[inline(always)]
576    pub fn usart2(self) -> &'a mut W {
577        self.variant(SOURCESEL_A::USART2)
578    }
579    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
580    #[inline(always)]
581    pub fn usart3(self) -> &'a mut W {
582        self.variant(SOURCESEL_A::USART3)
583    }
584    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 4"]
585    #[inline(always)]
586    pub fn usart4(self) -> &'a mut W {
587        self.variant(SOURCESEL_A::USART4)
588    }
589    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 5"]
590    #[inline(always)]
591    pub fn usart5(self) -> &'a mut W {
592        self.variant(SOURCESEL_A::USART5)
593    }
594    #[doc = "Universal Asynchronous Receiver/Transmitter 0"]
595    #[inline(always)]
596    pub fn uart0(self) -> &'a mut W {
597        self.variant(SOURCESEL_A::UART0)
598    }
599    #[doc = "Universal Asynchronous Receiver/Transmitter 1"]
600    #[inline(always)]
601    pub fn uart1(self) -> &'a mut W {
602        self.variant(SOURCESEL_A::UART1)
603    }
604    #[doc = "Timer 0"]
605    #[inline(always)]
606    pub fn timer0(self) -> &'a mut W {
607        self.variant(SOURCESEL_A::TIMER0)
608    }
609    #[doc = "Timer 1"]
610    #[inline(always)]
611    pub fn timer1(self) -> &'a mut W {
612        self.variant(SOURCESEL_A::TIMER1)
613    }
614    #[doc = "Timer 2"]
615    #[inline(always)]
616    pub fn timer2(self) -> &'a mut W {
617        self.variant(SOURCESEL_A::TIMER2)
618    }
619    #[doc = "`1000011`"]
620    #[inline(always)]
621    pub fn cm4(self) -> &'a mut W {
622        self.variant(SOURCESEL_A::CM4)
623    }
624    #[doc = "Timer 3"]
625    #[inline(always)]
626    pub fn timer3(self) -> &'a mut W {
627        self.variant(SOURCESEL_A::TIMER3)
628    }
629    #[doc = "Wide Timer 0"]
630    #[inline(always)]
631    pub fn wtimer0(self) -> &'a mut W {
632        self.variant(SOURCESEL_A::WTIMER0)
633    }
634    #[doc = "Wide Timer 0"]
635    #[inline(always)]
636    pub fn wtimer1(self) -> &'a mut W {
637        self.variant(SOURCESEL_A::WTIMER1)
638    }
639    #[doc = "Wide Timer 2"]
640    #[inline(always)]
641    pub fn wtimer2(self) -> &'a mut W {
642        self.variant(SOURCESEL_A::WTIMER2)
643    }
644    #[doc = "Wide Timer 3"]
645    #[inline(always)]
646    pub fn wtimer3(self) -> &'a mut W {
647        self.variant(SOURCESEL_A::WTIMER3)
648    }
649    #[doc = "Timer 4"]
650    #[inline(always)]
651    pub fn timer4(self) -> &'a mut W {
652        self.variant(SOURCESEL_A::TIMER4)
653    }
654    #[doc = "Timer 5"]
655    #[inline(always)]
656    pub fn timer5(self) -> &'a mut W {
657        self.variant(SOURCESEL_A::TIMER5)
658    }
659    #[doc = "Timer 6"]
660    #[inline(always)]
661    pub fn timer6(self) -> &'a mut W {
662        self.variant(SOURCESEL_A::TIMER6)
663    }
664}
665#[doc = "Edge Detect Select\n\nValue on reset: 0"]
666#[derive(Clone, Copy, Debug, PartialEq)]
667#[repr(u8)]
668pub enum EDSEL_A {
669    #[doc = "0: Signal is left as it is"]
670    OFF = 0,
671    #[doc = "1: A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
672    POSEDGE = 1,
673    #[doc = "2: A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
674    NEGEDGE = 2,
675    #[doc = "3: A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
676    BOTHEDGES = 3,
677}
678impl From<EDSEL_A> for u8 {
679    #[inline(always)]
680    fn from(variant: EDSEL_A) -> Self {
681        variant as _
682    }
683}
684#[doc = "Field `EDSEL` reader - Edge Detect Select"]
685pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
686impl EDSEL_R {
687    #[doc = "Get enumerated values variant"]
688    #[inline(always)]
689    pub fn variant(&self) -> EDSEL_A {
690        match self.bits {
691            0 => EDSEL_A::OFF,
692            1 => EDSEL_A::POSEDGE,
693            2 => EDSEL_A::NEGEDGE,
694            3 => EDSEL_A::BOTHEDGES,
695            _ => unreachable!(),
696        }
697    }
698    #[doc = "Checks if the value of the field is `OFF`"]
699    #[inline(always)]
700    pub fn is_off(&self) -> bool {
701        *self == EDSEL_A::OFF
702    }
703    #[doc = "Checks if the value of the field is `POSEDGE`"]
704    #[inline(always)]
705    pub fn is_posedge(&self) -> bool {
706        *self == EDSEL_A::POSEDGE
707    }
708    #[doc = "Checks if the value of the field is `NEGEDGE`"]
709    #[inline(always)]
710    pub fn is_negedge(&self) -> bool {
711        *self == EDSEL_A::NEGEDGE
712    }
713    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
714    #[inline(always)]
715    pub fn is_bothedges(&self) -> bool {
716        *self == EDSEL_A::BOTHEDGES
717    }
718}
719#[doc = "Field `EDSEL` writer - Edge Detect Select"]
720pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH17_CTRL_SPEC, u8, EDSEL_A, 2, 20>;
721impl<'a> EDSEL_W<'a> {
722    #[doc = "Signal is left as it is"]
723    #[inline(always)]
724    pub fn off(self) -> &'a mut W {
725        self.variant(EDSEL_A::OFF)
726    }
727    #[doc = "A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
728    #[inline(always)]
729    pub fn posedge(self) -> &'a mut W {
730        self.variant(EDSEL_A::POSEDGE)
731    }
732    #[doc = "A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
733    #[inline(always)]
734    pub fn negedge(self) -> &'a mut W {
735        self.variant(EDSEL_A::NEGEDGE)
736    }
737    #[doc = "A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
738    #[inline(always)]
739    pub fn bothedges(self) -> &'a mut W {
740        self.variant(EDSEL_A::BOTHEDGES)
741    }
742}
743#[doc = "Field `STRETCH` reader - Stretch Channel Output"]
744pub type STRETCH_R = crate::BitReader<bool>;
745#[doc = "Field `STRETCH` writer - Stretch Channel Output"]
746pub type STRETCH_W<'a> = crate::BitWriter<'a, u32, CH17_CTRL_SPEC, bool, 25>;
747#[doc = "Field `INV` reader - Invert Channel"]
748pub type INV_R = crate::BitReader<bool>;
749#[doc = "Field `INV` writer - Invert Channel"]
750pub type INV_W<'a> = crate::BitWriter<'a, u32, CH17_CTRL_SPEC, bool, 26>;
751#[doc = "Field `ORPREV` reader - Or Previous"]
752pub type ORPREV_R = crate::BitReader<bool>;
753#[doc = "Field `ORPREV` writer - Or Previous"]
754pub type ORPREV_W<'a> = crate::BitWriter<'a, u32, CH17_CTRL_SPEC, bool, 27>;
755#[doc = "Field `ANDNEXT` reader - And Next"]
756pub type ANDNEXT_R = crate::BitReader<bool>;
757#[doc = "Field `ANDNEXT` writer - And Next"]
758pub type ANDNEXT_W<'a> = crate::BitWriter<'a, u32, CH17_CTRL_SPEC, bool, 28>;
759#[doc = "Field `ASYNC` reader - Asynchronous Reflex"]
760pub type ASYNC_R = crate::BitReader<bool>;
761#[doc = "Field `ASYNC` writer - Asynchronous Reflex"]
762pub type ASYNC_W<'a> = crate::BitWriter<'a, u32, CH17_CTRL_SPEC, bool, 30>;
763impl R {
764    #[doc = "Bits 0:2 - Signal Select"]
765    #[inline(always)]
766    pub fn sigsel(&self) -> SIGSEL_R {
767        SIGSEL_R::new((self.bits & 7) as u8)
768    }
769    #[doc = "Bits 8:14 - Source Select"]
770    #[inline(always)]
771    pub fn sourcesel(&self) -> SOURCESEL_R {
772        SOURCESEL_R::new(((self.bits >> 8) & 0x7f) as u8)
773    }
774    #[doc = "Bits 20:21 - Edge Detect Select"]
775    #[inline(always)]
776    pub fn edsel(&self) -> EDSEL_R {
777        EDSEL_R::new(((self.bits >> 20) & 3) as u8)
778    }
779    #[doc = "Bit 25 - Stretch Channel Output"]
780    #[inline(always)]
781    pub fn stretch(&self) -> STRETCH_R {
782        STRETCH_R::new(((self.bits >> 25) & 1) != 0)
783    }
784    #[doc = "Bit 26 - Invert Channel"]
785    #[inline(always)]
786    pub fn inv(&self) -> INV_R {
787        INV_R::new(((self.bits >> 26) & 1) != 0)
788    }
789    #[doc = "Bit 27 - Or Previous"]
790    #[inline(always)]
791    pub fn orprev(&self) -> ORPREV_R {
792        ORPREV_R::new(((self.bits >> 27) & 1) != 0)
793    }
794    #[doc = "Bit 28 - And Next"]
795    #[inline(always)]
796    pub fn andnext(&self) -> ANDNEXT_R {
797        ANDNEXT_R::new(((self.bits >> 28) & 1) != 0)
798    }
799    #[doc = "Bit 30 - Asynchronous Reflex"]
800    #[inline(always)]
801    pub fn async_(&self) -> ASYNC_R {
802        ASYNC_R::new(((self.bits >> 30) & 1) != 0)
803    }
804}
805impl W {
806    #[doc = "Bits 0:2 - Signal Select"]
807    #[inline(always)]
808    pub fn sigsel(&mut self) -> SIGSEL_W {
809        SIGSEL_W::new(self)
810    }
811    #[doc = "Bits 8:14 - Source Select"]
812    #[inline(always)]
813    pub fn sourcesel(&mut self) -> SOURCESEL_W {
814        SOURCESEL_W::new(self)
815    }
816    #[doc = "Bits 20:21 - Edge Detect Select"]
817    #[inline(always)]
818    pub fn edsel(&mut self) -> EDSEL_W {
819        EDSEL_W::new(self)
820    }
821    #[doc = "Bit 25 - Stretch Channel Output"]
822    #[inline(always)]
823    pub fn stretch(&mut self) -> STRETCH_W {
824        STRETCH_W::new(self)
825    }
826    #[doc = "Bit 26 - Invert Channel"]
827    #[inline(always)]
828    pub fn inv(&mut self) -> INV_W {
829        INV_W::new(self)
830    }
831    #[doc = "Bit 27 - Or Previous"]
832    #[inline(always)]
833    pub fn orprev(&mut self) -> ORPREV_W {
834        ORPREV_W::new(self)
835    }
836    #[doc = "Bit 28 - And Next"]
837    #[inline(always)]
838    pub fn andnext(&mut self) -> ANDNEXT_W {
839        ANDNEXT_W::new(self)
840    }
841    #[doc = "Bit 30 - Asynchronous Reflex"]
842    #[inline(always)]
843    pub fn async_(&mut self) -> ASYNC_W {
844        ASYNC_W::new(self)
845    }
846    #[doc = "Writes raw bits to the register."]
847    #[inline(always)]
848    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
849        self.0.bits(bits);
850        self
851    }
852}
853#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch17_ctrl](index.html) module"]
854pub struct CH17_CTRL_SPEC;
855impl crate::RegisterSpec for CH17_CTRL_SPEC {
856    type Ux = u32;
857}
858#[doc = "`read()` method returns [ch17_ctrl::R](R) reader structure"]
859impl crate::Readable for CH17_CTRL_SPEC {
860    type Reader = R;
861}
862#[doc = "`write(|w| ..)` method takes [ch17_ctrl::W](W) writer structure"]
863impl crate::Writable for CH17_CTRL_SPEC {
864    type Writer = W;
865}
866#[doc = "`reset()` method sets CH17_CTRL to value 0"]
867impl crate::Resettable for CH17_CTRL_SPEC {
868    #[inline(always)]
869    fn reset_value() -> Self::Ux {
870        0
871    }
872}
efm32gg11b310_pac/prs/ch17_ctrl.rs

efm32gg11b310_pac/prs/
ch17_ctrl.rs
