1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `EN` reader - Analog Comparator Enable"]
38pub type EN_R = crate::BitReader<bool>;
39#[doc = "Field `EN` writer - Analog Comparator Enable"]
40pub type EN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 0>;
41#[doc = "Field `INACTVAL` reader - Inactive Value"]
42pub type INACTVAL_R = crate::BitReader<bool>;
43#[doc = "Field `INACTVAL` writer - Inactive Value"]
44pub type INACTVAL_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 2>;
45#[doc = "Field `GPIOINV` reader - Comparator GPIO Output Invert"]
46pub type GPIOINV_R = crate::BitReader<bool>;
47#[doc = "Field `GPIOINV` writer - Comparator GPIO Output Invert"]
48pub type GPIOINV_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 3>;
49#[doc = "Field `APORTXMASTERDIS` reader - APORT Bus X Master Disable"]
50pub type APORTXMASTERDIS_R = crate::BitReader<bool>;
51#[doc = "Field `APORTXMASTERDIS` writer - APORT Bus X Master Disable"]
52pub type APORTXMASTERDIS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 8>;
53#[doc = "Field `APORTYMASTERDIS` reader - APORT Bus Y Master Disable"]
54pub type APORTYMASTERDIS_R = crate::BitReader<bool>;
55#[doc = "Field `APORTYMASTERDIS` writer - APORT Bus Y Master Disable"]
56pub type APORTYMASTERDIS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 9>;
57#[doc = "Field `APORTVMASTERDIS` reader - APORT Bus Master Disable for Bus Selected By VASEL"]
58pub type APORTVMASTERDIS_R = crate::BitReader<bool>;
59#[doc = "Field `APORTVMASTERDIS` writer - APORT Bus Master Disable for Bus Selected By VASEL"]
60pub type APORTVMASTERDIS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 10>;
61#[doc = "Power Select\n\nValue on reset: 0"]
62#[derive(Clone, Copy, Debug, PartialEq)]
63#[repr(u8)]
64pub enum PWRSEL_A {
65 #[doc = "0: AVDD supply"]
66 AVDD = 0,
67 #[doc = "1: DVDD supply"]
68 DVDD = 1,
69 #[doc = "2: IOVDD/IOVDD0 supply"]
70 IOVDD0 = 2,
71 #[doc = "4: IOVDD1 supply (if part has two I/O voltages)"]
72 IOVDD1 = 4,
73}
74impl From<PWRSEL_A> for u8 {
75 #[inline(always)]
76 fn from(variant: PWRSEL_A) -> Self {
77 variant as _
78 }
79}
80#[doc = "Field `PWRSEL` reader - Power Select"]
81pub type PWRSEL_R = crate::FieldReader<u8, PWRSEL_A>;
82impl PWRSEL_R {
83 #[doc = "Get enumerated values variant"]
84 #[inline(always)]
85 pub fn variant(&self) -> Option<PWRSEL_A> {
86 match self.bits {
87 0 => Some(PWRSEL_A::AVDD),
88 1 => Some(PWRSEL_A::DVDD),
89 2 => Some(PWRSEL_A::IOVDD0),
90 4 => Some(PWRSEL_A::IOVDD1),
91 _ => None,
92 }
93 }
94 #[doc = "Checks if the value of the field is `AVDD`"]
95 #[inline(always)]
96 pub fn is_avdd(&self) -> bool {
97 *self == PWRSEL_A::AVDD
98 }
99 #[doc = "Checks if the value of the field is `DVDD`"]
100 #[inline(always)]
101 pub fn is_dvdd(&self) -> bool {
102 *self == PWRSEL_A::DVDD
103 }
104 #[doc = "Checks if the value of the field is `IOVDD0`"]
105 #[inline(always)]
106 pub fn is_iovdd0(&self) -> bool {
107 *self == PWRSEL_A::IOVDD0
108 }
109 #[doc = "Checks if the value of the field is `IOVDD1`"]
110 #[inline(always)]
111 pub fn is_iovdd1(&self) -> bool {
112 *self == PWRSEL_A::IOVDD1
113 }
114}
115#[doc = "Field `PWRSEL` writer - Power Select"]
116pub type PWRSEL_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, PWRSEL_A, 3, 12>;
117impl<'a> PWRSEL_W<'a> {
118 #[doc = "AVDD supply"]
119 #[inline(always)]
120 pub fn avdd(self) -> &'a mut W {
121 self.variant(PWRSEL_A::AVDD)
122 }
123 #[doc = "DVDD supply"]
124 #[inline(always)]
125 pub fn dvdd(self) -> &'a mut W {
126 self.variant(PWRSEL_A::DVDD)
127 }
128 #[doc = "IOVDD/IOVDD0 supply"]
129 #[inline(always)]
130 pub fn iovdd0(self) -> &'a mut W {
131 self.variant(PWRSEL_A::IOVDD0)
132 }
133 #[doc = "IOVDD1 supply (if part has two I/O voltages)"]
134 #[inline(always)]
135 pub fn iovdd1(self) -> &'a mut W {
136 self.variant(PWRSEL_A::IOVDD1)
137 }
138}
139#[doc = "Field `ACCURACY` reader - ACMP Accuracy Mode"]
140pub type ACCURACY_R = crate::BitReader<bool>;
141#[doc = "Field `ACCURACY` writer - ACMP Accuracy Mode"]
142pub type ACCURACY_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 15>;
143#[doc = "Input Range\n\nValue on reset: 0"]
144#[derive(Clone, Copy, Debug, PartialEq)]
145#[repr(u8)]
146pub enum INPUTRANGE_A {
147 #[doc = "0: Setting when the input can be from 0 to ACMPVDD."]
148 FULL = 0,
149 #[doc = "1: Setting when the input will always be greater than ACMPVDD/2."]
150 GTVDDDIV2 = 1,
151 #[doc = "2: Setting when the input will always be less than ACMPVDD/2."]
152 LTVDDDIV2 = 2,
153}
154impl From<INPUTRANGE_A> for u8 {
155 #[inline(always)]
156 fn from(variant: INPUTRANGE_A) -> Self {
157 variant as _
158 }
159}
160#[doc = "Field `INPUTRANGE` reader - Input Range"]
161pub type INPUTRANGE_R = crate::FieldReader<u8, INPUTRANGE_A>;
162impl INPUTRANGE_R {
163 #[doc = "Get enumerated values variant"]
164 #[inline(always)]
165 pub fn variant(&self) -> Option<INPUTRANGE_A> {
166 match self.bits {
167 0 => Some(INPUTRANGE_A::FULL),
168 1 => Some(INPUTRANGE_A::GTVDDDIV2),
169 2 => Some(INPUTRANGE_A::LTVDDDIV2),
170 _ => None,
171 }
172 }
173 #[doc = "Checks if the value of the field is `FULL`"]
174 #[inline(always)]
175 pub fn is_full(&self) -> bool {
176 *self == INPUTRANGE_A::FULL
177 }
178 #[doc = "Checks if the value of the field is `GTVDDDIV2`"]
179 #[inline(always)]
180 pub fn is_gtvdddiv2(&self) -> bool {
181 *self == INPUTRANGE_A::GTVDDDIV2
182 }
183 #[doc = "Checks if the value of the field is `LTVDDDIV2`"]
184 #[inline(always)]
185 pub fn is_ltvdddiv2(&self) -> bool {
186 *self == INPUTRANGE_A::LTVDDDIV2
187 }
188}
189#[doc = "Field `INPUTRANGE` writer - Input Range"]
190pub type INPUTRANGE_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, INPUTRANGE_A, 2, 18>;
191impl<'a> INPUTRANGE_W<'a> {
192 #[doc = "Setting when the input can be from 0 to ACMPVDD."]
193 #[inline(always)]
194 pub fn full(self) -> &'a mut W {
195 self.variant(INPUTRANGE_A::FULL)
196 }
197 #[doc = "Setting when the input will always be greater than ACMPVDD/2."]
198 #[inline(always)]
199 pub fn gtvdddiv2(self) -> &'a mut W {
200 self.variant(INPUTRANGE_A::GTVDDDIV2)
201 }
202 #[doc = "Setting when the input will always be less than ACMPVDD/2."]
203 #[inline(always)]
204 pub fn ltvdddiv2(self) -> &'a mut W {
205 self.variant(INPUTRANGE_A::LTVDDDIV2)
206 }
207}
208#[doc = "Field `IRISE` reader - Rising Edge Interrupt Sense"]
209pub type IRISE_R = crate::BitReader<bool>;
210#[doc = "Field `IRISE` writer - Rising Edge Interrupt Sense"]
211pub type IRISE_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 20>;
212#[doc = "Field `IFALL` reader - Falling Edge Interrupt Sense"]
213pub type IFALL_R = crate::BitReader<bool>;
214#[doc = "Field `IFALL` writer - Falling Edge Interrupt Sense"]
215pub type IFALL_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 21>;
216#[doc = "Field `BIASPROG` reader - Bias Configuration"]
217pub type BIASPROG_R = crate::FieldReader<u8, u8>;
218#[doc = "Field `BIASPROG` writer - Bias Configuration"]
219pub type BIASPROG_W<'a> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, u8, 6, 24>;
220#[doc = "Field `FULLBIAS` reader - Full Bias Current"]
221pub type FULLBIAS_R = crate::BitReader<bool>;
222#[doc = "Field `FULLBIAS` writer - Full Bias Current"]
223pub type FULLBIAS_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 31>;
224impl R {
225 #[doc = "Bit 0 - Analog Comparator Enable"]
226 #[inline(always)]
227 pub fn en(&self) -> EN_R {
228 EN_R::new((self.bits & 1) != 0)
229 }
230 #[doc = "Bit 2 - Inactive Value"]
231 #[inline(always)]
232 pub fn inactval(&self) -> INACTVAL_R {
233 INACTVAL_R::new(((self.bits >> 2) & 1) != 0)
234 }
235 #[doc = "Bit 3 - Comparator GPIO Output Invert"]
236 #[inline(always)]
237 pub fn gpioinv(&self) -> GPIOINV_R {
238 GPIOINV_R::new(((self.bits >> 3) & 1) != 0)
239 }
240 #[doc = "Bit 8 - APORT Bus X Master Disable"]
241 #[inline(always)]
242 pub fn aportxmasterdis(&self) -> APORTXMASTERDIS_R {
243 APORTXMASTERDIS_R::new(((self.bits >> 8) & 1) != 0)
244 }
245 #[doc = "Bit 9 - APORT Bus Y Master Disable"]
246 #[inline(always)]
247 pub fn aportymasterdis(&self) -> APORTYMASTERDIS_R {
248 APORTYMASTERDIS_R::new(((self.bits >> 9) & 1) != 0)
249 }
250 #[doc = "Bit 10 - APORT Bus Master Disable for Bus Selected By VASEL"]
251 #[inline(always)]
252 pub fn aportvmasterdis(&self) -> APORTVMASTERDIS_R {
253 APORTVMASTERDIS_R::new(((self.bits >> 10) & 1) != 0)
254 }
255 #[doc = "Bits 12:14 - Power Select"]
256 #[inline(always)]
257 pub fn pwrsel(&self) -> PWRSEL_R {
258 PWRSEL_R::new(((self.bits >> 12) & 7) as u8)
259 }
260 #[doc = "Bit 15 - ACMP Accuracy Mode"]
261 #[inline(always)]
262 pub fn accuracy(&self) -> ACCURACY_R {
263 ACCURACY_R::new(((self.bits >> 15) & 1) != 0)
264 }
265 #[doc = "Bits 18:19 - Input Range"]
266 #[inline(always)]
267 pub fn inputrange(&self) -> INPUTRANGE_R {
268 INPUTRANGE_R::new(((self.bits >> 18) & 3) as u8)
269 }
270 #[doc = "Bit 20 - Rising Edge Interrupt Sense"]
271 #[inline(always)]
272 pub fn irise(&self) -> IRISE_R {
273 IRISE_R::new(((self.bits >> 20) & 1) != 0)
274 }
275 #[doc = "Bit 21 - Falling Edge Interrupt Sense"]
276 #[inline(always)]
277 pub fn ifall(&self) -> IFALL_R {
278 IFALL_R::new(((self.bits >> 21) & 1) != 0)
279 }
280 #[doc = "Bits 24:29 - Bias Configuration"]
281 #[inline(always)]
282 pub fn biasprog(&self) -> BIASPROG_R {
283 BIASPROG_R::new(((self.bits >> 24) & 0x3f) as u8)
284 }
285 #[doc = "Bit 31 - Full Bias Current"]
286 #[inline(always)]
287 pub fn fullbias(&self) -> FULLBIAS_R {
288 FULLBIAS_R::new(((self.bits >> 31) & 1) != 0)
289 }
290}
291impl W {
292 #[doc = "Bit 0 - Analog Comparator Enable"]
293 #[inline(always)]
294 pub fn en(&mut self) -> EN_W {
295 EN_W::new(self)
296 }
297 #[doc = "Bit 2 - Inactive Value"]
298 #[inline(always)]
299 pub fn inactval(&mut self) -> INACTVAL_W {
300 INACTVAL_W::new(self)
301 }
302 #[doc = "Bit 3 - Comparator GPIO Output Invert"]
303 #[inline(always)]
304 pub fn gpioinv(&mut self) -> GPIOINV_W {
305 GPIOINV_W::new(self)
306 }
307 #[doc = "Bit 8 - APORT Bus X Master Disable"]
308 #[inline(always)]
309 pub fn aportxmasterdis(&mut self) -> APORTXMASTERDIS_W {
310 APORTXMASTERDIS_W::new(self)
311 }
312 #[doc = "Bit 9 - APORT Bus Y Master Disable"]
313 #[inline(always)]
314 pub fn aportymasterdis(&mut self) -> APORTYMASTERDIS_W {
315 APORTYMASTERDIS_W::new(self)
316 }
317 #[doc = "Bit 10 - APORT Bus Master Disable for Bus Selected By VASEL"]
318 #[inline(always)]
319 pub fn aportvmasterdis(&mut self) -> APORTVMASTERDIS_W {
320 APORTVMASTERDIS_W::new(self)
321 }
322 #[doc = "Bits 12:14 - Power Select"]
323 #[inline(always)]
324 pub fn pwrsel(&mut self) -> PWRSEL_W {
325 PWRSEL_W::new(self)
326 }
327 #[doc = "Bit 15 - ACMP Accuracy Mode"]
328 #[inline(always)]
329 pub fn accuracy(&mut self) -> ACCURACY_W {
330 ACCURACY_W::new(self)
331 }
332 #[doc = "Bits 18:19 - Input Range"]
333 #[inline(always)]
334 pub fn inputrange(&mut self) -> INPUTRANGE_W {
335 INPUTRANGE_W::new(self)
336 }
337 #[doc = "Bit 20 - Rising Edge Interrupt Sense"]
338 #[inline(always)]
339 pub fn irise(&mut self) -> IRISE_W {
340 IRISE_W::new(self)
341 }
342 #[doc = "Bit 21 - Falling Edge Interrupt Sense"]
343 #[inline(always)]
344 pub fn ifall(&mut self) -> IFALL_W {
345 IFALL_W::new(self)
346 }
347 #[doc = "Bits 24:29 - Bias Configuration"]
348 #[inline(always)]
349 pub fn biasprog(&mut self) -> BIASPROG_W {
350 BIASPROG_W::new(self)
351 }
352 #[doc = "Bit 31 - Full Bias Current"]
353 #[inline(always)]
354 pub fn fullbias(&mut self) -> FULLBIAS_W {
355 FULLBIAS_W::new(self)
356 }
357 #[doc = "Writes raw bits to the register."]
358 #[inline(always)]
359 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
360 self.0.bits(bits);
361 self
362 }
363}
364#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
365pub struct CTRL_SPEC;
366impl crate::RegisterSpec for CTRL_SPEC {
367 type Ux = u32;
368}
369#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
370impl crate::Readable for CTRL_SPEC {
371 type Reader = R;
372}
373#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
374impl crate::Writable for CTRL_SPEC {
375 type Writer = W;
376}
377#[doc = "`reset()` method sets CTRL to value 0x0700_0000"]
378impl crate::Resettable for CTRL_SPEC {
379 #[inline(always)]
380 fn reset_value() -> Self::Ux {
381 0x0700_0000
382 }
383}