efm32gg11b110_pac/msc/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ADDRFAULTEN` reader - Invalid Address Bus Fault Response Enable"]
38pub type ADDRFAULTEN_R = crate::BitReader<bool>;
39#[doc = "Field `ADDRFAULTEN` writer - Invalid Address Bus Fault Response Enable"]
40pub type ADDRFAULTEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 0>;
41#[doc = "Field `CLKDISFAULTEN` reader - Clock-disabled Bus Fault Response Enable"]
42pub type CLKDISFAULTEN_R = crate::BitReader<bool>;
43#[doc = "Field `CLKDISFAULTEN` writer - Clock-disabled Bus Fault Response Enable"]
44pub type CLKDISFAULTEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 1>;
45#[doc = "Field `PWRUPONDEMAND` reader - Power Up on Demand During Wake Up"]
46pub type PWRUPONDEMAND_R = crate::BitReader<bool>;
47#[doc = "Field `PWRUPONDEMAND` writer - Power Up on Demand During Wake Up"]
48pub type PWRUPONDEMAND_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 2>;
49#[doc = "Field `IFCREADCLEAR` reader - IFC Read Clears IF"]
50pub type IFCREADCLEAR_R = crate::BitReader<bool>;
51#[doc = "Field `IFCREADCLEAR` writer - IFC Read Clears IF"]
52pub type IFCREADCLEAR_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 3>;
53#[doc = "Field `TIMEOUTFAULTEN` reader - Timeout Bus Fault Response Enable"]
54pub type TIMEOUTFAULTEN_R = crate::BitReader<bool>;
55#[doc = "Field `TIMEOUTFAULTEN` writer - Timeout Bus Fault Response Enable"]
56pub type TIMEOUTFAULTEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 4>;
57#[doc = "Field `RAMECCERRFAULTEN` reader - Two Bit ECC Error Bus Fault Response Enable"]
58pub type RAMECCERRFAULTEN_R = crate::BitReader<bool>;
59#[doc = "Field `RAMECCERRFAULTEN` writer - Two Bit ECC Error Bus Fault Response Enable"]
60pub type RAMECCERRFAULTEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 5>;
61#[doc = "Field `EBIFAULTEN` reader - EBI Bus Fault Response Enable"]
62pub type EBIFAULTEN_R = crate::BitReader<bool>;
63#[doc = "Field `EBIFAULTEN` writer - EBI Bus Fault Response Enable"]
64pub type EBIFAULTEN_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 6>;
65#[doc = "Field `WAITMODE` reader - Peripheral Access Wait Mode"]
66pub type WAITMODE_R = crate::BitReader<bool>;
67#[doc = "Field `WAITMODE` writer - Peripheral Access Wait Mode"]
68pub type WAITMODE_W<'a> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, 12>;
69impl R {
70    #[doc = "Bit 0 - Invalid Address Bus Fault Response Enable"]
71    #[inline(always)]
72    pub fn addrfaulten(&self) -> ADDRFAULTEN_R {
73        ADDRFAULTEN_R::new((self.bits & 1) != 0)
74    }
75    #[doc = "Bit 1 - Clock-disabled Bus Fault Response Enable"]
76    #[inline(always)]
77    pub fn clkdisfaulten(&self) -> CLKDISFAULTEN_R {
78        CLKDISFAULTEN_R::new(((self.bits >> 1) & 1) != 0)
79    }
80    #[doc = "Bit 2 - Power Up on Demand During Wake Up"]
81    #[inline(always)]
82    pub fn pwrupondemand(&self) -> PWRUPONDEMAND_R {
83        PWRUPONDEMAND_R::new(((self.bits >> 2) & 1) != 0)
84    }
85    #[doc = "Bit 3 - IFC Read Clears IF"]
86    #[inline(always)]
87    pub fn ifcreadclear(&self) -> IFCREADCLEAR_R {
88        IFCREADCLEAR_R::new(((self.bits >> 3) & 1) != 0)
89    }
90    #[doc = "Bit 4 - Timeout Bus Fault Response Enable"]
91    #[inline(always)]
92    pub fn timeoutfaulten(&self) -> TIMEOUTFAULTEN_R {
93        TIMEOUTFAULTEN_R::new(((self.bits >> 4) & 1) != 0)
94    }
95    #[doc = "Bit 5 - Two Bit ECC Error Bus Fault Response Enable"]
96    #[inline(always)]
97    pub fn rameccerrfaulten(&self) -> RAMECCERRFAULTEN_R {
98        RAMECCERRFAULTEN_R::new(((self.bits >> 5) & 1) != 0)
99    }
100    #[doc = "Bit 6 - EBI Bus Fault Response Enable"]
101    #[inline(always)]
102    pub fn ebifaulten(&self) -> EBIFAULTEN_R {
103        EBIFAULTEN_R::new(((self.bits >> 6) & 1) != 0)
104    }
105    #[doc = "Bit 12 - Peripheral Access Wait Mode"]
106    #[inline(always)]
107    pub fn waitmode(&self) -> WAITMODE_R {
108        WAITMODE_R::new(((self.bits >> 12) & 1) != 0)
109    }
110}
111impl W {
112    #[doc = "Bit 0 - Invalid Address Bus Fault Response Enable"]
113    #[inline(always)]
114    pub fn addrfaulten(&mut self) -> ADDRFAULTEN_W {
115        ADDRFAULTEN_W::new(self)
116    }
117    #[doc = "Bit 1 - Clock-disabled Bus Fault Response Enable"]
118    #[inline(always)]
119    pub fn clkdisfaulten(&mut self) -> CLKDISFAULTEN_W {
120        CLKDISFAULTEN_W::new(self)
121    }
122    #[doc = "Bit 2 - Power Up on Demand During Wake Up"]
123    #[inline(always)]
124    pub fn pwrupondemand(&mut self) -> PWRUPONDEMAND_W {
125        PWRUPONDEMAND_W::new(self)
126    }
127    #[doc = "Bit 3 - IFC Read Clears IF"]
128    #[inline(always)]
129    pub fn ifcreadclear(&mut self) -> IFCREADCLEAR_W {
130        IFCREADCLEAR_W::new(self)
131    }
132    #[doc = "Bit 4 - Timeout Bus Fault Response Enable"]
133    #[inline(always)]
134    pub fn timeoutfaulten(&mut self) -> TIMEOUTFAULTEN_W {
135        TIMEOUTFAULTEN_W::new(self)
136    }
137    #[doc = "Bit 5 - Two Bit ECC Error Bus Fault Response Enable"]
138    #[inline(always)]
139    pub fn rameccerrfaulten(&mut self) -> RAMECCERRFAULTEN_W {
140        RAMECCERRFAULTEN_W::new(self)
141    }
142    #[doc = "Bit 6 - EBI Bus Fault Response Enable"]
143    #[inline(always)]
144    pub fn ebifaulten(&mut self) -> EBIFAULTEN_W {
145        EBIFAULTEN_W::new(self)
146    }
147    #[doc = "Bit 12 - Peripheral Access Wait Mode"]
148    #[inline(always)]
149    pub fn waitmode(&mut self) -> WAITMODE_W {
150        WAITMODE_W::new(self)
151    }
152    #[doc = "Writes raw bits to the register."]
153    #[inline(always)]
154    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
155        self.0.bits(bits);
156        self
157    }
158}
159#[doc = "Memory System Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
160pub struct CTRL_SPEC;
161impl crate::RegisterSpec for CTRL_SPEC {
162    type Ux = u32;
163}
164#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
165impl crate::Readable for CTRL_SPEC {
166    type Reader = R;
167}
168#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
169impl crate::Writable for CTRL_SPEC {
170    type Writer = W;
171}
172#[doc = "`reset()` method sets CTRL to value 0x21"]
173impl crate::Resettable for CTRL_SPEC {
174    #[inline(always)]
175    fn reset_value() -> Self::Ux {
176        0x21
177    }
178}
efm32gg11b110_pac/msc/ctrl.rs

efm32gg11b110_pac/msc/
ctrl.rs
