Type Definition efm32gg11b::vdac0::opa0_ctrl::W[][src]

type W = W<u32, OPA0_CTRL>;
Expand description

Writer for register OPA0_CTRL

Implementations

Bits 0:1 - OPAx Operation Mode

Bit 2 - OPAx Unity Gain Bandwidth Scale

Bit 3 - High Common Mode Disable

Bit 4 - Scale OPAx Output Driving Strength

Bit 8 - OPAx PRS Trigger Enable

Bit 9 - OPAx PRS Trigger Mode

Bits 10:14 - OPAx PRS Trigger Select

Bit 16 - OPAx PRS Output Select

Bit 20 - APORT Bus Master Disable

Bit 21 - APORT Bus Master Disable