Struct efm32gg11b::SCB [−][src]
pub struct SCB { /* fields omitted */ }
Expand description
System Control Block
Implementations
Returns the active exception number
Enables I-Cache if currently disabled
Disables I-Cache if currently enabled
Returns whether the I-Cache is currently enabled
Invalidates I-Cache
Enables D-cache if currently disabled
Disables D-cache if currently enabled
Returns whether the D-Cache is currently enabled
Cleans D-cache
Cleans and invalidates D-cache
Invalidates D-cache by address
addr
: the address to invalidate
size
: size of the memory block, in number of bytes
Invalidates cache starting from the lowest 32-byte aligned address represented by addr
,
in blocks of 32 bytes until at least size
bytes have been invalidated.
Cleans D-cache by address
addr
: the address to clean
size
: size of the memory block, in number of bytes
Cleans cache starting from the lowest 32-byte aligned address represented by addr
,
in blocks of 32 bytes until at least size
bytes have been cleaned.
Cleans and invalidates D-cache by address
addr
: the address to clean and invalidate
size
: size of the memory block, in number of bytes
Cleans and invalidates cache starting from the lowest 32-byte aligned address represented
by addr
, in blocks of 32 bytes until at least size
bytes have been cleaned and
invalidated.
Set the SLEEPDEEP bit in the SCR register
Clear the SLEEPDEEP bit in the SCR register
Initiate a system reset request to reset the MCU
Set the PENDSVSET bit in the ICSR register which will pend the PendSV interrupt
Check if PENDSVSET bit in the ICSR register is set meaning PendSV interrupt is pending
Set the PENDSVCLR bit in the ICSR register which will clear a pending PendSV interrupt
Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt
Check if PENDSTSET bit in the ICSR register is set meaning SysTick interrupt is pending
Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt
Returns the hardware priority of system_handler
NOTE: Hardware priority does not exactly match logical priority levels. See
NVIC.get_priority
for more details.
Sets the hardware priority of system_handler
to prio
NOTE: Hardware priority does not exactly match logical priority levels. See
NVIC.get_priority
for more details.
On ARMv6-M, updating a system handler priority requires a read-modify-write operation. On ARMv7-M, the operation is performed in a single, atomic write operation.
Unsafety
Changing priority levels can break priority-based critical sections (see
register::basepri
) and compromise memory safety.
Returns a pointer to the register block