Struct efm32gg11b::prs::ch11_ctrl::EDSEL_W [−][src]
pub struct EDSEL_W<'a> { /* fields omitted */ }
Expand description
Write proxy for field EDSEL
Implementations
A one HFCLK cycle pulse is generated for every positive edge of the incoming signal
A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal
A one HFCLK clock cycle pulse is generated for every edge of the incoming signal