Enum efm32gg11b::crypto0::ctrl::DMA1MODE_A [−][src]
#[repr(u8)] pub enum DMA1MODE_A { FULL, LENLIMIT, FULLBYTE, LENLIMITBYTE, }
Expand description
DMA1 Read Mode
Value on reset: 0
Variants
0: Target register is fully read/written during every DMA transaction
1: Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + 1 bytes + necessary zero padding is read. Zero padding is automatically added when writing.
2: Target register is fully read/written during every DMA transaction. Bytewise DMA.
3: Length Limited. When the current length, i.e. LENGTHA or LENGTHB indicates that there are less bytes available than the register size, only length + 1 bytes + necessary zero padding is read. Bytewise DMA. Zero padding is automatically added when writing.
Trait Implementations
Performs the conversion.