efm32gg11b/usart0/
status.rs

1#[doc = "Reader of register STATUS"]
2pub type R = crate::R<u32, super::STATUS>;
3#[doc = "Reader of field `RXENS`"]
4pub type RXENS_R = crate::R<bool, bool>;
5#[doc = "Reader of field `TXENS`"]
6pub type TXENS_R = crate::R<bool, bool>;
7#[doc = "Reader of field `MASTER`"]
8pub type MASTER_R = crate::R<bool, bool>;
9#[doc = "Reader of field `RXBLOCK`"]
10pub type RXBLOCK_R = crate::R<bool, bool>;
11#[doc = "Reader of field `TXTRI`"]
12pub type TXTRI_R = crate::R<bool, bool>;
13#[doc = "Reader of field `TXC`"]
14pub type TXC_R = crate::R<bool, bool>;
15#[doc = "Reader of field `TXBL`"]
16pub type TXBL_R = crate::R<bool, bool>;
17#[doc = "Reader of field `RXDATAV`"]
18pub type RXDATAV_R = crate::R<bool, bool>;
19#[doc = "Reader of field `RXFULL`"]
20pub type RXFULL_R = crate::R<bool, bool>;
21#[doc = "Reader of field `TXBDRIGHT`"]
22pub type TXBDRIGHT_R = crate::R<bool, bool>;
23#[doc = "Reader of field `TXBSRIGHT`"]
24pub type TXBSRIGHT_R = crate::R<bool, bool>;
25#[doc = "Reader of field `RXDATAVRIGHT`"]
26pub type RXDATAVRIGHT_R = crate::R<bool, bool>;
27#[doc = "Reader of field `RXFULLRIGHT`"]
28pub type RXFULLRIGHT_R = crate::R<bool, bool>;
29#[doc = "Reader of field `TXIDLE`"]
30pub type TXIDLE_R = crate::R<bool, bool>;
31#[doc = "Reader of field `TIMERRESTARTED`"]
32pub type TIMERRESTARTED_R = crate::R<bool, bool>;
33#[doc = "Reader of field `TXBUFCNT`"]
34pub type TXBUFCNT_R = crate::R<u8, u8>;
35impl R {
36    #[doc = "Bit 0 - Receiver Enable Status"]
37    #[inline(always)]
38    pub fn rxens(&self) -> RXENS_R { RXENS_R::new((self.bits & 0x01) != 0) }
39    #[doc = "Bit 1 - Transmitter Enable Status"]
40    #[inline(always)]
41    pub fn txens(&self) -> TXENS_R { TXENS_R::new(((self.bits >> 1) & 0x01) != 0) }
42    #[doc = "Bit 2 - SPI Master Mode"]
43    #[inline(always)]
44    pub fn master(&self) -> MASTER_R { MASTER_R::new(((self.bits >> 2) & 0x01) != 0) }
45    #[doc = "Bit 3 - Block Incoming Data"]
46    #[inline(always)]
47    pub fn rxblock(&self) -> RXBLOCK_R { RXBLOCK_R::new(((self.bits >> 3) & 0x01) != 0) }
48    #[doc = "Bit 4 - Transmitter Tristated"]
49    #[inline(always)]
50    pub fn txtri(&self) -> TXTRI_R { TXTRI_R::new(((self.bits >> 4) & 0x01) != 0) }
51    #[doc = "Bit 5 - TX Complete"]
52    #[inline(always)]
53    pub fn txc(&self) -> TXC_R { TXC_R::new(((self.bits >> 5) & 0x01) != 0) }
54    #[doc = "Bit 6 - TX Buffer Level"]
55    #[inline(always)]
56    pub fn txbl(&self) -> TXBL_R { TXBL_R::new(((self.bits >> 6) & 0x01) != 0) }
57    #[doc = "Bit 7 - RX Data Valid"]
58    #[inline(always)]
59    pub fn rxdatav(&self) -> RXDATAV_R { RXDATAV_R::new(((self.bits >> 7) & 0x01) != 0) }
60    #[doc = "Bit 8 - RX FIFO Full"]
61    #[inline(always)]
62    pub fn rxfull(&self) -> RXFULL_R { RXFULL_R::new(((self.bits >> 8) & 0x01) != 0) }
63    #[doc = "Bit 9 - TX Buffer Expects Double Right Data"]
64    #[inline(always)]
65    pub fn txbdright(&self) -> TXBDRIGHT_R { TXBDRIGHT_R::new(((self.bits >> 9) & 0x01) != 0) }
66    #[doc = "Bit 10 - TX Buffer Expects Single Right Data"]
67    #[inline(always)]
68    pub fn txbsright(&self) -> TXBSRIGHT_R { TXBSRIGHT_R::new(((self.bits >> 10) & 0x01) != 0) }
69    #[doc = "Bit 11 - RX Data Right"]
70    #[inline(always)]
71    pub fn rxdatavright(&self) -> RXDATAVRIGHT_R {
72        RXDATAVRIGHT_R::new(((self.bits >> 11) & 0x01) != 0)
73    }
74    #[doc = "Bit 12 - RX Full of Right Data"]
75    #[inline(always)]
76    pub fn rxfullright(&self) -> RXFULLRIGHT_R {
77        RXFULLRIGHT_R::new(((self.bits >> 12) & 0x01) != 0)
78    }
79    #[doc = "Bit 13 - TX Idle"]
80    #[inline(always)]
81    pub fn txidle(&self) -> TXIDLE_R { TXIDLE_R::new(((self.bits >> 13) & 0x01) != 0) }
82    #[doc = "Bit 14 - The USART Timer Restarted Itself"]
83    #[inline(always)]
84    pub fn timerrestarted(&self) -> TIMERRESTARTED_R {
85        TIMERRESTARTED_R::new(((self.bits >> 14) & 0x01) != 0)
86    }
87    #[doc = "Bits 16:17 - TX Buffer Count"]
88    #[inline(always)]
89    pub fn txbufcnt(&self) -> TXBUFCNT_R { TXBUFCNT_R::new(((self.bits >> 16) & 0x03) as u8) }
90}
efm32gg11b/usart0/status.rs

efm32gg11b/usart0/
status.rs
