efm32gg11b/usart0/
ctrlx.rs

1#[doc = "Reader of register CTRLX"]
2pub type R = crate::R<u32, super::CTRLX>;
3#[doc = "Writer for register CTRLX"]
4pub type W = crate::W<u32, super::CTRLX>;
5#[doc = "Register CTRLX `reset()`'s with value 0"]
6impl crate::ResetValue for super::CTRLX {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type { 0 }
10}
11#[doc = "Reader of field `DBGHALT`"]
12pub type DBGHALT_R = crate::R<bool, bool>;
13#[doc = "Write proxy for field `DBGHALT`"]
14pub struct DBGHALT_W<'a> {
15    w: &'a mut W,
16}
17impl<'a> DBGHALT_W<'a> {
18    #[doc = r"Sets the field bit"]
19    #[inline(always)]
20    pub fn set_bit(self) -> &'a mut W { self.bit(true) }
21    #[doc = r"Clears the field bit"]
22    #[inline(always)]
23    pub fn clear_bit(self) -> &'a mut W { self.bit(false) }
24    #[doc = r"Writes raw bits to the field"]
25    #[inline(always)]
26    pub fn bit(self, value: bool) -> &'a mut W {
27        self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
28        self.w
29    }
30}
31#[doc = "Reader of field `CTSINV`"]
32pub type CTSINV_R = crate::R<bool, bool>;
33#[doc = "Write proxy for field `CTSINV`"]
34pub struct CTSINV_W<'a> {
35    w: &'a mut W,
36}
37impl<'a> CTSINV_W<'a> {
38    #[doc = r"Sets the field bit"]
39    #[inline(always)]
40    pub fn set_bit(self) -> &'a mut W { self.bit(true) }
41    #[doc = r"Clears the field bit"]
42    #[inline(always)]
43    pub fn clear_bit(self) -> &'a mut W { self.bit(false) }
44    #[doc = r"Writes raw bits to the field"]
45    #[inline(always)]
46    pub fn bit(self, value: bool) -> &'a mut W {
47        self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
48        self.w
49    }
50}
51#[doc = "Reader of field `CTSEN`"]
52pub type CTSEN_R = crate::R<bool, bool>;
53#[doc = "Write proxy for field `CTSEN`"]
54pub struct CTSEN_W<'a> {
55    w: &'a mut W,
56}
57impl<'a> CTSEN_W<'a> {
58    #[doc = r"Sets the field bit"]
59    #[inline(always)]
60    pub fn set_bit(self) -> &'a mut W { self.bit(true) }
61    #[doc = r"Clears the field bit"]
62    #[inline(always)]
63    pub fn clear_bit(self) -> &'a mut W { self.bit(false) }
64    #[doc = r"Writes raw bits to the field"]
65    #[inline(always)]
66    pub fn bit(self, value: bool) -> &'a mut W {
67        self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
68        self.w
69    }
70}
71#[doc = "Reader of field `RTSINV`"]
72pub type RTSINV_R = crate::R<bool, bool>;
73#[doc = "Write proxy for field `RTSINV`"]
74pub struct RTSINV_W<'a> {
75    w: &'a mut W,
76}
77impl<'a> RTSINV_W<'a> {
78    #[doc = r"Sets the field bit"]
79    #[inline(always)]
80    pub fn set_bit(self) -> &'a mut W { self.bit(true) }
81    #[doc = r"Clears the field bit"]
82    #[inline(always)]
83    pub fn clear_bit(self) -> &'a mut W { self.bit(false) }
84    #[doc = r"Writes raw bits to the field"]
85    #[inline(always)]
86    pub fn bit(self, value: bool) -> &'a mut W {
87        self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
88        self.w
89    }
90}
91impl R {
92    #[doc = "Bit 0 - Debug Halt"]
93    #[inline(always)]
94    pub fn dbghalt(&self) -> DBGHALT_R { DBGHALT_R::new((self.bits & 0x01) != 0) }
95    #[doc = "Bit 1 - CTS Pin Inversion"]
96    #[inline(always)]
97    pub fn ctsinv(&self) -> CTSINV_R { CTSINV_R::new(((self.bits >> 1) & 0x01) != 0) }
98    #[doc = "Bit 2 - CTS Function Enabled"]
99    #[inline(always)]
100    pub fn ctsen(&self) -> CTSEN_R { CTSEN_R::new(((self.bits >> 2) & 0x01) != 0) }
101    #[doc = "Bit 3 - RTS Pin Inversion"]
102    #[inline(always)]
103    pub fn rtsinv(&self) -> RTSINV_R { RTSINV_R::new(((self.bits >> 3) & 0x01) != 0) }
104}
105impl W {
106    #[doc = "Bit 0 - Debug Halt"]
107    #[inline(always)]
108    pub fn dbghalt(&mut self) -> DBGHALT_W { DBGHALT_W { w: self } }
109    #[doc = "Bit 1 - CTS Pin Inversion"]
110    #[inline(always)]
111    pub fn ctsinv(&mut self) -> CTSINV_W { CTSINV_W { w: self } }
112    #[doc = "Bit 2 - CTS Function Enabled"]
113    #[inline(always)]
114    pub fn ctsen(&mut self) -> CTSEN_W { CTSEN_W { w: self } }
115    #[doc = "Bit 3 - RTS Pin Inversion"]
116    #[inline(always)]
117    pub fn rtsinv(&mut self) -> RTSINV_W { RTSINV_W { w: self } }
118}
efm32gg11b/usart0/ctrlx.rs

efm32gg11b/usart0/
ctrlx.rs
