1#[doc = "Reader of register CH21_CTRL"]
2pub type R = crate::R<u32, super::CH21_CTRL>;
3#[doc = "Writer for register CH21_CTRL"]
4pub type W = crate::W<u32, super::CH21_CTRL>;
5#[doc = "Register CH21_CTRL `reset()`'s with value 0"]
6impl crate::ResetValue for super::CH21_CTRL {
7 type Type = u32;
8 #[inline(always)]
9 fn reset_value() -> Self::Type { 0 }
10}
11#[doc = "Reader of field `SIGSEL`"]
12pub type SIGSEL_R = crate::R<u8, u8>;
13#[doc = "Write proxy for field `SIGSEL`"]
14pub struct SIGSEL_W<'a> {
15 w: &'a mut W,
16}
17impl<'a> SIGSEL_W<'a> {
18 #[doc = r"Writes raw bits to the field"]
19 #[inline(always)]
20 pub unsafe fn bits(self, value: u8) -> &'a mut W {
21 self.w.bits = (self.w.bits & !0x07) | ((value as u32) & 0x07);
22 self.w
23 }
24}
25#[doc = "Source Select\n\nValue on reset: 0"]
26#[derive(Clone, Copy, Debug, PartialEq)]
27#[repr(u8)]
28pub enum SOURCESEL_A {
29 #[doc = "0: No source selected"]
30 NONE = 0,
31 #[doc = "1: Peripheral Reflex System"]
32 PRSL = 1,
33 #[doc = "2: Peripheral Reflex System"]
34 PRS = 2,
35 #[doc = "3: Peripheral Reflex System"]
36 PRSH = 3,
37 #[doc = "4: Analog Comparator 0"]
38 ACMP0 = 4,
39 #[doc = "5: Analog Comparator 1"]
40 ACMP1 = 5,
41 #[doc = "6: Analog to Digital Converter 0"]
42 ADC0 = 6,
43 #[doc = "7: Real-Time Counter"]
44 RTC = 7,
45 #[doc = "8: Real-Time Counter and Calendar"]
46 RTCC = 8,
47 #[doc = "9: General purpose Input/Output"]
48 GPIOL = 9,
49 #[doc = "10: General purpose Input/Output"]
50 GPIOH = 10,
51 #[doc = "11: Low Energy Timer 0"]
52 LETIMER0 = 11,
53 #[doc = "12: Low Energy Timer 1"]
54 LETIMER1 = 12,
55 #[doc = "13: Pulse Counter 0"]
56 PCNT0 = 13,
57 #[doc = "14: Pulse Counter 1"]
58 PCNT1 = 14,
59 #[doc = "15: Pulse Counter 2"]
60 PCNT2 = 15,
61 #[doc = "16: CRYOTIMER"]
62 CRYOTIMER = 16,
63 #[doc = "17: Clock Management Unit"]
64 CMU = 17,
65 #[doc = "23: Digital to Analog Converter 0"]
66 VDAC0 = 23,
67 #[doc = "24: Low Energy Sensor Interface"]
68 LESENSEL = 24,
69 #[doc = "25: Low Energy Sensor Interface"]
70 LESENSEH = 25,
71 #[doc = "26: Low Energy Sensor Interface"]
72 LESENSED = 26,
73 #[doc = "27: Low Energy Sensor Interface"]
74 LESENSE = 27,
75 #[doc = "28: Analog Comparator 1"]
76 ACMP2 = 28,
77 #[doc = "29: Analog Comparator 3"]
78 ACMP3 = 29,
79 #[doc = "30: Analog to Digital Converter 0"]
80 ADC1 = 30,
81 #[doc = "48: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
82 USART0 = 48,
83 #[doc = "49: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
84 USART1 = 49,
85 #[doc = "50: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
86 USART2 = 50,
87 #[doc = "51: Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
88 USART3 = 51,
89 #[doc = "52: Universal Synchronous/Asynchronous Receiver/Transmitter 4"]
90 USART4 = 52,
91 #[doc = "53: Universal Synchronous/Asynchronous Receiver/Transmitter 5"]
92 USART5 = 53,
93 #[doc = "54: Universal Asynchronous Receiver/Transmitter 0"]
94 UART0 = 54,
95 #[doc = "55: Universal Asynchronous Receiver/Transmitter 1"]
96 UART1 = 55,
97 #[doc = "60: Timer 0"]
98 TIMER0 = 60,
99 #[doc = "61: Timer 1"]
100 TIMER1 = 61,
101 #[doc = "62: Timer 2"]
102 TIMER2 = 62,
103 #[doc = "64: Universal Serial Bus Interface"]
104 USB = 64,
105 #[doc = "67: `1000011`"]
106 CM4 = 67,
107 #[doc = "80: Timer 3"]
108 TIMER3 = 80,
109 #[doc = "82: Wide Timer 0"]
110 WTIMER0 = 82,
111 #[doc = "83: Wide Timer 0"]
112 WTIMER1 = 83,
113 #[doc = "84: Wide Timer 2"]
114 WTIMER2 = 84,
115 #[doc = "85: Wide Timer 3"]
116 WTIMER3 = 85,
117 #[doc = "98: Timer 4"]
118 TIMER4 = 98,
119 #[doc = "99: Timer 5"]
120 TIMER5 = 99,
121 #[doc = "100: Timer 6"]
122 TIMER6 = 100,
123}
124impl From<SOURCESEL_A> for u8 {
125 #[inline(always)]
126 fn from(variant: SOURCESEL_A) -> Self { variant as _ }
127}
128#[doc = "Reader of field `SOURCESEL`"]
129pub type SOURCESEL_R = crate::R<u8, SOURCESEL_A>;
130impl SOURCESEL_R {
131 #[doc = r"Get enumerated values variant"]
132 #[inline(always)]
133 pub fn variant(&self) -> crate::Variant<u8, SOURCESEL_A> {
134 use crate::Variant::*;
135 match self.bits {
136 0 => Val(SOURCESEL_A::NONE),
137 1 => Val(SOURCESEL_A::PRSL),
138 2 => Val(SOURCESEL_A::PRS),
139 3 => Val(SOURCESEL_A::PRSH),
140 4 => Val(SOURCESEL_A::ACMP0),
141 5 => Val(SOURCESEL_A::ACMP1),
142 6 => Val(SOURCESEL_A::ADC0),
143 7 => Val(SOURCESEL_A::RTC),
144 8 => Val(SOURCESEL_A::RTCC),
145 9 => Val(SOURCESEL_A::GPIOL),
146 10 => Val(SOURCESEL_A::GPIOH),
147 11 => Val(SOURCESEL_A::LETIMER0),
148 12 => Val(SOURCESEL_A::LETIMER1),
149 13 => Val(SOURCESEL_A::PCNT0),
150 14 => Val(SOURCESEL_A::PCNT1),
151 15 => Val(SOURCESEL_A::PCNT2),
152 16 => Val(SOURCESEL_A::CRYOTIMER),
153 17 => Val(SOURCESEL_A::CMU),
154 23 => Val(SOURCESEL_A::VDAC0),
155 24 => Val(SOURCESEL_A::LESENSEL),
156 25 => Val(SOURCESEL_A::LESENSEH),
157 26 => Val(SOURCESEL_A::LESENSED),
158 27 => Val(SOURCESEL_A::LESENSE),
159 28 => Val(SOURCESEL_A::ACMP2),
160 29 => Val(SOURCESEL_A::ACMP3),
161 30 => Val(SOURCESEL_A::ADC1),
162 48 => Val(SOURCESEL_A::USART0),
163 49 => Val(SOURCESEL_A::USART1),
164 50 => Val(SOURCESEL_A::USART2),
165 51 => Val(SOURCESEL_A::USART3),
166 52 => Val(SOURCESEL_A::USART4),
167 53 => Val(SOURCESEL_A::USART5),
168 54 => Val(SOURCESEL_A::UART0),
169 55 => Val(SOURCESEL_A::UART1),
170 60 => Val(SOURCESEL_A::TIMER0),
171 61 => Val(SOURCESEL_A::TIMER1),
172 62 => Val(SOURCESEL_A::TIMER2),
173 64 => Val(SOURCESEL_A::USB),
174 67 => Val(SOURCESEL_A::CM4),
175 80 => Val(SOURCESEL_A::TIMER3),
176 82 => Val(SOURCESEL_A::WTIMER0),
177 83 => Val(SOURCESEL_A::WTIMER1),
178 84 => Val(SOURCESEL_A::WTIMER2),
179 85 => Val(SOURCESEL_A::WTIMER3),
180 98 => Val(SOURCESEL_A::TIMER4),
181 99 => Val(SOURCESEL_A::TIMER5),
182 100 => Val(SOURCESEL_A::TIMER6),
183 i => Res(i),
184 }
185 }
186 #[doc = "Checks if the value of the field is `NONE`"]
187 #[inline(always)]
188 pub fn is_none(&self) -> bool { *self == SOURCESEL_A::NONE }
189 #[doc = "Checks if the value of the field is `PRSL`"]
190 #[inline(always)]
191 pub fn is_prsl(&self) -> bool { *self == SOURCESEL_A::PRSL }
192 #[doc = "Checks if the value of the field is `PRS`"]
193 #[inline(always)]
194 pub fn is_prs(&self) -> bool { *self == SOURCESEL_A::PRS }
195 #[doc = "Checks if the value of the field is `PRSH`"]
196 #[inline(always)]
197 pub fn is_prsh(&self) -> bool { *self == SOURCESEL_A::PRSH }
198 #[doc = "Checks if the value of the field is `ACMP0`"]
199 #[inline(always)]
200 pub fn is_acmp0(&self) -> bool { *self == SOURCESEL_A::ACMP0 }
201 #[doc = "Checks if the value of the field is `ACMP1`"]
202 #[inline(always)]
203 pub fn is_acmp1(&self) -> bool { *self == SOURCESEL_A::ACMP1 }
204 #[doc = "Checks if the value of the field is `ADC0`"]
205 #[inline(always)]
206 pub fn is_adc0(&self) -> bool { *self == SOURCESEL_A::ADC0 }
207 #[doc = "Checks if the value of the field is `RTC`"]
208 #[inline(always)]
209 pub fn is_rtc(&self) -> bool { *self == SOURCESEL_A::RTC }
210 #[doc = "Checks if the value of the field is `RTCC`"]
211 #[inline(always)]
212 pub fn is_rtcc(&self) -> bool { *self == SOURCESEL_A::RTCC }
213 #[doc = "Checks if the value of the field is `GPIOL`"]
214 #[inline(always)]
215 pub fn is_gpiol(&self) -> bool { *self == SOURCESEL_A::GPIOL }
216 #[doc = "Checks if the value of the field is `GPIOH`"]
217 #[inline(always)]
218 pub fn is_gpioh(&self) -> bool { *self == SOURCESEL_A::GPIOH }
219 #[doc = "Checks if the value of the field is `LETIMER0`"]
220 #[inline(always)]
221 pub fn is_letimer0(&self) -> bool { *self == SOURCESEL_A::LETIMER0 }
222 #[doc = "Checks if the value of the field is `LETIMER1`"]
223 #[inline(always)]
224 pub fn is_letimer1(&self) -> bool { *self == SOURCESEL_A::LETIMER1 }
225 #[doc = "Checks if the value of the field is `PCNT0`"]
226 #[inline(always)]
227 pub fn is_pcnt0(&self) -> bool { *self == SOURCESEL_A::PCNT0 }
228 #[doc = "Checks if the value of the field is `PCNT1`"]
229 #[inline(always)]
230 pub fn is_pcnt1(&self) -> bool { *self == SOURCESEL_A::PCNT1 }
231 #[doc = "Checks if the value of the field is `PCNT2`"]
232 #[inline(always)]
233 pub fn is_pcnt2(&self) -> bool { *self == SOURCESEL_A::PCNT2 }
234 #[doc = "Checks if the value of the field is `CRYOTIMER`"]
235 #[inline(always)]
236 pub fn is_cryotimer(&self) -> bool { *self == SOURCESEL_A::CRYOTIMER }
237 #[doc = "Checks if the value of the field is `CMU`"]
238 #[inline(always)]
239 pub fn is_cmu(&self) -> bool { *self == SOURCESEL_A::CMU }
240 #[doc = "Checks if the value of the field is `VDAC0`"]
241 #[inline(always)]
242 pub fn is_vdac0(&self) -> bool { *self == SOURCESEL_A::VDAC0 }
243 #[doc = "Checks if the value of the field is `LESENSEL`"]
244 #[inline(always)]
245 pub fn is_lesensel(&self) -> bool { *self == SOURCESEL_A::LESENSEL }
246 #[doc = "Checks if the value of the field is `LESENSEH`"]
247 #[inline(always)]
248 pub fn is_lesenseh(&self) -> bool { *self == SOURCESEL_A::LESENSEH }
249 #[doc = "Checks if the value of the field is `LESENSED`"]
250 #[inline(always)]
251 pub fn is_lesensed(&self) -> bool { *self == SOURCESEL_A::LESENSED }
252 #[doc = "Checks if the value of the field is `LESENSE`"]
253 #[inline(always)]
254 pub fn is_lesense(&self) -> bool { *self == SOURCESEL_A::LESENSE }
255 #[doc = "Checks if the value of the field is `ACMP2`"]
256 #[inline(always)]
257 pub fn is_acmp2(&self) -> bool { *self == SOURCESEL_A::ACMP2 }
258 #[doc = "Checks if the value of the field is `ACMP3`"]
259 #[inline(always)]
260 pub fn is_acmp3(&self) -> bool { *self == SOURCESEL_A::ACMP3 }
261 #[doc = "Checks if the value of the field is `ADC1`"]
262 #[inline(always)]
263 pub fn is_adc1(&self) -> bool { *self == SOURCESEL_A::ADC1 }
264 #[doc = "Checks if the value of the field is `USART0`"]
265 #[inline(always)]
266 pub fn is_usart0(&self) -> bool { *self == SOURCESEL_A::USART0 }
267 #[doc = "Checks if the value of the field is `USART1`"]
268 #[inline(always)]
269 pub fn is_usart1(&self) -> bool { *self == SOURCESEL_A::USART1 }
270 #[doc = "Checks if the value of the field is `USART2`"]
271 #[inline(always)]
272 pub fn is_usart2(&self) -> bool { *self == SOURCESEL_A::USART2 }
273 #[doc = "Checks if the value of the field is `USART3`"]
274 #[inline(always)]
275 pub fn is_usart3(&self) -> bool { *self == SOURCESEL_A::USART3 }
276 #[doc = "Checks if the value of the field is `USART4`"]
277 #[inline(always)]
278 pub fn is_usart4(&self) -> bool { *self == SOURCESEL_A::USART4 }
279 #[doc = "Checks if the value of the field is `USART5`"]
280 #[inline(always)]
281 pub fn is_usart5(&self) -> bool { *self == SOURCESEL_A::USART5 }
282 #[doc = "Checks if the value of the field is `UART0`"]
283 #[inline(always)]
284 pub fn is_uart0(&self) -> bool { *self == SOURCESEL_A::UART0 }
285 #[doc = "Checks if the value of the field is `UART1`"]
286 #[inline(always)]
287 pub fn is_uart1(&self) -> bool { *self == SOURCESEL_A::UART1 }
288 #[doc = "Checks if the value of the field is `TIMER0`"]
289 #[inline(always)]
290 pub fn is_timer0(&self) -> bool { *self == SOURCESEL_A::TIMER0 }
291 #[doc = "Checks if the value of the field is `TIMER1`"]
292 #[inline(always)]
293 pub fn is_timer1(&self) -> bool { *self == SOURCESEL_A::TIMER1 }
294 #[doc = "Checks if the value of the field is `TIMER2`"]
295 #[inline(always)]
296 pub fn is_timer2(&self) -> bool { *self == SOURCESEL_A::TIMER2 }
297 #[doc = "Checks if the value of the field is `USB`"]
298 #[inline(always)]
299 pub fn is_usb(&self) -> bool { *self == SOURCESEL_A::USB }
300 #[doc = "Checks if the value of the field is `CM4`"]
301 #[inline(always)]
302 pub fn is_cm4(&self) -> bool { *self == SOURCESEL_A::CM4 }
303 #[doc = "Checks if the value of the field is `TIMER3`"]
304 #[inline(always)]
305 pub fn is_timer3(&self) -> bool { *self == SOURCESEL_A::TIMER3 }
306 #[doc = "Checks if the value of the field is `WTIMER0`"]
307 #[inline(always)]
308 pub fn is_wtimer0(&self) -> bool { *self == SOURCESEL_A::WTIMER0 }
309 #[doc = "Checks if the value of the field is `WTIMER1`"]
310 #[inline(always)]
311 pub fn is_wtimer1(&self) -> bool { *self == SOURCESEL_A::WTIMER1 }
312 #[doc = "Checks if the value of the field is `WTIMER2`"]
313 #[inline(always)]
314 pub fn is_wtimer2(&self) -> bool { *self == SOURCESEL_A::WTIMER2 }
315 #[doc = "Checks if the value of the field is `WTIMER3`"]
316 #[inline(always)]
317 pub fn is_wtimer3(&self) -> bool { *self == SOURCESEL_A::WTIMER3 }
318 #[doc = "Checks if the value of the field is `TIMER4`"]
319 #[inline(always)]
320 pub fn is_timer4(&self) -> bool { *self == SOURCESEL_A::TIMER4 }
321 #[doc = "Checks if the value of the field is `TIMER5`"]
322 #[inline(always)]
323 pub fn is_timer5(&self) -> bool { *self == SOURCESEL_A::TIMER5 }
324 #[doc = "Checks if the value of the field is `TIMER6`"]
325 #[inline(always)]
326 pub fn is_timer6(&self) -> bool { *self == SOURCESEL_A::TIMER6 }
327}
328#[doc = "Write proxy for field `SOURCESEL`"]
329pub struct SOURCESEL_W<'a> {
330 w: &'a mut W,
331}
332impl<'a> SOURCESEL_W<'a> {
333 #[doc = r"Writes `variant` to the field"]
334 #[inline(always)]
335 pub fn variant(self, variant: SOURCESEL_A) -> &'a mut W { unsafe { self.bits(variant.into()) } }
336 #[doc = "No source selected"]
337 #[inline(always)]
338 pub fn none(self) -> &'a mut W { self.variant(SOURCESEL_A::NONE) }
339 #[doc = "Peripheral Reflex System"]
340 #[inline(always)]
341 pub fn prsl(self) -> &'a mut W { self.variant(SOURCESEL_A::PRSL) }
342 #[doc = "Peripheral Reflex System"]
343 #[inline(always)]
344 pub fn prs(self) -> &'a mut W { self.variant(SOURCESEL_A::PRS) }
345 #[doc = "Peripheral Reflex System"]
346 #[inline(always)]
347 pub fn prsh(self) -> &'a mut W { self.variant(SOURCESEL_A::PRSH) }
348 #[doc = "Analog Comparator 0"]
349 #[inline(always)]
350 pub fn acmp0(self) -> &'a mut W { self.variant(SOURCESEL_A::ACMP0) }
351 #[doc = "Analog Comparator 1"]
352 #[inline(always)]
353 pub fn acmp1(self) -> &'a mut W { self.variant(SOURCESEL_A::ACMP1) }
354 #[doc = "Analog to Digital Converter 0"]
355 #[inline(always)]
356 pub fn adc0(self) -> &'a mut W { self.variant(SOURCESEL_A::ADC0) }
357 #[doc = "Real-Time Counter"]
358 #[inline(always)]
359 pub fn rtc(self) -> &'a mut W { self.variant(SOURCESEL_A::RTC) }
360 #[doc = "Real-Time Counter and Calendar"]
361 #[inline(always)]
362 pub fn rtcc(self) -> &'a mut W { self.variant(SOURCESEL_A::RTCC) }
363 #[doc = "General purpose Input/Output"]
364 #[inline(always)]
365 pub fn gpiol(self) -> &'a mut W { self.variant(SOURCESEL_A::GPIOL) }
366 #[doc = "General purpose Input/Output"]
367 #[inline(always)]
368 pub fn gpioh(self) -> &'a mut W { self.variant(SOURCESEL_A::GPIOH) }
369 #[doc = "Low Energy Timer 0"]
370 #[inline(always)]
371 pub fn letimer0(self) -> &'a mut W { self.variant(SOURCESEL_A::LETIMER0) }
372 #[doc = "Low Energy Timer 1"]
373 #[inline(always)]
374 pub fn letimer1(self) -> &'a mut W { self.variant(SOURCESEL_A::LETIMER1) }
375 #[doc = "Pulse Counter 0"]
376 #[inline(always)]
377 pub fn pcnt0(self) -> &'a mut W { self.variant(SOURCESEL_A::PCNT0) }
378 #[doc = "Pulse Counter 1"]
379 #[inline(always)]
380 pub fn pcnt1(self) -> &'a mut W { self.variant(SOURCESEL_A::PCNT1) }
381 #[doc = "Pulse Counter 2"]
382 #[inline(always)]
383 pub fn pcnt2(self) -> &'a mut W { self.variant(SOURCESEL_A::PCNT2) }
384 #[doc = "CRYOTIMER"]
385 #[inline(always)]
386 pub fn cryotimer(self) -> &'a mut W { self.variant(SOURCESEL_A::CRYOTIMER) }
387 #[doc = "Clock Management Unit"]
388 #[inline(always)]
389 pub fn cmu(self) -> &'a mut W { self.variant(SOURCESEL_A::CMU) }
390 #[doc = "Digital to Analog Converter 0"]
391 #[inline(always)]
392 pub fn vdac0(self) -> &'a mut W { self.variant(SOURCESEL_A::VDAC0) }
393 #[doc = "Low Energy Sensor Interface"]
394 #[inline(always)]
395 pub fn lesensel(self) -> &'a mut W { self.variant(SOURCESEL_A::LESENSEL) }
396 #[doc = "Low Energy Sensor Interface"]
397 #[inline(always)]
398 pub fn lesenseh(self) -> &'a mut W { self.variant(SOURCESEL_A::LESENSEH) }
399 #[doc = "Low Energy Sensor Interface"]
400 #[inline(always)]
401 pub fn lesensed(self) -> &'a mut W { self.variant(SOURCESEL_A::LESENSED) }
402 #[doc = "Low Energy Sensor Interface"]
403 #[inline(always)]
404 pub fn lesense(self) -> &'a mut W { self.variant(SOURCESEL_A::LESENSE) }
405 #[doc = "Analog Comparator 1"]
406 #[inline(always)]
407 pub fn acmp2(self) -> &'a mut W { self.variant(SOURCESEL_A::ACMP2) }
408 #[doc = "Analog Comparator 3"]
409 #[inline(always)]
410 pub fn acmp3(self) -> &'a mut W { self.variant(SOURCESEL_A::ACMP3) }
411 #[doc = "Analog to Digital Converter 0"]
412 #[inline(always)]
413 pub fn adc1(self) -> &'a mut W { self.variant(SOURCESEL_A::ADC1) }
414 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
415 #[inline(always)]
416 pub fn usart0(self) -> &'a mut W { self.variant(SOURCESEL_A::USART0) }
417 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
418 #[inline(always)]
419 pub fn usart1(self) -> &'a mut W { self.variant(SOURCESEL_A::USART1) }
420 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
421 #[inline(always)]
422 pub fn usart2(self) -> &'a mut W { self.variant(SOURCESEL_A::USART2) }
423 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 3"]
424 #[inline(always)]
425 pub fn usart3(self) -> &'a mut W { self.variant(SOURCESEL_A::USART3) }
426 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 4"]
427 #[inline(always)]
428 pub fn usart4(self) -> &'a mut W { self.variant(SOURCESEL_A::USART4) }
429 #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 5"]
430 #[inline(always)]
431 pub fn usart5(self) -> &'a mut W { self.variant(SOURCESEL_A::USART5) }
432 #[doc = "Universal Asynchronous Receiver/Transmitter 0"]
433 #[inline(always)]
434 pub fn uart0(self) -> &'a mut W { self.variant(SOURCESEL_A::UART0) }
435 #[doc = "Universal Asynchronous Receiver/Transmitter 1"]
436 #[inline(always)]
437 pub fn uart1(self) -> &'a mut W { self.variant(SOURCESEL_A::UART1) }
438 #[doc = "Timer 0"]
439 #[inline(always)]
440 pub fn timer0(self) -> &'a mut W { self.variant(SOURCESEL_A::TIMER0) }
441 #[doc = "Timer 1"]
442 #[inline(always)]
443 pub fn timer1(self) -> &'a mut W { self.variant(SOURCESEL_A::TIMER1) }
444 #[doc = "Timer 2"]
445 #[inline(always)]
446 pub fn timer2(self) -> &'a mut W { self.variant(SOURCESEL_A::TIMER2) }
447 #[doc = "Universal Serial Bus Interface"]
448 #[inline(always)]
449 pub fn usb(self) -> &'a mut W { self.variant(SOURCESEL_A::USB) }
450 #[doc = "`1000011`"]
451 #[inline(always)]
452 pub fn cm4(self) -> &'a mut W { self.variant(SOURCESEL_A::CM4) }
453 #[doc = "Timer 3"]
454 #[inline(always)]
455 pub fn timer3(self) -> &'a mut W { self.variant(SOURCESEL_A::TIMER3) }
456 #[doc = "Wide Timer 0"]
457 #[inline(always)]
458 pub fn wtimer0(self) -> &'a mut W { self.variant(SOURCESEL_A::WTIMER0) }
459 #[doc = "Wide Timer 0"]
460 #[inline(always)]
461 pub fn wtimer1(self) -> &'a mut W { self.variant(SOURCESEL_A::WTIMER1) }
462 #[doc = "Wide Timer 2"]
463 #[inline(always)]
464 pub fn wtimer2(self) -> &'a mut W { self.variant(SOURCESEL_A::WTIMER2) }
465 #[doc = "Wide Timer 3"]
466 #[inline(always)]
467 pub fn wtimer3(self) -> &'a mut W { self.variant(SOURCESEL_A::WTIMER3) }
468 #[doc = "Timer 4"]
469 #[inline(always)]
470 pub fn timer4(self) -> &'a mut W { self.variant(SOURCESEL_A::TIMER4) }
471 #[doc = "Timer 5"]
472 #[inline(always)]
473 pub fn timer5(self) -> &'a mut W { self.variant(SOURCESEL_A::TIMER5) }
474 #[doc = "Timer 6"]
475 #[inline(always)]
476 pub fn timer6(self) -> &'a mut W { self.variant(SOURCESEL_A::TIMER6) }
477 #[doc = r"Writes raw bits to the field"]
478 #[inline(always)]
479 pub unsafe fn bits(self, value: u8) -> &'a mut W {
480 self.w.bits = (self.w.bits & !(0x7f << 8)) | (((value as u32) & 0x7f) << 8);
481 self.w
482 }
483}
484#[doc = "Edge Detect Select\n\nValue on reset: 0"]
485#[derive(Clone, Copy, Debug, PartialEq)]
486#[repr(u8)]
487pub enum EDSEL_A {
488 #[doc = "0: Signal is left as it is"]
489 OFF = 0,
490 #[doc = "1: A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
491 POSEDGE = 1,
492 #[doc = "2: A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
493 NEGEDGE = 2,
494 #[doc = "3: A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
495 BOTHEDGES = 3,
496}
497impl From<EDSEL_A> for u8 {
498 #[inline(always)]
499 fn from(variant: EDSEL_A) -> Self { variant as _ }
500}
501#[doc = "Reader of field `EDSEL`"]
502pub type EDSEL_R = crate::R<u8, EDSEL_A>;
503impl EDSEL_R {
504 #[doc = r"Get enumerated values variant"]
505 #[inline(always)]
506 pub fn variant(&self) -> EDSEL_A {
507 match self.bits {
508 0 => EDSEL_A::OFF,
509 1 => EDSEL_A::POSEDGE,
510 2 => EDSEL_A::NEGEDGE,
511 3 => EDSEL_A::BOTHEDGES,
512 _ => unreachable!(),
513 }
514 }
515 #[doc = "Checks if the value of the field is `OFF`"]
516 #[inline(always)]
517 pub fn is_off(&self) -> bool { *self == EDSEL_A::OFF }
518 #[doc = "Checks if the value of the field is `POSEDGE`"]
519 #[inline(always)]
520 pub fn is_posedge(&self) -> bool { *self == EDSEL_A::POSEDGE }
521 #[doc = "Checks if the value of the field is `NEGEDGE`"]
522 #[inline(always)]
523 pub fn is_negedge(&self) -> bool { *self == EDSEL_A::NEGEDGE }
524 #[doc = "Checks if the value of the field is `BOTHEDGES`"]
525 #[inline(always)]
526 pub fn is_bothedges(&self) -> bool { *self == EDSEL_A::BOTHEDGES }
527}
528#[doc = "Write proxy for field `EDSEL`"]
529pub struct EDSEL_W<'a> {
530 w: &'a mut W,
531}
532impl<'a> EDSEL_W<'a> {
533 #[doc = r"Writes `variant` to the field"]
534 #[inline(always)]
535 pub fn variant(self, variant: EDSEL_A) -> &'a mut W {
536 {
537 self.bits(variant.into())
538 }
539 }
540 #[doc = "Signal is left as it is"]
541 #[inline(always)]
542 pub fn off(self) -> &'a mut W { self.variant(EDSEL_A::OFF) }
543 #[doc = "A one HFCLK cycle pulse is generated for every positive edge of the incoming signal"]
544 #[inline(always)]
545 pub fn posedge(self) -> &'a mut W { self.variant(EDSEL_A::POSEDGE) }
546 #[doc = "A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
547 #[inline(always)]
548 pub fn negedge(self) -> &'a mut W { self.variant(EDSEL_A::NEGEDGE) }
549 #[doc = "A one HFCLK clock cycle pulse is generated for every edge of the incoming signal"]
550 #[inline(always)]
551 pub fn bothedges(self) -> &'a mut W { self.variant(EDSEL_A::BOTHEDGES) }
552 #[doc = r"Writes raw bits to the field"]
553 #[inline(always)]
554 pub fn bits(self, value: u8) -> &'a mut W {
555 self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
556 self.w
557 }
558}
559#[doc = "Reader of field `STRETCH`"]
560pub type STRETCH_R = crate::R<bool, bool>;
561#[doc = "Write proxy for field `STRETCH`"]
562pub struct STRETCH_W<'a> {
563 w: &'a mut W,
564}
565impl<'a> STRETCH_W<'a> {
566 #[doc = r"Sets the field bit"]
567 #[inline(always)]
568 pub fn set_bit(self) -> &'a mut W { self.bit(true) }
569 #[doc = r"Clears the field bit"]
570 #[inline(always)]
571 pub fn clear_bit(self) -> &'a mut W { self.bit(false) }
572 #[doc = r"Writes raw bits to the field"]
573 #[inline(always)]
574 pub fn bit(self, value: bool) -> &'a mut W {
575 self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
576 self.w
577 }
578}
579#[doc = "Reader of field `INV`"]
580pub type INV_R = crate::R<bool, bool>;
581#[doc = "Write proxy for field `INV`"]
582pub struct INV_W<'a> {
583 w: &'a mut W,
584}
585impl<'a> INV_W<'a> {
586 #[doc = r"Sets the field bit"]
587 #[inline(always)]
588 pub fn set_bit(self) -> &'a mut W { self.bit(true) }
589 #[doc = r"Clears the field bit"]
590 #[inline(always)]
591 pub fn clear_bit(self) -> &'a mut W { self.bit(false) }
592 #[doc = r"Writes raw bits to the field"]
593 #[inline(always)]
594 pub fn bit(self, value: bool) -> &'a mut W {
595 self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
596 self.w
597 }
598}
599#[doc = "Reader of field `ORPREV`"]
600pub type ORPREV_R = crate::R<bool, bool>;
601#[doc = "Write proxy for field `ORPREV`"]
602pub struct ORPREV_W<'a> {
603 w: &'a mut W,
604}
605impl<'a> ORPREV_W<'a> {
606 #[doc = r"Sets the field bit"]
607 #[inline(always)]
608 pub fn set_bit(self) -> &'a mut W { self.bit(true) }
609 #[doc = r"Clears the field bit"]
610 #[inline(always)]
611 pub fn clear_bit(self) -> &'a mut W { self.bit(false) }
612 #[doc = r"Writes raw bits to the field"]
613 #[inline(always)]
614 pub fn bit(self, value: bool) -> &'a mut W {
615 self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
616 self.w
617 }
618}
619#[doc = "Reader of field `ANDNEXT`"]
620pub type ANDNEXT_R = crate::R<bool, bool>;
621#[doc = "Write proxy for field `ANDNEXT`"]
622pub struct ANDNEXT_W<'a> {
623 w: &'a mut W,
624}
625impl<'a> ANDNEXT_W<'a> {
626 #[doc = r"Sets the field bit"]
627 #[inline(always)]
628 pub fn set_bit(self) -> &'a mut W { self.bit(true) }
629 #[doc = r"Clears the field bit"]
630 #[inline(always)]
631 pub fn clear_bit(self) -> &'a mut W { self.bit(false) }
632 #[doc = r"Writes raw bits to the field"]
633 #[inline(always)]
634 pub fn bit(self, value: bool) -> &'a mut W {
635 self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
636 self.w
637 }
638}
639#[doc = "Reader of field `ASYNC`"]
640pub type ASYNC_R = crate::R<bool, bool>;
641#[doc = "Write proxy for field `ASYNC`"]
642pub struct ASYNC_W<'a> {
643 w: &'a mut W,
644}
645impl<'a> ASYNC_W<'a> {
646 #[doc = r"Sets the field bit"]
647 #[inline(always)]
648 pub fn set_bit(self) -> &'a mut W { self.bit(true) }
649 #[doc = r"Clears the field bit"]
650 #[inline(always)]
651 pub fn clear_bit(self) -> &'a mut W { self.bit(false) }
652 #[doc = r"Writes raw bits to the field"]
653 #[inline(always)]
654 pub fn bit(self, value: bool) -> &'a mut W {
655 self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
656 self.w
657 }
658}
659impl R {
660 #[doc = "Bits 0:2 - Signal Select"]
661 #[inline(always)]
662 pub fn sigsel(&self) -> SIGSEL_R { SIGSEL_R::new((self.bits & 0x07) as u8) }
663 #[doc = "Bits 8:14 - Source Select"]
664 #[inline(always)]
665 pub fn sourcesel(&self) -> SOURCESEL_R { SOURCESEL_R::new(((self.bits >> 8) & 0x7f) as u8) }
666 #[doc = "Bits 20:21 - Edge Detect Select"]
667 #[inline(always)]
668 pub fn edsel(&self) -> EDSEL_R { EDSEL_R::new(((self.bits >> 20) & 0x03) as u8) }
669 #[doc = "Bit 25 - Stretch Channel Output"]
670 #[inline(always)]
671 pub fn stretch(&self) -> STRETCH_R { STRETCH_R::new(((self.bits >> 25) & 0x01) != 0) }
672 #[doc = "Bit 26 - Invert Channel"]
673 #[inline(always)]
674 pub fn inv(&self) -> INV_R { INV_R::new(((self.bits >> 26) & 0x01) != 0) }
675 #[doc = "Bit 27 - Or Previous"]
676 #[inline(always)]
677 pub fn orprev(&self) -> ORPREV_R { ORPREV_R::new(((self.bits >> 27) & 0x01) != 0) }
678 #[doc = "Bit 28 - And Next"]
679 #[inline(always)]
680 pub fn andnext(&self) -> ANDNEXT_R { ANDNEXT_R::new(((self.bits >> 28) & 0x01) != 0) }
681 #[doc = "Bit 30 - Asynchronous Reflex"]
682 #[inline(always)]
683 pub fn async_(&self) -> ASYNC_R { ASYNC_R::new(((self.bits >> 30) & 0x01) != 0) }
684}
685impl W {
686 #[doc = "Bits 0:2 - Signal Select"]
687 #[inline(always)]
688 pub fn sigsel(&mut self) -> SIGSEL_W { SIGSEL_W { w: self } }
689 #[doc = "Bits 8:14 - Source Select"]
690 #[inline(always)]
691 pub fn sourcesel(&mut self) -> SOURCESEL_W { SOURCESEL_W { w: self } }
692 #[doc = "Bits 20:21 - Edge Detect Select"]
693 #[inline(always)]
694 pub fn edsel(&mut self) -> EDSEL_W { EDSEL_W { w: self } }
695 #[doc = "Bit 25 - Stretch Channel Output"]
696 #[inline(always)]
697 pub fn stretch(&mut self) -> STRETCH_W { STRETCH_W { w: self } }
698 #[doc = "Bit 26 - Invert Channel"]
699 #[inline(always)]
700 pub fn inv(&mut self) -> INV_W { INV_W { w: self } }
701 #[doc = "Bit 27 - Or Previous"]
702 #[inline(always)]
703 pub fn orprev(&mut self) -> ORPREV_W { ORPREV_W { w: self } }
704 #[doc = "Bit 28 - And Next"]
705 #[inline(always)]
706 pub fn andnext(&mut self) -> ANDNEXT_W { ANDNEXT_W { w: self } }
707 #[doc = "Bit 30 - Asynchronous Reflex"]
708 #[inline(always)]
709 pub fn async_(&mut self) -> ASYNC_W { ASYNC_W { w: self } }
710}