efm32gg11b/cmu/
ushfrcoctrl.rs

1#[doc = "Reader of register USHFRCOCTRL"]
2pub type R = crate::R<u32, super::USHFRCOCTRL>;
3#[doc = "Writer for register USHFRCOCTRL"]
4pub type W = crate::W<u32, super::USHFRCOCTRL>;
5#[doc = "Register USHFRCOCTRL `reset()`'s with value 0xb148_1f7f"]
6impl crate::ResetValue for super::USHFRCOCTRL {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type { 0xb148_1f7f }
10}
11#[doc = "Reader of field `TUNING`"]
12pub type TUNING_R = crate::R<u8, u8>;
13#[doc = "Write proxy for field `TUNING`"]
14pub struct TUNING_W<'a> {
15    w: &'a mut W,
16}
17impl<'a> TUNING_W<'a> {
18    #[doc = r"Writes raw bits to the field"]
19    #[inline(always)]
20    pub unsafe fn bits(self, value: u8) -> &'a mut W {
21        self.w.bits = (self.w.bits & !0x7f) | ((value as u32) & 0x7f);
22        self.w
23    }
24}
25#[doc = "Reader of field `FINETUNING`"]
26pub type FINETUNING_R = crate::R<u8, u8>;
27#[doc = "Write proxy for field `FINETUNING`"]
28pub struct FINETUNING_W<'a> {
29    w: &'a mut W,
30}
31impl<'a> FINETUNING_W<'a> {
32    #[doc = r"Writes raw bits to the field"]
33    #[inline(always)]
34    pub unsafe fn bits(self, value: u8) -> &'a mut W {
35        self.w.bits = (self.w.bits & !(0x3f << 8)) | (((value as u32) & 0x3f) << 8);
36        self.w
37    }
38}
39#[doc = "Reader of field `FREQRANGE`"]
40pub type FREQRANGE_R = crate::R<u8, u8>;
41#[doc = "Write proxy for field `FREQRANGE`"]
42pub struct FREQRANGE_W<'a> {
43    w: &'a mut W,
44}
45impl<'a> FREQRANGE_W<'a> {
46    #[doc = r"Writes raw bits to the field"]
47    #[inline(always)]
48    pub unsafe fn bits(self, value: u8) -> &'a mut W {
49        self.w.bits = (self.w.bits & !(0x1f << 16)) | (((value as u32) & 0x1f) << 16);
50        self.w
51    }
52}
53#[doc = "Reader of field `CMPBIAS`"]
54pub type CMPBIAS_R = crate::R<u8, u8>;
55#[doc = "Write proxy for field `CMPBIAS`"]
56pub struct CMPBIAS_W<'a> {
57    w: &'a mut W,
58}
59impl<'a> CMPBIAS_W<'a> {
60    #[doc = r"Writes raw bits to the field"]
61    #[inline(always)]
62    pub unsafe fn bits(self, value: u8) -> &'a mut W {
63        self.w.bits = (self.w.bits & !(0x07 << 21)) | (((value as u32) & 0x07) << 21);
64        self.w
65    }
66}
67#[doc = "Reader of field `LDOHP`"]
68pub type LDOHP_R = crate::R<bool, bool>;
69#[doc = "Write proxy for field `LDOHP`"]
70pub struct LDOHP_W<'a> {
71    w: &'a mut W,
72}
73impl<'a> LDOHP_W<'a> {
74    #[doc = r"Sets the field bit"]
75    #[inline(always)]
76    pub fn set_bit(self) -> &'a mut W { self.bit(true) }
77    #[doc = r"Clears the field bit"]
78    #[inline(always)]
79    pub fn clear_bit(self) -> &'a mut W { self.bit(false) }
80    #[doc = r"Writes raw bits to the field"]
81    #[inline(always)]
82    pub fn bit(self, value: bool) -> &'a mut W {
83        self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
84        self.w
85    }
86}
87#[doc = "Locally Divide USHFRCO Clock Output\n\nValue on reset: 0"]
88#[derive(Clone, Copy, Debug, PartialEq)]
89#[repr(u8)]
90pub enum CLKDIV_A {
91    #[doc = "0: Divide by 1."]
92    DIV1 = 0,
93    #[doc = "1: Divide by 2."]
94    DIV2 = 1,
95    #[doc = "2: Divide by 4."]
96    DIV4 = 2,
97}
98impl From<CLKDIV_A> for u8 {
99    #[inline(always)]
100    fn from(variant: CLKDIV_A) -> Self { variant as _ }
101}
102#[doc = "Reader of field `CLKDIV`"]
103pub type CLKDIV_R = crate::R<u8, CLKDIV_A>;
104impl CLKDIV_R {
105    #[doc = r"Get enumerated values variant"]
106    #[inline(always)]
107    pub fn variant(&self) -> crate::Variant<u8, CLKDIV_A> {
108        use crate::Variant::*;
109        match self.bits {
110            0 => Val(CLKDIV_A::DIV1),
111            1 => Val(CLKDIV_A::DIV2),
112            2 => Val(CLKDIV_A::DIV4),
113            i => Res(i),
114        }
115    }
116    #[doc = "Checks if the value of the field is `DIV1`"]
117    #[inline(always)]
118    pub fn is_div1(&self) -> bool { *self == CLKDIV_A::DIV1 }
119    #[doc = "Checks if the value of the field is `DIV2`"]
120    #[inline(always)]
121    pub fn is_div2(&self) -> bool { *self == CLKDIV_A::DIV2 }
122    #[doc = "Checks if the value of the field is `DIV4`"]
123    #[inline(always)]
124    pub fn is_div4(&self) -> bool { *self == CLKDIV_A::DIV4 }
125}
126#[doc = "Write proxy for field `CLKDIV`"]
127pub struct CLKDIV_W<'a> {
128    w: &'a mut W,
129}
130impl<'a> CLKDIV_W<'a> {
131    #[doc = r"Writes `variant` to the field"]
132    #[inline(always)]
133    pub fn variant(self, variant: CLKDIV_A) -> &'a mut W { unsafe { self.bits(variant.into()) } }
134    #[doc = "Divide by 1."]
135    #[inline(always)]
136    pub fn div1(self) -> &'a mut W { self.variant(CLKDIV_A::DIV1) }
137    #[doc = "Divide by 2."]
138    #[inline(always)]
139    pub fn div2(self) -> &'a mut W { self.variant(CLKDIV_A::DIV2) }
140    #[doc = "Divide by 4."]
141    #[inline(always)]
142    pub fn div4(self) -> &'a mut W { self.variant(CLKDIV_A::DIV4) }
143    #[doc = r"Writes raw bits to the field"]
144    #[inline(always)]
145    pub unsafe fn bits(self, value: u8) -> &'a mut W {
146        self.w.bits = (self.w.bits & !(0x03 << 25)) | (((value as u32) & 0x03) << 25);
147        self.w
148    }
149}
150#[doc = "Reader of field `FINETUNINGEN`"]
151pub type FINETUNINGEN_R = crate::R<bool, bool>;
152#[doc = "Write proxy for field `FINETUNINGEN`"]
153pub struct FINETUNINGEN_W<'a> {
154    w: &'a mut W,
155}
156impl<'a> FINETUNINGEN_W<'a> {
157    #[doc = r"Sets the field bit"]
158    #[inline(always)]
159    pub fn set_bit(self) -> &'a mut W { self.bit(true) }
160    #[doc = r"Clears the field bit"]
161    #[inline(always)]
162    pub fn clear_bit(self) -> &'a mut W { self.bit(false) }
163    #[doc = r"Writes raw bits to the field"]
164    #[inline(always)]
165    pub fn bit(self, value: bool) -> &'a mut W {
166        self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
167        self.w
168    }
169}
170#[doc = "Reader of field `VREFTC`"]
171pub type VREFTC_R = crate::R<u8, u8>;
172#[doc = "Write proxy for field `VREFTC`"]
173pub struct VREFTC_W<'a> {
174    w: &'a mut W,
175}
176impl<'a> VREFTC_W<'a> {
177    #[doc = r"Writes raw bits to the field"]
178    #[inline(always)]
179    pub unsafe fn bits(self, value: u8) -> &'a mut W {
180        self.w.bits = (self.w.bits & !(0x0f << 28)) | (((value as u32) & 0x0f) << 28);
181        self.w
182    }
183}
184impl R {
185    #[doc = "Bits 0:6 - USHFRCO Tuning Value"]
186    #[inline(always)]
187    pub fn tuning(&self) -> TUNING_R { TUNING_R::new((self.bits & 0x7f) as u8) }
188    #[doc = "Bits 8:13 - USHFRCO Fine Tuning Value"]
189    #[inline(always)]
190    pub fn finetuning(&self) -> FINETUNING_R { FINETUNING_R::new(((self.bits >> 8) & 0x3f) as u8) }
191    #[doc = "Bits 16:20 - USHFRCO Frequency Range"]
192    #[inline(always)]
193    pub fn freqrange(&self) -> FREQRANGE_R { FREQRANGE_R::new(((self.bits >> 16) & 0x1f) as u8) }
194    #[doc = "Bits 21:23 - USHFRCO Comparator Bias Current"]
195    #[inline(always)]
196    pub fn cmpbias(&self) -> CMPBIAS_R { CMPBIAS_R::new(((self.bits >> 21) & 0x07) as u8) }
197    #[doc = "Bit 24 - USHFRCO LDO High Power Mode"]
198    #[inline(always)]
199    pub fn ldohp(&self) -> LDOHP_R { LDOHP_R::new(((self.bits >> 24) & 0x01) != 0) }
200    #[doc = "Bits 25:26 - Locally Divide USHFRCO Clock Output"]
201    #[inline(always)]
202    pub fn clkdiv(&self) -> CLKDIV_R { CLKDIV_R::new(((self.bits >> 25) & 0x03) as u8) }
203    #[doc = "Bit 27 - Enable Reference for Fine Tuning"]
204    #[inline(always)]
205    pub fn finetuningen(&self) -> FINETUNINGEN_R {
206        FINETUNINGEN_R::new(((self.bits >> 27) & 0x01) != 0)
207    }
208    #[doc = "Bits 28:31 - USHFRCO Temperature Coefficient Trim on Comparator Reference"]
209    #[inline(always)]
210    pub fn vreftc(&self) -> VREFTC_R { VREFTC_R::new(((self.bits >> 28) & 0x0f) as u8) }
211}
212impl W {
213    #[doc = "Bits 0:6 - USHFRCO Tuning Value"]
214    #[inline(always)]
215    pub fn tuning(&mut self) -> TUNING_W { TUNING_W { w: self } }
216    #[doc = "Bits 8:13 - USHFRCO Fine Tuning Value"]
217    #[inline(always)]
218    pub fn finetuning(&mut self) -> FINETUNING_W { FINETUNING_W { w: self } }
219    #[doc = "Bits 16:20 - USHFRCO Frequency Range"]
220    #[inline(always)]
221    pub fn freqrange(&mut self) -> FREQRANGE_W { FREQRANGE_W { w: self } }
222    #[doc = "Bits 21:23 - USHFRCO Comparator Bias Current"]
223    #[inline(always)]
224    pub fn cmpbias(&mut self) -> CMPBIAS_W { CMPBIAS_W { w: self } }
225    #[doc = "Bit 24 - USHFRCO LDO High Power Mode"]
226    #[inline(always)]
227    pub fn ldohp(&mut self) -> LDOHP_W { LDOHP_W { w: self } }
228    #[doc = "Bits 25:26 - Locally Divide USHFRCO Clock Output"]
229    #[inline(always)]
230    pub fn clkdiv(&mut self) -> CLKDIV_W { CLKDIV_W { w: self } }
231    #[doc = "Bit 27 - Enable Reference for Fine Tuning"]
232    #[inline(always)]
233    pub fn finetuningen(&mut self) -> FINETUNINGEN_W { FINETUNINGEN_W { w: self } }
234    #[doc = "Bits 28:31 - USHFRCO Temperature Coefficient Trim on Comparator Reference"]
235    #[inline(always)]
236    pub fn vreftc(&mut self) -> VREFTC_W { VREFTC_W { w: self } }
237}