efm32gg11b_pac/efm32gg11b840/qspi0/
devinstrrdconfig.rs

1#[doc = "Register `DEVINSTRRDCONFIG` reader"]
2pub struct R(crate::R<DEVINSTRRDCONFIG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DEVINSTRRDCONFIG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DEVINSTRRDCONFIG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DEVINSTRRDCONFIG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DEVINSTRRDCONFIG` writer"]
17pub struct W(crate::W<DEVINSTRRDCONFIG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DEVINSTRRDCONFIG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DEVINSTRRDCONFIG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DEVINSTRRDCONFIG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `RDOPCODENONXIP` reader - Read Opcode in Non-XIP Mode"]
38pub type RDOPCODENONXIP_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `RDOPCODENONXIP` writer - Read Opcode in Non-XIP Mode"]
40pub type RDOPCODENONXIP_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, DEVINSTRRDCONFIG_SPEC, u8, u8, 8, O>;
42#[doc = "Field `INSTRTYPE` reader - Instruction Type"]
43pub type INSTRTYPE_R = crate::FieldReader<u8, u8>;
44#[doc = "Field `INSTRTYPE` writer - Instruction Type"]
45pub type INSTRTYPE_W<'a, const O: u8> =
46    crate::FieldWriter<'a, u32, DEVINSTRRDCONFIG_SPEC, u8, u8, 2, O>;
47#[doc = "Field `DDREN` reader - DDR Enable"]
48pub type DDREN_R = crate::BitReader<bool>;
49#[doc = "Field `DDREN` writer - DDR Enable"]
50pub type DDREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DEVINSTRRDCONFIG_SPEC, bool, O>;
51#[doc = "Field `ADDRXFERTYPESTDMODE` reader - Address Transfer Type for Standard SPI Modes"]
52pub type ADDRXFERTYPESTDMODE_R = crate::FieldReader<u8, u8>;
53#[doc = "Field `ADDRXFERTYPESTDMODE` writer - Address Transfer Type for Standard SPI Modes"]
54pub type ADDRXFERTYPESTDMODE_W<'a, const O: u8> =
55    crate::FieldWriter<'a, u32, DEVINSTRRDCONFIG_SPEC, u8, u8, 2, O>;
56#[doc = "Field `DATAXFERTYPEEXTMODE` reader - Data Transfer Type for Standard SPI Modes"]
57pub type DATAXFERTYPEEXTMODE_R = crate::FieldReader<u8, u8>;
58#[doc = "Field `DATAXFERTYPEEXTMODE` writer - Data Transfer Type for Standard SPI Modes"]
59pub type DATAXFERTYPEEXTMODE_W<'a, const O: u8> =
60    crate::FieldWriter<'a, u32, DEVINSTRRDCONFIG_SPEC, u8, u8, 2, O>;
61#[doc = "Field `MODEBITENABLE` reader - Mode Bit Enable"]
62pub type MODEBITENABLE_R = crate::BitReader<bool>;
63#[doc = "Field `MODEBITENABLE` writer - Mode Bit Enable"]
64pub type MODEBITENABLE_W<'a, const O: u8> =
65    crate::BitWriter<'a, u32, DEVINSTRRDCONFIG_SPEC, bool, O>;
66#[doc = "Field `DUMMYRDCLKCYCLES` reader - Dummy Read Clock Cycles"]
67pub type DUMMYRDCLKCYCLES_R = crate::FieldReader<u8, u8>;
68#[doc = "Field `DUMMYRDCLKCYCLES` writer - Dummy Read Clock Cycles"]
69pub type DUMMYRDCLKCYCLES_W<'a, const O: u8> =
70    crate::FieldWriter<'a, u32, DEVINSTRRDCONFIG_SPEC, u8, u8, 5, O>;
71impl R {
72    #[doc = "Bits 0:7 - Read Opcode in Non-XIP Mode"]
73    #[inline(always)]
74    pub fn rdopcodenonxip(&self) -> RDOPCODENONXIP_R {
75        RDOPCODENONXIP_R::new((self.bits & 0xff) as u8)
76    }
77    #[doc = "Bits 8:9 - Instruction Type"]
78    #[inline(always)]
79    pub fn instrtype(&self) -> INSTRTYPE_R {
80        INSTRTYPE_R::new(((self.bits >> 8) & 3) as u8)
81    }
82    #[doc = "Bit 10 - DDR Enable"]
83    #[inline(always)]
84    pub fn ddren(&self) -> DDREN_R {
85        DDREN_R::new(((self.bits >> 10) & 1) != 0)
86    }
87    #[doc = "Bits 12:13 - Address Transfer Type for Standard SPI Modes"]
88    #[inline(always)]
89    pub fn addrxfertypestdmode(&self) -> ADDRXFERTYPESTDMODE_R {
90        ADDRXFERTYPESTDMODE_R::new(((self.bits >> 12) & 3) as u8)
91    }
92    #[doc = "Bits 16:17 - Data Transfer Type for Standard SPI Modes"]
93    #[inline(always)]
94    pub fn dataxfertypeextmode(&self) -> DATAXFERTYPEEXTMODE_R {
95        DATAXFERTYPEEXTMODE_R::new(((self.bits >> 16) & 3) as u8)
96    }
97    #[doc = "Bit 20 - Mode Bit Enable"]
98    #[inline(always)]
99    pub fn modebitenable(&self) -> MODEBITENABLE_R {
100        MODEBITENABLE_R::new(((self.bits >> 20) & 1) != 0)
101    }
102    #[doc = "Bits 24:28 - Dummy Read Clock Cycles"]
103    #[inline(always)]
104    pub fn dummyrdclkcycles(&self) -> DUMMYRDCLKCYCLES_R {
105        DUMMYRDCLKCYCLES_R::new(((self.bits >> 24) & 0x1f) as u8)
106    }
107}
108impl W {
109    #[doc = "Bits 0:7 - Read Opcode in Non-XIP Mode"]
110    #[inline(always)]
111    #[must_use]
112    pub fn rdopcodenonxip(&mut self) -> RDOPCODENONXIP_W<0> {
113        RDOPCODENONXIP_W::new(self)
114    }
115    #[doc = "Bits 8:9 - Instruction Type"]
116    #[inline(always)]
117    #[must_use]
118    pub fn instrtype(&mut self) -> INSTRTYPE_W<8> {
119        INSTRTYPE_W::new(self)
120    }
121    #[doc = "Bit 10 - DDR Enable"]
122    #[inline(always)]
123    #[must_use]
124    pub fn ddren(&mut self) -> DDREN_W<10> {
125        DDREN_W::new(self)
126    }
127    #[doc = "Bits 12:13 - Address Transfer Type for Standard SPI Modes"]
128    #[inline(always)]
129    #[must_use]
130    pub fn addrxfertypestdmode(&mut self) -> ADDRXFERTYPESTDMODE_W<12> {
131        ADDRXFERTYPESTDMODE_W::new(self)
132    }
133    #[doc = "Bits 16:17 - Data Transfer Type for Standard SPI Modes"]
134    #[inline(always)]
135    #[must_use]
136    pub fn dataxfertypeextmode(&mut self) -> DATAXFERTYPEEXTMODE_W<16> {
137        DATAXFERTYPEEXTMODE_W::new(self)
138    }
139    #[doc = "Bit 20 - Mode Bit Enable"]
140    #[inline(always)]
141    #[must_use]
142    pub fn modebitenable(&mut self) -> MODEBITENABLE_W<20> {
143        MODEBITENABLE_W::new(self)
144    }
145    #[doc = "Bits 24:28 - Dummy Read Clock Cycles"]
146    #[inline(always)]
147    #[must_use]
148    pub fn dummyrdclkcycles(&mut self) -> DUMMYRDCLKCYCLES_W<24> {
149        DUMMYRDCLKCYCLES_W::new(self)
150    }
151    #[doc = "Writes raw bits to the register."]
152    #[inline(always)]
153    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
154        self.0.bits(bits);
155        self
156    }
157}
158#[doc = "Device Read Instruction Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devinstrrdconfig](index.html) module"]
159pub struct DEVINSTRRDCONFIG_SPEC;
160impl crate::RegisterSpec for DEVINSTRRDCONFIG_SPEC {
161    type Ux = u32;
162}
163#[doc = "`read()` method returns [devinstrrdconfig::R](R) reader structure"]
164impl crate::Readable for DEVINSTRRDCONFIG_SPEC {
165    type Reader = R;
166}
167#[doc = "`write(|w| ..)` method takes [devinstrrdconfig::W](W) writer structure"]
168impl crate::Writable for DEVINSTRRDCONFIG_SPEC {
169    type Writer = W;
170    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
171    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
172}
173#[doc = "`reset()` method sets DEVINSTRRDCONFIG to value 0x03"]
174impl crate::Resettable for DEVINSTRRDCONFIG_SPEC {
175    const RESET_VALUE: Self::Ux = 0x03;
176}
efm32gg11b_pac/efm32gg11b840/qspi0/devinstrrdconfig.rs

efm32gg11b_pac/efm32gg11b840/qspi0/
devinstrrdconfig.rs
