Enum efm32gg11b_pac::efm32gg11b840::msc::readctrl::MODE_A
source · #[repr(u8)]
pub enum MODE_A {
WS0,
WS1,
WS2,
WS3,
}
Expand description
Read Mode
Value on reset: 1
Variants§
WS0
0: Zero wait-states inserted in fetch or read transfers
WS1
1: One wait-state inserted for each fetch or read transfer. See Flash Wait-States table for details
WS2
2: Two wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details
WS3
3: Three wait-states inserted for eatch fetch or read transfer. See Flash Wait-States table for details