pub type EDSEL_W<'a, const O: u8> = FieldWriterSafe<'a, u32, CH7_CTRL_SPEC, u8, EDSEL_A, 2, O>;
Expand description

Field EDSEL writer - Edge Detect Select

Implementations§

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impl<'a, const O: u8> EDSEL_W<'a, O>

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pub fn off(self) -> &'a mut W

Signal is left as it is

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pub fn posedge(self) -> &'a mut W

A one HFCLK cycle pulse is generated for every positive edge of the incoming signal

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pub fn negedge(self) -> &'a mut W

A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal

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pub fn bothedges(self) -> &'a mut W

A one HFCLK clock cycle pulse is generated for every edge of the incoming signal