efm32gg_pac/efm32gg995/usb/
pcgcctl.rs

1#[doc = "Register `PCGCCTL` reader"]
2pub struct R(crate::R<PCGCCTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PCGCCTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PCGCCTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PCGCCTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PCGCCTL` writer"]
17pub struct W(crate::W<PCGCCTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PCGCCTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PCGCCTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PCGCCTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `STOPPCLK` reader - Stop PHY clock"]
38pub type STOPPCLK_R = crate::BitReader<bool>;
39#[doc = "Field `STOPPCLK` writer - Stop PHY clock"]
40pub type STOPPCLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>;
41#[doc = "Field `GATEHCLK` reader - Gate HCLK"]
42pub type GATEHCLK_R = crate::BitReader<bool>;
43#[doc = "Field `GATEHCLK` writer - Gate HCLK"]
44pub type GATEHCLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>;
45#[doc = "Field `PWRCLMP` reader - Power Clamp"]
46pub type PWRCLMP_R = crate::BitReader<bool>;
47#[doc = "Field `PWRCLMP` writer - Power Clamp"]
48pub type PWRCLMP_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>;
49#[doc = "Field `RSTPDWNMODULE` reader - Reset Power-Down Modules"]
50pub type RSTPDWNMODULE_R = crate::BitReader<bool>;
51#[doc = "Field `RSTPDWNMODULE` writer - Reset Power-Down Modules"]
52pub type RSTPDWNMODULE_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCGCCTL_SPEC, bool, O>;
53#[doc = "Field `PHYSLEEP` reader - PHY In Sleep"]
54pub type PHYSLEEP_R = crate::BitReader<bool>;
55#[doc = "Field `RESETAFTERSUSP` reader - Reset after suspend"]
56pub type RESETAFTERSUSP_R = crate::BitReader<bool>;
57impl R {
58    #[doc = "Bit 0 - Stop PHY clock"]
59    #[inline(always)]
60    pub fn stoppclk(&self) -> STOPPCLK_R {
61        STOPPCLK_R::new((self.bits & 1) != 0)
62    }
63    #[doc = "Bit 1 - Gate HCLK"]
64    #[inline(always)]
65    pub fn gatehclk(&self) -> GATEHCLK_R {
66        GATEHCLK_R::new(((self.bits >> 1) & 1) != 0)
67    }
68    #[doc = "Bit 2 - Power Clamp"]
69    #[inline(always)]
70    pub fn pwrclmp(&self) -> PWRCLMP_R {
71        PWRCLMP_R::new(((self.bits >> 2) & 1) != 0)
72    }
73    #[doc = "Bit 3 - Reset Power-Down Modules"]
74    #[inline(always)]
75    pub fn rstpdwnmodule(&self) -> RSTPDWNMODULE_R {
76        RSTPDWNMODULE_R::new(((self.bits >> 3) & 1) != 0)
77    }
78    #[doc = "Bit 6 - PHY In Sleep"]
79    #[inline(always)]
80    pub fn physleep(&self) -> PHYSLEEP_R {
81        PHYSLEEP_R::new(((self.bits >> 6) & 1) != 0)
82    }
83    #[doc = "Bit 8 - Reset after suspend"]
84    #[inline(always)]
85    pub fn resetaftersusp(&self) -> RESETAFTERSUSP_R {
86        RESETAFTERSUSP_R::new(((self.bits >> 8) & 1) != 0)
87    }
88}
89impl W {
90    #[doc = "Bit 0 - Stop PHY clock"]
91    #[inline(always)]
92    #[must_use]
93    pub fn stoppclk(&mut self) -> STOPPCLK_W<0> {
94        STOPPCLK_W::new(self)
95    }
96    #[doc = "Bit 1 - Gate HCLK"]
97    #[inline(always)]
98    #[must_use]
99    pub fn gatehclk(&mut self) -> GATEHCLK_W<1> {
100        GATEHCLK_W::new(self)
101    }
102    #[doc = "Bit 2 - Power Clamp"]
103    #[inline(always)]
104    #[must_use]
105    pub fn pwrclmp(&mut self) -> PWRCLMP_W<2> {
106        PWRCLMP_W::new(self)
107    }
108    #[doc = "Bit 3 - Reset Power-Down Modules"]
109    #[inline(always)]
110    #[must_use]
111    pub fn rstpdwnmodule(&mut self) -> RSTPDWNMODULE_W<3> {
112        RSTPDWNMODULE_W::new(self)
113    }
114    #[doc = "Writes raw bits to the register."]
115    #[inline(always)]
116    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
117        self.0.bits(bits);
118        self
119    }
120}
121#[doc = "Power and Clock Gating Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pcgcctl](index.html) module"]
122pub struct PCGCCTL_SPEC;
123impl crate::RegisterSpec for PCGCCTL_SPEC {
124    type Ux = u32;
125}
126#[doc = "`read()` method returns [pcgcctl::R](R) reader structure"]
127impl crate::Readable for PCGCCTL_SPEC {
128    type Reader = R;
129}
130#[doc = "`write(|w| ..)` method takes [pcgcctl::W](W) writer structure"]
131impl crate::Writable for PCGCCTL_SPEC {
132    type Writer = W;
133    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
134    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
135}
136#[doc = "`reset()` method sets PCGCCTL to value 0"]
137impl crate::Resettable for PCGCCTL_SPEC {
138    const RESET_VALUE: Self::Ux = 0;
139}
efm32gg_pac/efm32gg995/usb/pcgcctl.rs

efm32gg_pac/efm32gg995/usb/
pcgcctl.rs
