efm32gg_pac/efm32gg995/usb/
hprt.rs

1#[doc = "Register `HPRT` reader"]
2pub struct R(crate::R<HPRT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HPRT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HPRT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HPRT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HPRT` writer"]
17pub struct W(crate::W<HPRT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HPRT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HPRT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HPRT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PRTCONNSTS` reader - Port Connect Status"]
38pub type PRTCONNSTS_R = crate::BitReader<bool>;
39#[doc = "Field `PRTCONNDET` reader - Port Connect Detected"]
40pub type PRTCONNDET_R = crate::BitReader<bool>;
41#[doc = "Field `PRTCONNDET` writer - Port Connect Detected"]
42pub type PRTCONNDET_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>;
43#[doc = "Field `PRTENA` reader - Port Enable"]
44pub type PRTENA_R = crate::BitReader<bool>;
45#[doc = "Field `PRTENA` writer - Port Enable"]
46pub type PRTENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>;
47#[doc = "Field `PRTENCHNG` reader - Port Enable/Disable Change"]
48pub type PRTENCHNG_R = crate::BitReader<bool>;
49#[doc = "Field `PRTENCHNG` writer - Port Enable/Disable Change"]
50pub type PRTENCHNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>;
51#[doc = "Field `PRTOVRCURRACT` reader - Port Overcurrent Active"]
52pub type PRTOVRCURRACT_R = crate::BitReader<bool>;
53#[doc = "Field `PRTOVRCURRCHNG` reader - Port Overcurrent Change"]
54pub type PRTOVRCURRCHNG_R = crate::BitReader<bool>;
55#[doc = "Field `PRTOVRCURRCHNG` writer - Port Overcurrent Change"]
56pub type PRTOVRCURRCHNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>;
57#[doc = "Field `PRTRES` reader - Port Resume"]
58pub type PRTRES_R = crate::BitReader<bool>;
59#[doc = "Field `PRTRES` writer - Port Resume"]
60pub type PRTRES_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>;
61#[doc = "Field `PRTSUSP` reader - Port Suspend"]
62pub type PRTSUSP_R = crate::BitReader<bool>;
63#[doc = "Field `PRTSUSP` writer - Port Suspend"]
64pub type PRTSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>;
65#[doc = "Field `PRTRST` reader - Port Reset"]
66pub type PRTRST_R = crate::BitReader<bool>;
67#[doc = "Field `PRTRST` writer - Port Reset"]
68pub type PRTRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>;
69#[doc = "Field `PRTLNSTS` reader - Port Line Status"]
70pub type PRTLNSTS_R = crate::FieldReader<u8, u8>;
71#[doc = "Field `PRTPWR` reader - Port Power"]
72pub type PRTPWR_R = crate::BitReader<bool>;
73#[doc = "Field `PRTPWR` writer - Port Power"]
74pub type PRTPWR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HPRT_SPEC, bool, O>;
75#[doc = "Field `PRTTSTCTL` reader - Port Test Control"]
76pub type PRTTSTCTL_R = crate::FieldReader<u8, PRTTSTCTL_A>;
77#[doc = "Port Test Control\n\nValue on reset: 0"]
78#[derive(Clone, Copy, Debug, PartialEq, Eq)]
79#[repr(u8)]
80pub enum PRTTSTCTL_A {
81    #[doc = "0: Test mode disabled."]
82    DISABLE = 0,
83    #[doc = "1: Test_J mode."]
84    J = 1,
85    #[doc = "2: Test_K mode."]
86    K = 2,
87    #[doc = "3: Test_SE0_NAK mode."]
88    SE0NAK = 3,
89    #[doc = "4: Test_Packet mode."]
90    PACKET = 4,
91    #[doc = "5: Test_Force_Enable."]
92    FORCE = 5,
93}
94impl From<PRTTSTCTL_A> for u8 {
95    #[inline(always)]
96    fn from(variant: PRTTSTCTL_A) -> Self {
97        variant as _
98    }
99}
100impl PRTTSTCTL_R {
101    #[doc = "Get enumerated values variant"]
102    #[inline(always)]
103    pub fn variant(&self) -> Option<PRTTSTCTL_A> {
104        match self.bits {
105            0 => Some(PRTTSTCTL_A::DISABLE),
106            1 => Some(PRTTSTCTL_A::J),
107            2 => Some(PRTTSTCTL_A::K),
108            3 => Some(PRTTSTCTL_A::SE0NAK),
109            4 => Some(PRTTSTCTL_A::PACKET),
110            5 => Some(PRTTSTCTL_A::FORCE),
111            _ => None,
112        }
113    }
114    #[doc = "Checks if the value of the field is `DISABLE`"]
115    #[inline(always)]
116    pub fn is_disable(&self) -> bool {
117        *self == PRTTSTCTL_A::DISABLE
118    }
119    #[doc = "Checks if the value of the field is `J`"]
120    #[inline(always)]
121    pub fn is_j(&self) -> bool {
122        *self == PRTTSTCTL_A::J
123    }
124    #[doc = "Checks if the value of the field is `K`"]
125    #[inline(always)]
126    pub fn is_k(&self) -> bool {
127        *self == PRTTSTCTL_A::K
128    }
129    #[doc = "Checks if the value of the field is `SE0NAK`"]
130    #[inline(always)]
131    pub fn is_se0nak(&self) -> bool {
132        *self == PRTTSTCTL_A::SE0NAK
133    }
134    #[doc = "Checks if the value of the field is `PACKET`"]
135    #[inline(always)]
136    pub fn is_packet(&self) -> bool {
137        *self == PRTTSTCTL_A::PACKET
138    }
139    #[doc = "Checks if the value of the field is `FORCE`"]
140    #[inline(always)]
141    pub fn is_force(&self) -> bool {
142        *self == PRTTSTCTL_A::FORCE
143    }
144}
145#[doc = "Field `PRTTSTCTL` writer - Port Test Control"]
146pub type PRTTSTCTL_W<'a, const O: u8> =
147    crate::FieldWriter<'a, u32, HPRT_SPEC, u8, PRTTSTCTL_A, 4, O>;
148impl<'a, const O: u8> PRTTSTCTL_W<'a, O> {
149    #[doc = "Test mode disabled."]
150    #[inline(always)]
151    pub fn disable(self) -> &'a mut W {
152        self.variant(PRTTSTCTL_A::DISABLE)
153    }
154    #[doc = "Test_J mode."]
155    #[inline(always)]
156    pub fn j(self) -> &'a mut W {
157        self.variant(PRTTSTCTL_A::J)
158    }
159    #[doc = "Test_K mode."]
160    #[inline(always)]
161    pub fn k(self) -> &'a mut W {
162        self.variant(PRTTSTCTL_A::K)
163    }
164    #[doc = "Test_SE0_NAK mode."]
165    #[inline(always)]
166    pub fn se0nak(self) -> &'a mut W {
167        self.variant(PRTTSTCTL_A::SE0NAK)
168    }
169    #[doc = "Test_Packet mode."]
170    #[inline(always)]
171    pub fn packet(self) -> &'a mut W {
172        self.variant(PRTTSTCTL_A::PACKET)
173    }
174    #[doc = "Test_Force_Enable."]
175    #[inline(always)]
176    pub fn force(self) -> &'a mut W {
177        self.variant(PRTTSTCTL_A::FORCE)
178    }
179}
180#[doc = "Field `PRTSPD` reader - Port Speed"]
181pub type PRTSPD_R = crate::FieldReader<u8, PRTSPD_A>;
182#[doc = "Port Speed\n\nValue on reset: 0"]
183#[derive(Clone, Copy, Debug, PartialEq, Eq)]
184#[repr(u8)]
185pub enum PRTSPD_A {
186    #[doc = "0: High speed."]
187    HS = 0,
188    #[doc = "1: Full speed."]
189    FS = 1,
190    #[doc = "2: Low speed."]
191    LS = 2,
192}
193impl From<PRTSPD_A> for u8 {
194    #[inline(always)]
195    fn from(variant: PRTSPD_A) -> Self {
196        variant as _
197    }
198}
199impl PRTSPD_R {
200    #[doc = "Get enumerated values variant"]
201    #[inline(always)]
202    pub fn variant(&self) -> Option<PRTSPD_A> {
203        match self.bits {
204            0 => Some(PRTSPD_A::HS),
205            1 => Some(PRTSPD_A::FS),
206            2 => Some(PRTSPD_A::LS),
207            _ => None,
208        }
209    }
210    #[doc = "Checks if the value of the field is `HS`"]
211    #[inline(always)]
212    pub fn is_hs(&self) -> bool {
213        *self == PRTSPD_A::HS
214    }
215    #[doc = "Checks if the value of the field is `FS`"]
216    #[inline(always)]
217    pub fn is_fs(&self) -> bool {
218        *self == PRTSPD_A::FS
219    }
220    #[doc = "Checks if the value of the field is `LS`"]
221    #[inline(always)]
222    pub fn is_ls(&self) -> bool {
223        *self == PRTSPD_A::LS
224    }
225}
226impl R {
227    #[doc = "Bit 0 - Port Connect Status"]
228    #[inline(always)]
229    pub fn prtconnsts(&self) -> PRTCONNSTS_R {
230        PRTCONNSTS_R::new((self.bits & 1) != 0)
231    }
232    #[doc = "Bit 1 - Port Connect Detected"]
233    #[inline(always)]
234    pub fn prtconndet(&self) -> PRTCONNDET_R {
235        PRTCONNDET_R::new(((self.bits >> 1) & 1) != 0)
236    }
237    #[doc = "Bit 2 - Port Enable"]
238    #[inline(always)]
239    pub fn prtena(&self) -> PRTENA_R {
240        PRTENA_R::new(((self.bits >> 2) & 1) != 0)
241    }
242    #[doc = "Bit 3 - Port Enable/Disable Change"]
243    #[inline(always)]
244    pub fn prtenchng(&self) -> PRTENCHNG_R {
245        PRTENCHNG_R::new(((self.bits >> 3) & 1) != 0)
246    }
247    #[doc = "Bit 4 - Port Overcurrent Active"]
248    #[inline(always)]
249    pub fn prtovrcurract(&self) -> PRTOVRCURRACT_R {
250        PRTOVRCURRACT_R::new(((self.bits >> 4) & 1) != 0)
251    }
252    #[doc = "Bit 5 - Port Overcurrent Change"]
253    #[inline(always)]
254    pub fn prtovrcurrchng(&self) -> PRTOVRCURRCHNG_R {
255        PRTOVRCURRCHNG_R::new(((self.bits >> 5) & 1) != 0)
256    }
257    #[doc = "Bit 6 - Port Resume"]
258    #[inline(always)]
259    pub fn prtres(&self) -> PRTRES_R {
260        PRTRES_R::new(((self.bits >> 6) & 1) != 0)
261    }
262    #[doc = "Bit 7 - Port Suspend"]
263    #[inline(always)]
264    pub fn prtsusp(&self) -> PRTSUSP_R {
265        PRTSUSP_R::new(((self.bits >> 7) & 1) != 0)
266    }
267    #[doc = "Bit 8 - Port Reset"]
268    #[inline(always)]
269    pub fn prtrst(&self) -> PRTRST_R {
270        PRTRST_R::new(((self.bits >> 8) & 1) != 0)
271    }
272    #[doc = "Bits 10:11 - Port Line Status"]
273    #[inline(always)]
274    pub fn prtlnsts(&self) -> PRTLNSTS_R {
275        PRTLNSTS_R::new(((self.bits >> 10) & 3) as u8)
276    }
277    #[doc = "Bit 12 - Port Power"]
278    #[inline(always)]
279    pub fn prtpwr(&self) -> PRTPWR_R {
280        PRTPWR_R::new(((self.bits >> 12) & 1) != 0)
281    }
282    #[doc = "Bits 13:16 - Port Test Control"]
283    #[inline(always)]
284    pub fn prttstctl(&self) -> PRTTSTCTL_R {
285        PRTTSTCTL_R::new(((self.bits >> 13) & 0x0f) as u8)
286    }
287    #[doc = "Bits 17:18 - Port Speed"]
288    #[inline(always)]
289    pub fn prtspd(&self) -> PRTSPD_R {
290        PRTSPD_R::new(((self.bits >> 17) & 3) as u8)
291    }
292}
293impl W {
294    #[doc = "Bit 1 - Port Connect Detected"]
295    #[inline(always)]
296    #[must_use]
297    pub fn prtconndet(&mut self) -> PRTCONNDET_W<1> {
298        PRTCONNDET_W::new(self)
299    }
300    #[doc = "Bit 2 - Port Enable"]
301    #[inline(always)]
302    #[must_use]
303    pub fn prtena(&mut self) -> PRTENA_W<2> {
304        PRTENA_W::new(self)
305    }
306    #[doc = "Bit 3 - Port Enable/Disable Change"]
307    #[inline(always)]
308    #[must_use]
309    pub fn prtenchng(&mut self) -> PRTENCHNG_W<3> {
310        PRTENCHNG_W::new(self)
311    }
312    #[doc = "Bit 5 - Port Overcurrent Change"]
313    #[inline(always)]
314    #[must_use]
315    pub fn prtovrcurrchng(&mut self) -> PRTOVRCURRCHNG_W<5> {
316        PRTOVRCURRCHNG_W::new(self)
317    }
318    #[doc = "Bit 6 - Port Resume"]
319    #[inline(always)]
320    #[must_use]
321    pub fn prtres(&mut self) -> PRTRES_W<6> {
322        PRTRES_W::new(self)
323    }
324    #[doc = "Bit 7 - Port Suspend"]
325    #[inline(always)]
326    #[must_use]
327    pub fn prtsusp(&mut self) -> PRTSUSP_W<7> {
328        PRTSUSP_W::new(self)
329    }
330    #[doc = "Bit 8 - Port Reset"]
331    #[inline(always)]
332    #[must_use]
333    pub fn prtrst(&mut self) -> PRTRST_W<8> {
334        PRTRST_W::new(self)
335    }
336    #[doc = "Bit 12 - Port Power"]
337    #[inline(always)]
338    #[must_use]
339    pub fn prtpwr(&mut self) -> PRTPWR_W<12> {
340        PRTPWR_W::new(self)
341    }
342    #[doc = "Bits 13:16 - Port Test Control"]
343    #[inline(always)]
344    #[must_use]
345    pub fn prttstctl(&mut self) -> PRTTSTCTL_W<13> {
346        PRTTSTCTL_W::new(self)
347    }
348    #[doc = "Writes raw bits to the register."]
349    #[inline(always)]
350    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
351        self.0.bits(bits);
352        self
353    }
354}
355#[doc = "Host Port Control and Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hprt](index.html) module"]
356pub struct HPRT_SPEC;
357impl crate::RegisterSpec for HPRT_SPEC {
358    type Ux = u32;
359}
360#[doc = "`read()` method returns [hprt::R](R) reader structure"]
361impl crate::Readable for HPRT_SPEC {
362    type Reader = R;
363}
364#[doc = "`write(|w| ..)` method takes [hprt::W](W) writer structure"]
365impl crate::Writable for HPRT_SPEC {
366    type Writer = W;
367    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
368    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
369}
370#[doc = "`reset()` method sets HPRT to value 0"]
371impl crate::Resettable for HPRT_SPEC {
372    const RESET_VALUE: Self::Ux = 0;
373}
efm32gg_pac/efm32gg995/usb/hprt.rs

efm32gg_pac/efm32gg995/usb/
hprt.rs
