efm32gg_pac/efm32gg995/usb/
hcfg.rs

1#[doc = "Register `HCFG` reader"]
2pub struct R(crate::R<HCFG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HCFG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HCFG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HCFG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HCFG` writer"]
17pub struct W(crate::W<HCFG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HCFG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HCFG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HCFG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `FSLSPCLKSEL` reader - FS/LS PHY Clock Select"]
38pub type FSLSPCLKSEL_R = crate::FieldReader<u8, FSLSPCLKSEL_A>;
39#[doc = "FS/LS PHY Clock Select\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum FSLSPCLKSEL_A {
43    #[doc = "1: Internal PHY clock is running at 48 MHz (undivided)."]
44    DIV1 = 1,
45    #[doc = "2: Internal PHY clock is running at 6 MHz (48 MHz divided by 8)."]
46    DIV8 = 2,
47}
48impl From<FSLSPCLKSEL_A> for u8 {
49    #[inline(always)]
50    fn from(variant: FSLSPCLKSEL_A) -> Self {
51        variant as _
52    }
53}
54impl FSLSPCLKSEL_R {
55    #[doc = "Get enumerated values variant"]
56    #[inline(always)]
57    pub fn variant(&self) -> Option<FSLSPCLKSEL_A> {
58        match self.bits {
59            1 => Some(FSLSPCLKSEL_A::DIV1),
60            2 => Some(FSLSPCLKSEL_A::DIV8),
61            _ => None,
62        }
63    }
64    #[doc = "Checks if the value of the field is `DIV1`"]
65    #[inline(always)]
66    pub fn is_div1(&self) -> bool {
67        *self == FSLSPCLKSEL_A::DIV1
68    }
69    #[doc = "Checks if the value of the field is `DIV8`"]
70    #[inline(always)]
71    pub fn is_div8(&self) -> bool {
72        *self == FSLSPCLKSEL_A::DIV8
73    }
74}
75#[doc = "Field `FSLSPCLKSEL` writer - FS/LS PHY Clock Select"]
76pub type FSLSPCLKSEL_W<'a, const O: u8> =
77    crate::FieldWriter<'a, u32, HCFG_SPEC, u8, FSLSPCLKSEL_A, 2, O>;
78impl<'a, const O: u8> FSLSPCLKSEL_W<'a, O> {
79    #[doc = "Internal PHY clock is running at 48 MHz (undivided)."]
80    #[inline(always)]
81    pub fn div1(self) -> &'a mut W {
82        self.variant(FSLSPCLKSEL_A::DIV1)
83    }
84    #[doc = "Internal PHY clock is running at 6 MHz (48 MHz divided by 8)."]
85    #[inline(always)]
86    pub fn div8(self) -> &'a mut W {
87        self.variant(FSLSPCLKSEL_A::DIV8)
88    }
89}
90#[doc = "Field `FSLSSUPP` reader - FS- and LS-Only Support"]
91pub type FSLSSUPP_R = crate::BitReader<bool>;
92#[doc = "Field `FSLSSUPP` writer - FS- and LS-Only Support"]
93pub type FSLSSUPP_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCFG_SPEC, bool, O>;
94#[doc = "Field `ENA32KHZS` reader - Enable 32 KHz Suspend mode"]
95pub type ENA32KHZS_R = crate::BitReader<bool>;
96#[doc = "Field `ENA32KHZS` writer - Enable 32 KHz Suspend mode"]
97pub type ENA32KHZS_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCFG_SPEC, bool, O>;
98#[doc = "Field `RESVALID` reader - Resume Validation Period"]
99pub type RESVALID_R = crate::FieldReader<u8, u8>;
100#[doc = "Field `RESVALID` writer - Resume Validation Period"]
101pub type RESVALID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HCFG_SPEC, u8, u8, 8, O>;
102#[doc = "Field `MODECHTIMEN` reader - Mode Change Time"]
103pub type MODECHTIMEN_R = crate::BitReader<bool>;
104#[doc = "Field `MODECHTIMEN` writer - Mode Change Time"]
105pub type MODECHTIMEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, HCFG_SPEC, bool, O>;
106impl R {
107    #[doc = "Bits 0:1 - FS/LS PHY Clock Select"]
108    #[inline(always)]
109    pub fn fslspclksel(&self) -> FSLSPCLKSEL_R {
110        FSLSPCLKSEL_R::new((self.bits & 3) as u8)
111    }
112    #[doc = "Bit 2 - FS- and LS-Only Support"]
113    #[inline(always)]
114    pub fn fslssupp(&self) -> FSLSSUPP_R {
115        FSLSSUPP_R::new(((self.bits >> 2) & 1) != 0)
116    }
117    #[doc = "Bit 7 - Enable 32 KHz Suspend mode"]
118    #[inline(always)]
119    pub fn ena32khzs(&self) -> ENA32KHZS_R {
120        ENA32KHZS_R::new(((self.bits >> 7) & 1) != 0)
121    }
122    #[doc = "Bits 8:15 - Resume Validation Period"]
123    #[inline(always)]
124    pub fn resvalid(&self) -> RESVALID_R {
125        RESVALID_R::new(((self.bits >> 8) & 0xff) as u8)
126    }
127    #[doc = "Bit 31 - Mode Change Time"]
128    #[inline(always)]
129    pub fn modechtimen(&self) -> MODECHTIMEN_R {
130        MODECHTIMEN_R::new(((self.bits >> 31) & 1) != 0)
131    }
132}
133impl W {
134    #[doc = "Bits 0:1 - FS/LS PHY Clock Select"]
135    #[inline(always)]
136    #[must_use]
137    pub fn fslspclksel(&mut self) -> FSLSPCLKSEL_W<0> {
138        FSLSPCLKSEL_W::new(self)
139    }
140    #[doc = "Bit 2 - FS- and LS-Only Support"]
141    #[inline(always)]
142    #[must_use]
143    pub fn fslssupp(&mut self) -> FSLSSUPP_W<2> {
144        FSLSSUPP_W::new(self)
145    }
146    #[doc = "Bit 7 - Enable 32 KHz Suspend mode"]
147    #[inline(always)]
148    #[must_use]
149    pub fn ena32khzs(&mut self) -> ENA32KHZS_W<7> {
150        ENA32KHZS_W::new(self)
151    }
152    #[doc = "Bits 8:15 - Resume Validation Period"]
153    #[inline(always)]
154    #[must_use]
155    pub fn resvalid(&mut self) -> RESVALID_W<8> {
156        RESVALID_W::new(self)
157    }
158    #[doc = "Bit 31 - Mode Change Time"]
159    #[inline(always)]
160    #[must_use]
161    pub fn modechtimen(&mut self) -> MODECHTIMEN_W<31> {
162        MODECHTIMEN_W::new(self)
163    }
164    #[doc = "Writes raw bits to the register."]
165    #[inline(always)]
166    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
167        self.0.bits(bits);
168        self
169    }
170}
171#[doc = "Host Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hcfg](index.html) module"]
172pub struct HCFG_SPEC;
173impl crate::RegisterSpec for HCFG_SPEC {
174    type Ux = u32;
175}
176#[doc = "`read()` method returns [hcfg::R](R) reader structure"]
177impl crate::Readable for HCFG_SPEC {
178    type Reader = R;
179}
180#[doc = "`write(|w| ..)` method takes [hcfg::W](W) writer structure"]
181impl crate::Writable for HCFG_SPEC {
182    type Writer = W;
183    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
184    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
185}
186#[doc = "`reset()` method sets HCFG to value 0x0020_0000"]
187impl crate::Resettable for HCFG_SPEC {
188    const RESET_VALUE: Self::Ux = 0x0020_0000;
189}
efm32gg_pac/efm32gg995/usb/hcfg.rs

efm32gg_pac/efm32gg995/usb/
hcfg.rs
