efm32gg_pac/efm32gg995/usb/
hc6_tsiz.rs

1#[doc = "Register `HC6_TSIZ` reader"]
2pub struct R(crate::R<HC6_TSIZ_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<HC6_TSIZ_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<HC6_TSIZ_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<HC6_TSIZ_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `HC6_TSIZ` writer"]
17pub struct W(crate::W<HC6_TSIZ_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<HC6_TSIZ_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<HC6_TSIZ_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<HC6_TSIZ_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `XFERSIZE` reader - Transfer Size"]
38pub type XFERSIZE_R = crate::FieldReader<u32, u32>;
39#[doc = "Field `XFERSIZE` writer - Transfer Size"]
40pub type XFERSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HC6_TSIZ_SPEC, u32, u32, 19, O>;
41#[doc = "Field `PKTCNT` reader - Packet Count"]
42pub type PKTCNT_R = crate::FieldReader<u16, u16>;
43#[doc = "Field `PKTCNT` writer - Packet Count"]
44pub type PKTCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HC6_TSIZ_SPEC, u16, u16, 10, O>;
45#[doc = "Field `PID` reader - Packet ID"]
46pub type PID_R = crate::FieldReader<u8, PID_A>;
47#[doc = "Packet ID\n\nValue on reset: 0"]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49#[repr(u8)]
50pub enum PID_A {
51    #[doc = "0: DATA0 PID."]
52    DATA0 = 0,
53    #[doc = "1: DATA2 PID."]
54    DATA2 = 1,
55    #[doc = "2: DATA1 PID."]
56    DATA1 = 2,
57    #[doc = "3: MDATA (non-control) / SETUP (control) PID."]
58    MDATA = 3,
59}
60impl From<PID_A> for u8 {
61    #[inline(always)]
62    fn from(variant: PID_A) -> Self {
63        variant as _
64    }
65}
66impl PID_R {
67    #[doc = "Get enumerated values variant"]
68    #[inline(always)]
69    pub fn variant(&self) -> PID_A {
70        match self.bits {
71            0 => PID_A::DATA0,
72            1 => PID_A::DATA2,
73            2 => PID_A::DATA1,
74            3 => PID_A::MDATA,
75            _ => unreachable!(),
76        }
77    }
78    #[doc = "Checks if the value of the field is `DATA0`"]
79    #[inline(always)]
80    pub fn is_data0(&self) -> bool {
81        *self == PID_A::DATA0
82    }
83    #[doc = "Checks if the value of the field is `DATA2`"]
84    #[inline(always)]
85    pub fn is_data2(&self) -> bool {
86        *self == PID_A::DATA2
87    }
88    #[doc = "Checks if the value of the field is `DATA1`"]
89    #[inline(always)]
90    pub fn is_data1(&self) -> bool {
91        *self == PID_A::DATA1
92    }
93    #[doc = "Checks if the value of the field is `MDATA`"]
94    #[inline(always)]
95    pub fn is_mdata(&self) -> bool {
96        *self == PID_A::MDATA
97    }
98}
99#[doc = "Field `PID` writer - Packet ID"]
100pub type PID_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, HC6_TSIZ_SPEC, u8, PID_A, 2, O>;
101impl<'a, const O: u8> PID_W<'a, O> {
102    #[doc = "DATA0 PID."]
103    #[inline(always)]
104    pub fn data0(self) -> &'a mut W {
105        self.variant(PID_A::DATA0)
106    }
107    #[doc = "DATA2 PID."]
108    #[inline(always)]
109    pub fn data2(self) -> &'a mut W {
110        self.variant(PID_A::DATA2)
111    }
112    #[doc = "DATA1 PID."]
113    #[inline(always)]
114    pub fn data1(self) -> &'a mut W {
115        self.variant(PID_A::DATA1)
116    }
117    #[doc = "MDATA (non-control) / SETUP (control) PID."]
118    #[inline(always)]
119    pub fn mdata(self) -> &'a mut W {
120        self.variant(PID_A::MDATA)
121    }
122}
123impl R {
124    #[doc = "Bits 0:18 - Transfer Size"]
125    #[inline(always)]
126    pub fn xfersize(&self) -> XFERSIZE_R {
127        XFERSIZE_R::new(self.bits & 0x0007_ffff)
128    }
129    #[doc = "Bits 19:28 - Packet Count"]
130    #[inline(always)]
131    pub fn pktcnt(&self) -> PKTCNT_R {
132        PKTCNT_R::new(((self.bits >> 19) & 0x03ff) as u16)
133    }
134    #[doc = "Bits 29:30 - Packet ID"]
135    #[inline(always)]
136    pub fn pid(&self) -> PID_R {
137        PID_R::new(((self.bits >> 29) & 3) as u8)
138    }
139}
140impl W {
141    #[doc = "Bits 0:18 - Transfer Size"]
142    #[inline(always)]
143    #[must_use]
144    pub fn xfersize(&mut self) -> XFERSIZE_W<0> {
145        XFERSIZE_W::new(self)
146    }
147    #[doc = "Bits 19:28 - Packet Count"]
148    #[inline(always)]
149    #[must_use]
150    pub fn pktcnt(&mut self) -> PKTCNT_W<19> {
151        PKTCNT_W::new(self)
152    }
153    #[doc = "Bits 29:30 - Packet ID"]
154    #[inline(always)]
155    #[must_use]
156    pub fn pid(&mut self) -> PID_W<29> {
157        PID_W::new(self)
158    }
159    #[doc = "Writes raw bits to the register."]
160    #[inline(always)]
161    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
162        self.0.bits(bits);
163        self
164    }
165}
166#[doc = "Host Channel x Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc6_tsiz](index.html) module"]
167pub struct HC6_TSIZ_SPEC;
168impl crate::RegisterSpec for HC6_TSIZ_SPEC {
169    type Ux = u32;
170}
171#[doc = "`read()` method returns [hc6_tsiz::R](R) reader structure"]
172impl crate::Readable for HC6_TSIZ_SPEC {
173    type Reader = R;
174}
175#[doc = "`write(|w| ..)` method takes [hc6_tsiz::W](W) writer structure"]
176impl crate::Writable for HC6_TSIZ_SPEC {
177    type Writer = W;
178    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
179    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
180}
181#[doc = "`reset()` method sets HC6_TSIZ to value 0"]
182impl crate::Resettable for HC6_TSIZ_SPEC {
183    const RESET_VALUE: Self::Ux = 0;
184}
efm32gg_pac/efm32gg995/usb/hc6_tsiz.rs

efm32gg_pac/efm32gg995/usb/
hc6_tsiz.rs
