efm32gg_pac/efm32gg995/usb/
hc12_int.rs1#[doc = "Register `HC12_INT` reader"]
2pub struct R(crate::R<HC12_INT_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<HC12_INT_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<HC12_INT_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<HC12_INT_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `HC12_INT` writer"]
17pub struct W(crate::W<HC12_INT_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<HC12_INT_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<HC12_INT_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<HC12_INT_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `XFERCOMPL` reader - Transfer Completed"]
38pub type XFERCOMPL_R = crate::BitReader<bool>;
39#[doc = "Field `XFERCOMPL` writer - Transfer Completed"]
40pub type XFERCOMPL_W<'a, const O: u8> = crate::BitWriter<'a, u32, HC12_INT_SPEC, bool, O>;
41#[doc = "Field `CHHLTD` reader - Channel Halted"]
42pub type CHHLTD_R = crate::BitReader<bool>;
43#[doc = "Field `CHHLTD` writer - Channel Halted"]
44pub type CHHLTD_W<'a, const O: u8> = crate::BitWriter<'a, u32, HC12_INT_SPEC, bool, O>;
45#[doc = "Field `AHBERR` reader - AHB Error"]
46pub type AHBERR_R = crate::BitReader<bool>;
47#[doc = "Field `AHBERR` writer - AHB Error"]
48pub type AHBERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HC12_INT_SPEC, bool, O>;
49#[doc = "Field `STALL` reader - STALL Response Received Interrupt"]
50pub type STALL_R = crate::BitReader<bool>;
51#[doc = "Field `STALL` writer - STALL Response Received Interrupt"]
52pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, HC12_INT_SPEC, bool, O>;
53#[doc = "Field `NAK` reader - NAK Response Received Interrupt"]
54pub type NAK_R = crate::BitReader<bool>;
55#[doc = "Field `NAK` writer - NAK Response Received Interrupt"]
56pub type NAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, HC12_INT_SPEC, bool, O>;
57#[doc = "Field `ACK` reader - ACK Response Received/Transmitted Interrupt"]
58pub type ACK_R = crate::BitReader<bool>;
59#[doc = "Field `ACK` writer - ACK Response Received/Transmitted Interrupt"]
60pub type ACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, HC12_INT_SPEC, bool, O>;
61#[doc = "Field `XACTERR` reader - Transaction Error"]
62pub type XACTERR_R = crate::BitReader<bool>;
63#[doc = "Field `XACTERR` writer - Transaction Error"]
64pub type XACTERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HC12_INT_SPEC, bool, O>;
65#[doc = "Field `BBLERR` reader - Babble Error"]
66pub type BBLERR_R = crate::BitReader<bool>;
67#[doc = "Field `BBLERR` writer - Babble Error"]
68pub type BBLERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HC12_INT_SPEC, bool, O>;
69#[doc = "Field `FRMOVRUN` reader - Frame Overrun"]
70pub type FRMOVRUN_R = crate::BitReader<bool>;
71#[doc = "Field `FRMOVRUN` writer - Frame Overrun"]
72pub type FRMOVRUN_W<'a, const O: u8> = crate::BitWriter<'a, u32, HC12_INT_SPEC, bool, O>;
73#[doc = "Field `DATATGLERR` reader - Data Toggle Error"]
74pub type DATATGLERR_R = crate::BitReader<bool>;
75#[doc = "Field `DATATGLERR` writer - Data Toggle Error"]
76pub type DATATGLERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, HC12_INT_SPEC, bool, O>;
77impl R {
78 #[doc = "Bit 0 - Transfer Completed"]
79 #[inline(always)]
80 pub fn xfercompl(&self) -> XFERCOMPL_R {
81 XFERCOMPL_R::new((self.bits & 1) != 0)
82 }
83 #[doc = "Bit 1 - Channel Halted"]
84 #[inline(always)]
85 pub fn chhltd(&self) -> CHHLTD_R {
86 CHHLTD_R::new(((self.bits >> 1) & 1) != 0)
87 }
88 #[doc = "Bit 2 - AHB Error"]
89 #[inline(always)]
90 pub fn ahberr(&self) -> AHBERR_R {
91 AHBERR_R::new(((self.bits >> 2) & 1) != 0)
92 }
93 #[doc = "Bit 3 - STALL Response Received Interrupt"]
94 #[inline(always)]
95 pub fn stall(&self) -> STALL_R {
96 STALL_R::new(((self.bits >> 3) & 1) != 0)
97 }
98 #[doc = "Bit 4 - NAK Response Received Interrupt"]
99 #[inline(always)]
100 pub fn nak(&self) -> NAK_R {
101 NAK_R::new(((self.bits >> 4) & 1) != 0)
102 }
103 #[doc = "Bit 5 - ACK Response Received/Transmitted Interrupt"]
104 #[inline(always)]
105 pub fn ack(&self) -> ACK_R {
106 ACK_R::new(((self.bits >> 5) & 1) != 0)
107 }
108 #[doc = "Bit 7 - Transaction Error"]
109 #[inline(always)]
110 pub fn xacterr(&self) -> XACTERR_R {
111 XACTERR_R::new(((self.bits >> 7) & 1) != 0)
112 }
113 #[doc = "Bit 8 - Babble Error"]
114 #[inline(always)]
115 pub fn bblerr(&self) -> BBLERR_R {
116 BBLERR_R::new(((self.bits >> 8) & 1) != 0)
117 }
118 #[doc = "Bit 9 - Frame Overrun"]
119 #[inline(always)]
120 pub fn frmovrun(&self) -> FRMOVRUN_R {
121 FRMOVRUN_R::new(((self.bits >> 9) & 1) != 0)
122 }
123 #[doc = "Bit 10 - Data Toggle Error"]
124 #[inline(always)]
125 pub fn datatglerr(&self) -> DATATGLERR_R {
126 DATATGLERR_R::new(((self.bits >> 10) & 1) != 0)
127 }
128}
129impl W {
130 #[doc = "Bit 0 - Transfer Completed"]
131 #[inline(always)]
132 #[must_use]
133 pub fn xfercompl(&mut self) -> XFERCOMPL_W<0> {
134 XFERCOMPL_W::new(self)
135 }
136 #[doc = "Bit 1 - Channel Halted"]
137 #[inline(always)]
138 #[must_use]
139 pub fn chhltd(&mut self) -> CHHLTD_W<1> {
140 CHHLTD_W::new(self)
141 }
142 #[doc = "Bit 2 - AHB Error"]
143 #[inline(always)]
144 #[must_use]
145 pub fn ahberr(&mut self) -> AHBERR_W<2> {
146 AHBERR_W::new(self)
147 }
148 #[doc = "Bit 3 - STALL Response Received Interrupt"]
149 #[inline(always)]
150 #[must_use]
151 pub fn stall(&mut self) -> STALL_W<3> {
152 STALL_W::new(self)
153 }
154 #[doc = "Bit 4 - NAK Response Received Interrupt"]
155 #[inline(always)]
156 #[must_use]
157 pub fn nak(&mut self) -> NAK_W<4> {
158 NAK_W::new(self)
159 }
160 #[doc = "Bit 5 - ACK Response Received/Transmitted Interrupt"]
161 #[inline(always)]
162 #[must_use]
163 pub fn ack(&mut self) -> ACK_W<5> {
164 ACK_W::new(self)
165 }
166 #[doc = "Bit 7 - Transaction Error"]
167 #[inline(always)]
168 #[must_use]
169 pub fn xacterr(&mut self) -> XACTERR_W<7> {
170 XACTERR_W::new(self)
171 }
172 #[doc = "Bit 8 - Babble Error"]
173 #[inline(always)]
174 #[must_use]
175 pub fn bblerr(&mut self) -> BBLERR_W<8> {
176 BBLERR_W::new(self)
177 }
178 #[doc = "Bit 9 - Frame Overrun"]
179 #[inline(always)]
180 #[must_use]
181 pub fn frmovrun(&mut self) -> FRMOVRUN_W<9> {
182 FRMOVRUN_W::new(self)
183 }
184 #[doc = "Bit 10 - Data Toggle Error"]
185 #[inline(always)]
186 #[must_use]
187 pub fn datatglerr(&mut self) -> DATATGLERR_W<10> {
188 DATATGLERR_W::new(self)
189 }
190 #[doc = "Writes raw bits to the register."]
191 #[inline(always)]
192 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
193 self.0.bits(bits);
194 self
195 }
196}
197#[doc = "Host Channel x Interrupt Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hc12_int](index.html) module"]
198pub struct HC12_INT_SPEC;
199impl crate::RegisterSpec for HC12_INT_SPEC {
200 type Ux = u32;
201}
202#[doc = "`read()` method returns [hc12_int::R](R) reader structure"]
203impl crate::Readable for HC12_INT_SPEC {
204 type Reader = R;
205}
206#[doc = "`write(|w| ..)` method takes [hc12_int::W](W) writer structure"]
207impl crate::Writable for HC12_INT_SPEC {
208 type Writer = W;
209 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
210 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
211}
212#[doc = "`reset()` method sets HC12_INT to value 0"]
213impl crate::Resettable for HC12_INT_SPEC {
214 const RESET_VALUE: Self::Ux = 0;
215}