efm32gg_pac/efm32gg995/usb/
diep5_ctl.rs

1#[doc = "Register `DIEP5_CTL` reader"]
2pub struct R(crate::R<DIEP5_CTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DIEP5_CTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DIEP5_CTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DIEP5_CTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DIEP5_CTL` writer"]
17pub struct W(crate::W<DIEP5_CTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DIEP5_CTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DIEP5_CTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DIEP5_CTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MPS` reader - Maximum Packet Size"]
38pub type MPS_R = crate::FieldReader<u16, u16>;
39#[doc = "Field `MPS` writer - Maximum Packet Size"]
40pub type MPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEP5_CTL_SPEC, u16, u16, 11, O>;
41#[doc = "Field `USBACTEP` reader - USB Active Endpoint"]
42pub type USBACTEP_R = crate::BitReader<bool>;
43#[doc = "Field `USBACTEP` writer - USB Active Endpoint"]
44pub type USBACTEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEP5_CTL_SPEC, bool, O>;
45#[doc = "Field `DPIDEOF` reader - Endpoint Data PID / Even or Odd Frame"]
46pub type DPIDEOF_R = crate::BitReader<bool>;
47#[doc = "Field `NAKSTS` reader - NAK Status"]
48pub type NAKSTS_R = crate::BitReader<bool>;
49#[doc = "Field `EPTYPE` reader - Endpoint Type"]
50pub type EPTYPE_R = crate::FieldReader<u8, EPTYPE_A>;
51#[doc = "Endpoint Type\n\nValue on reset: 0"]
52#[derive(Clone, Copy, Debug, PartialEq, Eq)]
53#[repr(u8)]
54pub enum EPTYPE_A {
55    #[doc = "0: Control Endpoint."]
56    CONTROL = 0,
57    #[doc = "1: Isochronous Endpoint."]
58    ISO = 1,
59    #[doc = "2: Bulk Endpoint."]
60    BULK = 2,
61    #[doc = "3: Interrupt Endpoint."]
62    INT = 3,
63}
64impl From<EPTYPE_A> for u8 {
65    #[inline(always)]
66    fn from(variant: EPTYPE_A) -> Self {
67        variant as _
68    }
69}
70impl EPTYPE_R {
71    #[doc = "Get enumerated values variant"]
72    #[inline(always)]
73    pub fn variant(&self) -> EPTYPE_A {
74        match self.bits {
75            0 => EPTYPE_A::CONTROL,
76            1 => EPTYPE_A::ISO,
77            2 => EPTYPE_A::BULK,
78            3 => EPTYPE_A::INT,
79            _ => unreachable!(),
80        }
81    }
82    #[doc = "Checks if the value of the field is `CONTROL`"]
83    #[inline(always)]
84    pub fn is_control(&self) -> bool {
85        *self == EPTYPE_A::CONTROL
86    }
87    #[doc = "Checks if the value of the field is `ISO`"]
88    #[inline(always)]
89    pub fn is_iso(&self) -> bool {
90        *self == EPTYPE_A::ISO
91    }
92    #[doc = "Checks if the value of the field is `BULK`"]
93    #[inline(always)]
94    pub fn is_bulk(&self) -> bool {
95        *self == EPTYPE_A::BULK
96    }
97    #[doc = "Checks if the value of the field is `INT`"]
98    #[inline(always)]
99    pub fn is_int(&self) -> bool {
100        *self == EPTYPE_A::INT
101    }
102}
103#[doc = "Field `EPTYPE` writer - Endpoint Type"]
104pub type EPTYPE_W<'a, const O: u8> =
105    crate::FieldWriterSafe<'a, u32, DIEP5_CTL_SPEC, u8, EPTYPE_A, 2, O>;
106impl<'a, const O: u8> EPTYPE_W<'a, O> {
107    #[doc = "Control Endpoint."]
108    #[inline(always)]
109    pub fn control(self) -> &'a mut W {
110        self.variant(EPTYPE_A::CONTROL)
111    }
112    #[doc = "Isochronous Endpoint."]
113    #[inline(always)]
114    pub fn iso(self) -> &'a mut W {
115        self.variant(EPTYPE_A::ISO)
116    }
117    #[doc = "Bulk Endpoint."]
118    #[inline(always)]
119    pub fn bulk(self) -> &'a mut W {
120        self.variant(EPTYPE_A::BULK)
121    }
122    #[doc = "Interrupt Endpoint."]
123    #[inline(always)]
124    pub fn int(self) -> &'a mut W {
125        self.variant(EPTYPE_A::INT)
126    }
127}
128#[doc = "Field `STALL` reader - Handshake"]
129pub type STALL_R = crate::BitReader<bool>;
130#[doc = "Field `STALL` writer - Handshake"]
131pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEP5_CTL_SPEC, bool, O>;
132#[doc = "Field `TXFNUM` reader - TxFIFO Number"]
133pub type TXFNUM_R = crate::FieldReader<u8, u8>;
134#[doc = "Field `TXFNUM` writer - TxFIFO Number"]
135pub type TXFNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEP5_CTL_SPEC, u8, u8, 4, O>;
136#[doc = "Field `CNAK` writer - Clear NAK"]
137pub type CNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEP5_CTL_SPEC, bool, O>;
138#[doc = "Field `SNAK` writer - Set NAK"]
139pub type SNAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEP5_CTL_SPEC, bool, O>;
140#[doc = "Field `SETD0PIDEF` writer - Set DATA0 PID / Even Frame"]
141pub type SETD0PIDEF_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEP5_CTL_SPEC, bool, O>;
142#[doc = "Field `SETD1PIDOF` writer - Set DATA1 PID / Odd Frame"]
143pub type SETD1PIDOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEP5_CTL_SPEC, bool, O>;
144#[doc = "Field `EPDIS` reader - Endpoint Disable"]
145pub type EPDIS_R = crate::BitReader<bool>;
146#[doc = "Field `EPDIS` writer - Endpoint Disable"]
147pub type EPDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEP5_CTL_SPEC, bool, O>;
148#[doc = "Field `EPENA` reader - Endpoint Enable"]
149pub type EPENA_R = crate::BitReader<bool>;
150#[doc = "Field `EPENA` writer - Endpoint Enable"]
151pub type EPENA_W<'a, const O: u8> = crate::BitWriter<'a, u32, DIEP5_CTL_SPEC, bool, O>;
152impl R {
153    #[doc = "Bits 0:10 - Maximum Packet Size"]
154    #[inline(always)]
155    pub fn mps(&self) -> MPS_R {
156        MPS_R::new((self.bits & 0x07ff) as u16)
157    }
158    #[doc = "Bit 15 - USB Active Endpoint"]
159    #[inline(always)]
160    pub fn usbactep(&self) -> USBACTEP_R {
161        USBACTEP_R::new(((self.bits >> 15) & 1) != 0)
162    }
163    #[doc = "Bit 16 - Endpoint Data PID / Even or Odd Frame"]
164    #[inline(always)]
165    pub fn dpideof(&self) -> DPIDEOF_R {
166        DPIDEOF_R::new(((self.bits >> 16) & 1) != 0)
167    }
168    #[doc = "Bit 17 - NAK Status"]
169    #[inline(always)]
170    pub fn naksts(&self) -> NAKSTS_R {
171        NAKSTS_R::new(((self.bits >> 17) & 1) != 0)
172    }
173    #[doc = "Bits 18:19 - Endpoint Type"]
174    #[inline(always)]
175    pub fn eptype(&self) -> EPTYPE_R {
176        EPTYPE_R::new(((self.bits >> 18) & 3) as u8)
177    }
178    #[doc = "Bit 21 - Handshake"]
179    #[inline(always)]
180    pub fn stall(&self) -> STALL_R {
181        STALL_R::new(((self.bits >> 21) & 1) != 0)
182    }
183    #[doc = "Bits 22:25 - TxFIFO Number"]
184    #[inline(always)]
185    pub fn txfnum(&self) -> TXFNUM_R {
186        TXFNUM_R::new(((self.bits >> 22) & 0x0f) as u8)
187    }
188    #[doc = "Bit 30 - Endpoint Disable"]
189    #[inline(always)]
190    pub fn epdis(&self) -> EPDIS_R {
191        EPDIS_R::new(((self.bits >> 30) & 1) != 0)
192    }
193    #[doc = "Bit 31 - Endpoint Enable"]
194    #[inline(always)]
195    pub fn epena(&self) -> EPENA_R {
196        EPENA_R::new(((self.bits >> 31) & 1) != 0)
197    }
198}
199impl W {
200    #[doc = "Bits 0:10 - Maximum Packet Size"]
201    #[inline(always)]
202    #[must_use]
203    pub fn mps(&mut self) -> MPS_W<0> {
204        MPS_W::new(self)
205    }
206    #[doc = "Bit 15 - USB Active Endpoint"]
207    #[inline(always)]
208    #[must_use]
209    pub fn usbactep(&mut self) -> USBACTEP_W<15> {
210        USBACTEP_W::new(self)
211    }
212    #[doc = "Bits 18:19 - Endpoint Type"]
213    #[inline(always)]
214    #[must_use]
215    pub fn eptype(&mut self) -> EPTYPE_W<18> {
216        EPTYPE_W::new(self)
217    }
218    #[doc = "Bit 21 - Handshake"]
219    #[inline(always)]
220    #[must_use]
221    pub fn stall(&mut self) -> STALL_W<21> {
222        STALL_W::new(self)
223    }
224    #[doc = "Bits 22:25 - TxFIFO Number"]
225    #[inline(always)]
226    #[must_use]
227    pub fn txfnum(&mut self) -> TXFNUM_W<22> {
228        TXFNUM_W::new(self)
229    }
230    #[doc = "Bit 26 - Clear NAK"]
231    #[inline(always)]
232    #[must_use]
233    pub fn cnak(&mut self) -> CNAK_W<26> {
234        CNAK_W::new(self)
235    }
236    #[doc = "Bit 27 - Set NAK"]
237    #[inline(always)]
238    #[must_use]
239    pub fn snak(&mut self) -> SNAK_W<27> {
240        SNAK_W::new(self)
241    }
242    #[doc = "Bit 28 - Set DATA0 PID / Even Frame"]
243    #[inline(always)]
244    #[must_use]
245    pub fn setd0pidef(&mut self) -> SETD0PIDEF_W<28> {
246        SETD0PIDEF_W::new(self)
247    }
248    #[doc = "Bit 29 - Set DATA1 PID / Odd Frame"]
249    #[inline(always)]
250    #[must_use]
251    pub fn setd1pidof(&mut self) -> SETD1PIDOF_W<29> {
252        SETD1PIDOF_W::new(self)
253    }
254    #[doc = "Bit 30 - Endpoint Disable"]
255    #[inline(always)]
256    #[must_use]
257    pub fn epdis(&mut self) -> EPDIS_W<30> {
258        EPDIS_W::new(self)
259    }
260    #[doc = "Bit 31 - Endpoint Enable"]
261    #[inline(always)]
262    #[must_use]
263    pub fn epena(&mut self) -> EPENA_W<31> {
264        EPENA_W::new(self)
265    }
266    #[doc = "Writes raw bits to the register."]
267    #[inline(always)]
268    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
269        self.0.bits(bits);
270        self
271    }
272}
273#[doc = "Device IN Endpoint x+1 Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep5_ctl](index.html) module"]
274pub struct DIEP5_CTL_SPEC;
275impl crate::RegisterSpec for DIEP5_CTL_SPEC {
276    type Ux = u32;
277}
278#[doc = "`read()` method returns [diep5_ctl::R](R) reader structure"]
279impl crate::Readable for DIEP5_CTL_SPEC {
280    type Reader = R;
281}
282#[doc = "`write(|w| ..)` method takes [diep5_ctl::W](W) writer structure"]
283impl crate::Writable for DIEP5_CTL_SPEC {
284    type Writer = W;
285    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
286    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
287}
288#[doc = "`reset()` method sets DIEP5_CTL to value 0"]
289impl crate::Resettable for DIEP5_CTL_SPEC {
290    const RESET_VALUE: Self::Ux = 0;
291}
efm32gg_pac/efm32gg995/usb/diep5_ctl.rs

efm32gg_pac/efm32gg995/usb/
diep5_ctl.rs
