1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `SYNC` reader - USART Synchronous Mode"]
38pub type SYNC_R = crate::BitReader<bool>;
39#[doc = "Field `SYNC` writer - USART Synchronous Mode"]
40pub type SYNC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
41#[doc = "Field `LOOPBK` reader - Loopback Enable"]
42pub type LOOPBK_R = crate::BitReader<bool>;
43#[doc = "Field `LOOPBK` writer - Loopback Enable"]
44pub type LOOPBK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
45#[doc = "Field `CCEN` reader - Collision Check Enable"]
46pub type CCEN_R = crate::BitReader<bool>;
47#[doc = "Field `CCEN` writer - Collision Check Enable"]
48pub type CCEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
49#[doc = "Field `MPM` reader - Multi-Processor Mode"]
50pub type MPM_R = crate::BitReader<bool>;
51#[doc = "Field `MPM` writer - Multi-Processor Mode"]
52pub type MPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
53#[doc = "Field `MPAB` reader - Multi-Processor Address-Bit"]
54pub type MPAB_R = crate::BitReader<bool>;
55#[doc = "Field `MPAB` writer - Multi-Processor Address-Bit"]
56pub type MPAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
57#[doc = "Field `OVS` reader - Oversampling"]
58pub type OVS_R = crate::FieldReader<u8, OVS_A>;
59#[doc = "Oversampling\n\nValue on reset: 0"]
60#[derive(Clone, Copy, Debug, PartialEq, Eq)]
61#[repr(u8)]
62pub enum OVS_A {
63 #[doc = "0: Regular UART mode with 16X oversampling in asynchronous mode"]
64 X16 = 0,
65 #[doc = "1: Double speed with 8X oversampling in asynchronous mode"]
66 X8 = 1,
67 #[doc = "2: 6X oversampling in asynchronous mode"]
68 X6 = 2,
69 #[doc = "3: Quadruple speed with 4X oversampling in asynchronous mode"]
70 X4 = 3,
71}
72impl From<OVS_A> for u8 {
73 #[inline(always)]
74 fn from(variant: OVS_A) -> Self {
75 variant as _
76 }
77}
78impl OVS_R {
79 #[doc = "Get enumerated values variant"]
80 #[inline(always)]
81 pub fn variant(&self) -> OVS_A {
82 match self.bits {
83 0 => OVS_A::X16,
84 1 => OVS_A::X8,
85 2 => OVS_A::X6,
86 3 => OVS_A::X4,
87 _ => unreachable!(),
88 }
89 }
90 #[doc = "Checks if the value of the field is `X16`"]
91 #[inline(always)]
92 pub fn is_x16(&self) -> bool {
93 *self == OVS_A::X16
94 }
95 #[doc = "Checks if the value of the field is `X8`"]
96 #[inline(always)]
97 pub fn is_x8(&self) -> bool {
98 *self == OVS_A::X8
99 }
100 #[doc = "Checks if the value of the field is `X6`"]
101 #[inline(always)]
102 pub fn is_x6(&self) -> bool {
103 *self == OVS_A::X6
104 }
105 #[doc = "Checks if the value of the field is `X4`"]
106 #[inline(always)]
107 pub fn is_x4(&self) -> bool {
108 *self == OVS_A::X4
109 }
110}
111#[doc = "Field `OVS` writer - Oversampling"]
112pub type OVS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, OVS_A, 2, O>;
113impl<'a, const O: u8> OVS_W<'a, O> {
114 #[doc = "Regular UART mode with 16X oversampling in asynchronous mode"]
115 #[inline(always)]
116 pub fn x16(self) -> &'a mut W {
117 self.variant(OVS_A::X16)
118 }
119 #[doc = "Double speed with 8X oversampling in asynchronous mode"]
120 #[inline(always)]
121 pub fn x8(self) -> &'a mut W {
122 self.variant(OVS_A::X8)
123 }
124 #[doc = "6X oversampling in asynchronous mode"]
125 #[inline(always)]
126 pub fn x6(self) -> &'a mut W {
127 self.variant(OVS_A::X6)
128 }
129 #[doc = "Quadruple speed with 4X oversampling in asynchronous mode"]
130 #[inline(always)]
131 pub fn x4(self) -> &'a mut W {
132 self.variant(OVS_A::X4)
133 }
134}
135#[doc = "Field `CLKPOL` reader - Clock Polarity"]
136pub type CLKPOL_R = crate::BitReader<bool>;
137#[doc = "Field `CLKPOL` writer - Clock Polarity"]
138pub type CLKPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
139#[doc = "Field `CLKPHA` reader - Clock Edge For Setup/Sample"]
140pub type CLKPHA_R = crate::BitReader<bool>;
141#[doc = "Field `CLKPHA` writer - Clock Edge For Setup/Sample"]
142pub type CLKPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
143#[doc = "Field `MSBF` reader - Most Significant Bit First"]
144pub type MSBF_R = crate::BitReader<bool>;
145#[doc = "Field `MSBF` writer - Most Significant Bit First"]
146pub type MSBF_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
147#[doc = "Field `CSMA` reader - Action On Slave-Select In Master Mode"]
148pub type CSMA_R = crate::BitReader<bool>;
149#[doc = "Field `CSMA` writer - Action On Slave-Select In Master Mode"]
150pub type CSMA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
151#[doc = "Field `TXBIL` reader - TX Buffer Interrupt Level"]
152pub type TXBIL_R = crate::BitReader<bool>;
153#[doc = "Field `TXBIL` writer - TX Buffer Interrupt Level"]
154pub type TXBIL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
155#[doc = "Field `RXINV` reader - Receiver Input Invert"]
156pub type RXINV_R = crate::BitReader<bool>;
157#[doc = "Field `RXINV` writer - Receiver Input Invert"]
158pub type RXINV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
159#[doc = "Field `TXINV` reader - Transmitter output Invert"]
160pub type TXINV_R = crate::BitReader<bool>;
161#[doc = "Field `TXINV` writer - Transmitter output Invert"]
162pub type TXINV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
163#[doc = "Field `CSINV` reader - Chip Select Invert"]
164pub type CSINV_R = crate::BitReader<bool>;
165#[doc = "Field `CSINV` writer - Chip Select Invert"]
166pub type CSINV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
167#[doc = "Field `AUTOCS` reader - Automatic Chip Select"]
168pub type AUTOCS_R = crate::BitReader<bool>;
169#[doc = "Field `AUTOCS` writer - Automatic Chip Select"]
170pub type AUTOCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
171#[doc = "Field `AUTOTRI` reader - Automatic TX Tristate"]
172pub type AUTOTRI_R = crate::BitReader<bool>;
173#[doc = "Field `AUTOTRI` writer - Automatic TX Tristate"]
174pub type AUTOTRI_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
175#[doc = "Field `SCMODE` reader - SmartCard Mode"]
176pub type SCMODE_R = crate::BitReader<bool>;
177#[doc = "Field `SCMODE` writer - SmartCard Mode"]
178pub type SCMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
179#[doc = "Field `SCRETRANS` reader - SmartCard Retransmit"]
180pub type SCRETRANS_R = crate::BitReader<bool>;
181#[doc = "Field `SCRETRANS` writer - SmartCard Retransmit"]
182pub type SCRETRANS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
183#[doc = "Field `SKIPPERRF` reader - Skip Parity Error Frames"]
184pub type SKIPPERRF_R = crate::BitReader<bool>;
185#[doc = "Field `SKIPPERRF` writer - Skip Parity Error Frames"]
186pub type SKIPPERRF_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
187#[doc = "Field `BIT8DV` reader - Bit 8 Default Value"]
188pub type BIT8DV_R = crate::BitReader<bool>;
189#[doc = "Field `BIT8DV` writer - Bit 8 Default Value"]
190pub type BIT8DV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
191#[doc = "Field `ERRSDMA` reader - Halt DMA On Error"]
192pub type ERRSDMA_R = crate::BitReader<bool>;
193#[doc = "Field `ERRSDMA` writer - Halt DMA On Error"]
194pub type ERRSDMA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
195#[doc = "Field `ERRSRX` reader - Disable RX On Error"]
196pub type ERRSRX_R = crate::BitReader<bool>;
197#[doc = "Field `ERRSRX` writer - Disable RX On Error"]
198pub type ERRSRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
199#[doc = "Field `ERRSTX` reader - Disable TX On Error"]
200pub type ERRSTX_R = crate::BitReader<bool>;
201#[doc = "Field `ERRSTX` writer - Disable TX On Error"]
202pub type ERRSTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
203#[doc = "Field `TXDELAY` reader - TX Delay Transmission"]
204pub type TXDELAY_R = crate::FieldReader<u8, TXDELAY_A>;
205#[doc = "TX Delay Transmission\n\nValue on reset: 0"]
206#[derive(Clone, Copy, Debug, PartialEq, Eq)]
207#[repr(u8)]
208pub enum TXDELAY_A {
209 #[doc = "0: Frames are transmitted immediately"]
210 NONE = 0,
211 #[doc = "1: Transmission of new frames are delayed by a single baud period"]
212 SINGLE = 1,
213 #[doc = "2: Transmission of new frames are delayed by two baud periods"]
214 DOUBLE = 2,
215 #[doc = "3: Transmission of new frames are delayed by three baud periods"]
216 TRIPLE = 3,
217}
218impl From<TXDELAY_A> for u8 {
219 #[inline(always)]
220 fn from(variant: TXDELAY_A) -> Self {
221 variant as _
222 }
223}
224impl TXDELAY_R {
225 #[doc = "Get enumerated values variant"]
226 #[inline(always)]
227 pub fn variant(&self) -> TXDELAY_A {
228 match self.bits {
229 0 => TXDELAY_A::NONE,
230 1 => TXDELAY_A::SINGLE,
231 2 => TXDELAY_A::DOUBLE,
232 3 => TXDELAY_A::TRIPLE,
233 _ => unreachable!(),
234 }
235 }
236 #[doc = "Checks if the value of the field is `NONE`"]
237 #[inline(always)]
238 pub fn is_none(&self) -> bool {
239 *self == TXDELAY_A::NONE
240 }
241 #[doc = "Checks if the value of the field is `SINGLE`"]
242 #[inline(always)]
243 pub fn is_single(&self) -> bool {
244 *self == TXDELAY_A::SINGLE
245 }
246 #[doc = "Checks if the value of the field is `DOUBLE`"]
247 #[inline(always)]
248 pub fn is_double(&self) -> bool {
249 *self == TXDELAY_A::DOUBLE
250 }
251 #[doc = "Checks if the value of the field is `TRIPLE`"]
252 #[inline(always)]
253 pub fn is_triple(&self) -> bool {
254 *self == TXDELAY_A::TRIPLE
255 }
256}
257#[doc = "Field `TXDELAY` writer - TX Delay Transmission"]
258pub type TXDELAY_W<'a, const O: u8> =
259 crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, TXDELAY_A, 2, O>;
260impl<'a, const O: u8> TXDELAY_W<'a, O> {
261 #[doc = "Frames are transmitted immediately"]
262 #[inline(always)]
263 pub fn none(self) -> &'a mut W {
264 self.variant(TXDELAY_A::NONE)
265 }
266 #[doc = "Transmission of new frames are delayed by a single baud period"]
267 #[inline(always)]
268 pub fn single(self) -> &'a mut W {
269 self.variant(TXDELAY_A::SINGLE)
270 }
271 #[doc = "Transmission of new frames are delayed by two baud periods"]
272 #[inline(always)]
273 pub fn double(self) -> &'a mut W {
274 self.variant(TXDELAY_A::DOUBLE)
275 }
276 #[doc = "Transmission of new frames are delayed by three baud periods"]
277 #[inline(always)]
278 pub fn triple(self) -> &'a mut W {
279 self.variant(TXDELAY_A::TRIPLE)
280 }
281}
282#[doc = "Field `BYTESWAP` reader - Byteswap In Double Accesses"]
283pub type BYTESWAP_R = crate::BitReader<bool>;
284#[doc = "Field `BYTESWAP` writer - Byteswap In Double Accesses"]
285pub type BYTESWAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
286#[doc = "Field `AUTOTX` reader - Always Transmit When RX Not Full"]
287pub type AUTOTX_R = crate::BitReader<bool>;
288#[doc = "Field `AUTOTX` writer - Always Transmit When RX Not Full"]
289pub type AUTOTX_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
290#[doc = "Field `MVDIS` reader - Majority Vote Disable"]
291pub type MVDIS_R = crate::BitReader<bool>;
292#[doc = "Field `MVDIS` writer - Majority Vote Disable"]
293pub type MVDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
294impl R {
295 #[doc = "Bit 0 - USART Synchronous Mode"]
296 #[inline(always)]
297 pub fn sync(&self) -> SYNC_R {
298 SYNC_R::new((self.bits & 1) != 0)
299 }
300 #[doc = "Bit 1 - Loopback Enable"]
301 #[inline(always)]
302 pub fn loopbk(&self) -> LOOPBK_R {
303 LOOPBK_R::new(((self.bits >> 1) & 1) != 0)
304 }
305 #[doc = "Bit 2 - Collision Check Enable"]
306 #[inline(always)]
307 pub fn ccen(&self) -> CCEN_R {
308 CCEN_R::new(((self.bits >> 2) & 1) != 0)
309 }
310 #[doc = "Bit 3 - Multi-Processor Mode"]
311 #[inline(always)]
312 pub fn mpm(&self) -> MPM_R {
313 MPM_R::new(((self.bits >> 3) & 1) != 0)
314 }
315 #[doc = "Bit 4 - Multi-Processor Address-Bit"]
316 #[inline(always)]
317 pub fn mpab(&self) -> MPAB_R {
318 MPAB_R::new(((self.bits >> 4) & 1) != 0)
319 }
320 #[doc = "Bits 5:6 - Oversampling"]
321 #[inline(always)]
322 pub fn ovs(&self) -> OVS_R {
323 OVS_R::new(((self.bits >> 5) & 3) as u8)
324 }
325 #[doc = "Bit 8 - Clock Polarity"]
326 #[inline(always)]
327 pub fn clkpol(&self) -> CLKPOL_R {
328 CLKPOL_R::new(((self.bits >> 8) & 1) != 0)
329 }
330 #[doc = "Bit 9 - Clock Edge For Setup/Sample"]
331 #[inline(always)]
332 pub fn clkpha(&self) -> CLKPHA_R {
333 CLKPHA_R::new(((self.bits >> 9) & 1) != 0)
334 }
335 #[doc = "Bit 10 - Most Significant Bit First"]
336 #[inline(always)]
337 pub fn msbf(&self) -> MSBF_R {
338 MSBF_R::new(((self.bits >> 10) & 1) != 0)
339 }
340 #[doc = "Bit 11 - Action On Slave-Select In Master Mode"]
341 #[inline(always)]
342 pub fn csma(&self) -> CSMA_R {
343 CSMA_R::new(((self.bits >> 11) & 1) != 0)
344 }
345 #[doc = "Bit 12 - TX Buffer Interrupt Level"]
346 #[inline(always)]
347 pub fn txbil(&self) -> TXBIL_R {
348 TXBIL_R::new(((self.bits >> 12) & 1) != 0)
349 }
350 #[doc = "Bit 13 - Receiver Input Invert"]
351 #[inline(always)]
352 pub fn rxinv(&self) -> RXINV_R {
353 RXINV_R::new(((self.bits >> 13) & 1) != 0)
354 }
355 #[doc = "Bit 14 - Transmitter output Invert"]
356 #[inline(always)]
357 pub fn txinv(&self) -> TXINV_R {
358 TXINV_R::new(((self.bits >> 14) & 1) != 0)
359 }
360 #[doc = "Bit 15 - Chip Select Invert"]
361 #[inline(always)]
362 pub fn csinv(&self) -> CSINV_R {
363 CSINV_R::new(((self.bits >> 15) & 1) != 0)
364 }
365 #[doc = "Bit 16 - Automatic Chip Select"]
366 #[inline(always)]
367 pub fn autocs(&self) -> AUTOCS_R {
368 AUTOCS_R::new(((self.bits >> 16) & 1) != 0)
369 }
370 #[doc = "Bit 17 - Automatic TX Tristate"]
371 #[inline(always)]
372 pub fn autotri(&self) -> AUTOTRI_R {
373 AUTOTRI_R::new(((self.bits >> 17) & 1) != 0)
374 }
375 #[doc = "Bit 18 - SmartCard Mode"]
376 #[inline(always)]
377 pub fn scmode(&self) -> SCMODE_R {
378 SCMODE_R::new(((self.bits >> 18) & 1) != 0)
379 }
380 #[doc = "Bit 19 - SmartCard Retransmit"]
381 #[inline(always)]
382 pub fn scretrans(&self) -> SCRETRANS_R {
383 SCRETRANS_R::new(((self.bits >> 19) & 1) != 0)
384 }
385 #[doc = "Bit 20 - Skip Parity Error Frames"]
386 #[inline(always)]
387 pub fn skipperrf(&self) -> SKIPPERRF_R {
388 SKIPPERRF_R::new(((self.bits >> 20) & 1) != 0)
389 }
390 #[doc = "Bit 21 - Bit 8 Default Value"]
391 #[inline(always)]
392 pub fn bit8dv(&self) -> BIT8DV_R {
393 BIT8DV_R::new(((self.bits >> 21) & 1) != 0)
394 }
395 #[doc = "Bit 22 - Halt DMA On Error"]
396 #[inline(always)]
397 pub fn errsdma(&self) -> ERRSDMA_R {
398 ERRSDMA_R::new(((self.bits >> 22) & 1) != 0)
399 }
400 #[doc = "Bit 23 - Disable RX On Error"]
401 #[inline(always)]
402 pub fn errsrx(&self) -> ERRSRX_R {
403 ERRSRX_R::new(((self.bits >> 23) & 1) != 0)
404 }
405 #[doc = "Bit 24 - Disable TX On Error"]
406 #[inline(always)]
407 pub fn errstx(&self) -> ERRSTX_R {
408 ERRSTX_R::new(((self.bits >> 24) & 1) != 0)
409 }
410 #[doc = "Bits 26:27 - TX Delay Transmission"]
411 #[inline(always)]
412 pub fn txdelay(&self) -> TXDELAY_R {
413 TXDELAY_R::new(((self.bits >> 26) & 3) as u8)
414 }
415 #[doc = "Bit 28 - Byteswap In Double Accesses"]
416 #[inline(always)]
417 pub fn byteswap(&self) -> BYTESWAP_R {
418 BYTESWAP_R::new(((self.bits >> 28) & 1) != 0)
419 }
420 #[doc = "Bit 29 - Always Transmit When RX Not Full"]
421 #[inline(always)]
422 pub fn autotx(&self) -> AUTOTX_R {
423 AUTOTX_R::new(((self.bits >> 29) & 1) != 0)
424 }
425 #[doc = "Bit 30 - Majority Vote Disable"]
426 #[inline(always)]
427 pub fn mvdis(&self) -> MVDIS_R {
428 MVDIS_R::new(((self.bits >> 30) & 1) != 0)
429 }
430}
431impl W {
432 #[doc = "Bit 0 - USART Synchronous Mode"]
433 #[inline(always)]
434 #[must_use]
435 pub fn sync(&mut self) -> SYNC_W<0> {
436 SYNC_W::new(self)
437 }
438 #[doc = "Bit 1 - Loopback Enable"]
439 #[inline(always)]
440 #[must_use]
441 pub fn loopbk(&mut self) -> LOOPBK_W<1> {
442 LOOPBK_W::new(self)
443 }
444 #[doc = "Bit 2 - Collision Check Enable"]
445 #[inline(always)]
446 #[must_use]
447 pub fn ccen(&mut self) -> CCEN_W<2> {
448 CCEN_W::new(self)
449 }
450 #[doc = "Bit 3 - Multi-Processor Mode"]
451 #[inline(always)]
452 #[must_use]
453 pub fn mpm(&mut self) -> MPM_W<3> {
454 MPM_W::new(self)
455 }
456 #[doc = "Bit 4 - Multi-Processor Address-Bit"]
457 #[inline(always)]
458 #[must_use]
459 pub fn mpab(&mut self) -> MPAB_W<4> {
460 MPAB_W::new(self)
461 }
462 #[doc = "Bits 5:6 - Oversampling"]
463 #[inline(always)]
464 #[must_use]
465 pub fn ovs(&mut self) -> OVS_W<5> {
466 OVS_W::new(self)
467 }
468 #[doc = "Bit 8 - Clock Polarity"]
469 #[inline(always)]
470 #[must_use]
471 pub fn clkpol(&mut self) -> CLKPOL_W<8> {
472 CLKPOL_W::new(self)
473 }
474 #[doc = "Bit 9 - Clock Edge For Setup/Sample"]
475 #[inline(always)]
476 #[must_use]
477 pub fn clkpha(&mut self) -> CLKPHA_W<9> {
478 CLKPHA_W::new(self)
479 }
480 #[doc = "Bit 10 - Most Significant Bit First"]
481 #[inline(always)]
482 #[must_use]
483 pub fn msbf(&mut self) -> MSBF_W<10> {
484 MSBF_W::new(self)
485 }
486 #[doc = "Bit 11 - Action On Slave-Select In Master Mode"]
487 #[inline(always)]
488 #[must_use]
489 pub fn csma(&mut self) -> CSMA_W<11> {
490 CSMA_W::new(self)
491 }
492 #[doc = "Bit 12 - TX Buffer Interrupt Level"]
493 #[inline(always)]
494 #[must_use]
495 pub fn txbil(&mut self) -> TXBIL_W<12> {
496 TXBIL_W::new(self)
497 }
498 #[doc = "Bit 13 - Receiver Input Invert"]
499 #[inline(always)]
500 #[must_use]
501 pub fn rxinv(&mut self) -> RXINV_W<13> {
502 RXINV_W::new(self)
503 }
504 #[doc = "Bit 14 - Transmitter output Invert"]
505 #[inline(always)]
506 #[must_use]
507 pub fn txinv(&mut self) -> TXINV_W<14> {
508 TXINV_W::new(self)
509 }
510 #[doc = "Bit 15 - Chip Select Invert"]
511 #[inline(always)]
512 #[must_use]
513 pub fn csinv(&mut self) -> CSINV_W<15> {
514 CSINV_W::new(self)
515 }
516 #[doc = "Bit 16 - Automatic Chip Select"]
517 #[inline(always)]
518 #[must_use]
519 pub fn autocs(&mut self) -> AUTOCS_W<16> {
520 AUTOCS_W::new(self)
521 }
522 #[doc = "Bit 17 - Automatic TX Tristate"]
523 #[inline(always)]
524 #[must_use]
525 pub fn autotri(&mut self) -> AUTOTRI_W<17> {
526 AUTOTRI_W::new(self)
527 }
528 #[doc = "Bit 18 - SmartCard Mode"]
529 #[inline(always)]
530 #[must_use]
531 pub fn scmode(&mut self) -> SCMODE_W<18> {
532 SCMODE_W::new(self)
533 }
534 #[doc = "Bit 19 - SmartCard Retransmit"]
535 #[inline(always)]
536 #[must_use]
537 pub fn scretrans(&mut self) -> SCRETRANS_W<19> {
538 SCRETRANS_W::new(self)
539 }
540 #[doc = "Bit 20 - Skip Parity Error Frames"]
541 #[inline(always)]
542 #[must_use]
543 pub fn skipperrf(&mut self) -> SKIPPERRF_W<20> {
544 SKIPPERRF_W::new(self)
545 }
546 #[doc = "Bit 21 - Bit 8 Default Value"]
547 #[inline(always)]
548 #[must_use]
549 pub fn bit8dv(&mut self) -> BIT8DV_W<21> {
550 BIT8DV_W::new(self)
551 }
552 #[doc = "Bit 22 - Halt DMA On Error"]
553 #[inline(always)]
554 #[must_use]
555 pub fn errsdma(&mut self) -> ERRSDMA_W<22> {
556 ERRSDMA_W::new(self)
557 }
558 #[doc = "Bit 23 - Disable RX On Error"]
559 #[inline(always)]
560 #[must_use]
561 pub fn errsrx(&mut self) -> ERRSRX_W<23> {
562 ERRSRX_W::new(self)
563 }
564 #[doc = "Bit 24 - Disable TX On Error"]
565 #[inline(always)]
566 #[must_use]
567 pub fn errstx(&mut self) -> ERRSTX_W<24> {
568 ERRSTX_W::new(self)
569 }
570 #[doc = "Bits 26:27 - TX Delay Transmission"]
571 #[inline(always)]
572 #[must_use]
573 pub fn txdelay(&mut self) -> TXDELAY_W<26> {
574 TXDELAY_W::new(self)
575 }
576 #[doc = "Bit 28 - Byteswap In Double Accesses"]
577 #[inline(always)]
578 #[must_use]
579 pub fn byteswap(&mut self) -> BYTESWAP_W<28> {
580 BYTESWAP_W::new(self)
581 }
582 #[doc = "Bit 29 - Always Transmit When RX Not Full"]
583 #[inline(always)]
584 #[must_use]
585 pub fn autotx(&mut self) -> AUTOTX_W<29> {
586 AUTOTX_W::new(self)
587 }
588 #[doc = "Bit 30 - Majority Vote Disable"]
589 #[inline(always)]
590 #[must_use]
591 pub fn mvdis(&mut self) -> MVDIS_W<30> {
592 MVDIS_W::new(self)
593 }
594 #[doc = "Writes raw bits to the register."]
595 #[inline(always)]
596 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
597 self.0.bits(bits);
598 self
599 }
600}
601#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
602pub struct CTRL_SPEC;
603impl crate::RegisterSpec for CTRL_SPEC {
604 type Ux = u32;
605}
606#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
607impl crate::Readable for CTRL_SPEC {
608 type Reader = R;
609}
610#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
611impl crate::Writable for CTRL_SPEC {
612 type Writer = W;
613 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
614 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
615}
616#[doc = "`reset()` method sets CTRL to value 0"]
617impl crate::Resettable for CTRL_SPEC {
618 const RESET_VALUE: Self::Ux = 0;
619}