efm32gg_pac/efm32gg995/uart1/
ien.rs1#[doc = "Register `IEN` reader"]
2pub struct R(crate::R<IEN_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<IEN_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<IEN_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<IEN_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `IEN` writer"]
17pub struct W(crate::W<IEN_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<IEN_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<IEN_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<IEN_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `TXC` reader - TX Complete Interrupt Enable"]
38pub type TXC_R = crate::BitReader<bool>;
39#[doc = "Field `TXC` writer - TX Complete Interrupt Enable"]
40pub type TXC_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
41#[doc = "Field `TXBL` reader - TX Buffer Level Interrupt Enable"]
42pub type TXBL_R = crate::BitReader<bool>;
43#[doc = "Field `TXBL` writer - TX Buffer Level Interrupt Enable"]
44pub type TXBL_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
45#[doc = "Field `RXDATAV` reader - RX Data Valid Interrupt Enable"]
46pub type RXDATAV_R = crate::BitReader<bool>;
47#[doc = "Field `RXDATAV` writer - RX Data Valid Interrupt Enable"]
48pub type RXDATAV_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
49#[doc = "Field `RXFULL` reader - RX Buffer Full Interrupt Enable"]
50pub type RXFULL_R = crate::BitReader<bool>;
51#[doc = "Field `RXFULL` writer - RX Buffer Full Interrupt Enable"]
52pub type RXFULL_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
53#[doc = "Field `RXOF` reader - RX Overflow Interrupt Enable"]
54pub type RXOF_R = crate::BitReader<bool>;
55#[doc = "Field `RXOF` writer - RX Overflow Interrupt Enable"]
56pub type RXOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
57#[doc = "Field `RXUF` reader - RX Underflow Interrupt Enable"]
58pub type RXUF_R = crate::BitReader<bool>;
59#[doc = "Field `RXUF` writer - RX Underflow Interrupt Enable"]
60pub type RXUF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
61#[doc = "Field `TXOF` reader - TX Overflow Interrupt Enable"]
62pub type TXOF_R = crate::BitReader<bool>;
63#[doc = "Field `TXOF` writer - TX Overflow Interrupt Enable"]
64pub type TXOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
65#[doc = "Field `TXUF` reader - TX Underflow Interrupt Enable"]
66pub type TXUF_R = crate::BitReader<bool>;
67#[doc = "Field `TXUF` writer - TX Underflow Interrupt Enable"]
68pub type TXUF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
69#[doc = "Field `PERR` reader - Parity Error Interrupt Enable"]
70pub type PERR_R = crate::BitReader<bool>;
71#[doc = "Field `PERR` writer - Parity Error Interrupt Enable"]
72pub type PERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
73#[doc = "Field `FERR` reader - Framing Error Interrupt Enable"]
74pub type FERR_R = crate::BitReader<bool>;
75#[doc = "Field `FERR` writer - Framing Error Interrupt Enable"]
76pub type FERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
77#[doc = "Field `MPAF` reader - Multi-Processor Address Frame Interrupt Enable"]
78pub type MPAF_R = crate::BitReader<bool>;
79#[doc = "Field `MPAF` writer - Multi-Processor Address Frame Interrupt Enable"]
80pub type MPAF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
81#[doc = "Field `SSM` reader - Slave-Select In Master Mode Interrupt Enable"]
82pub type SSM_R = crate::BitReader<bool>;
83#[doc = "Field `SSM` writer - Slave-Select In Master Mode Interrupt Enable"]
84pub type SSM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
85#[doc = "Field `CCF` reader - Collision Check Fail Interrupt Enable"]
86pub type CCF_R = crate::BitReader<bool>;
87#[doc = "Field `CCF` writer - Collision Check Fail Interrupt Enable"]
88pub type CCF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IEN_SPEC, bool, O>;
89impl R {
90 #[doc = "Bit 0 - TX Complete Interrupt Enable"]
91 #[inline(always)]
92 pub fn txc(&self) -> TXC_R {
93 TXC_R::new((self.bits & 1) != 0)
94 }
95 #[doc = "Bit 1 - TX Buffer Level Interrupt Enable"]
96 #[inline(always)]
97 pub fn txbl(&self) -> TXBL_R {
98 TXBL_R::new(((self.bits >> 1) & 1) != 0)
99 }
100 #[doc = "Bit 2 - RX Data Valid Interrupt Enable"]
101 #[inline(always)]
102 pub fn rxdatav(&self) -> RXDATAV_R {
103 RXDATAV_R::new(((self.bits >> 2) & 1) != 0)
104 }
105 #[doc = "Bit 3 - RX Buffer Full Interrupt Enable"]
106 #[inline(always)]
107 pub fn rxfull(&self) -> RXFULL_R {
108 RXFULL_R::new(((self.bits >> 3) & 1) != 0)
109 }
110 #[doc = "Bit 4 - RX Overflow Interrupt Enable"]
111 #[inline(always)]
112 pub fn rxof(&self) -> RXOF_R {
113 RXOF_R::new(((self.bits >> 4) & 1) != 0)
114 }
115 #[doc = "Bit 5 - RX Underflow Interrupt Enable"]
116 #[inline(always)]
117 pub fn rxuf(&self) -> RXUF_R {
118 RXUF_R::new(((self.bits >> 5) & 1) != 0)
119 }
120 #[doc = "Bit 6 - TX Overflow Interrupt Enable"]
121 #[inline(always)]
122 pub fn txof(&self) -> TXOF_R {
123 TXOF_R::new(((self.bits >> 6) & 1) != 0)
124 }
125 #[doc = "Bit 7 - TX Underflow Interrupt Enable"]
126 #[inline(always)]
127 pub fn txuf(&self) -> TXUF_R {
128 TXUF_R::new(((self.bits >> 7) & 1) != 0)
129 }
130 #[doc = "Bit 8 - Parity Error Interrupt Enable"]
131 #[inline(always)]
132 pub fn perr(&self) -> PERR_R {
133 PERR_R::new(((self.bits >> 8) & 1) != 0)
134 }
135 #[doc = "Bit 9 - Framing Error Interrupt Enable"]
136 #[inline(always)]
137 pub fn ferr(&self) -> FERR_R {
138 FERR_R::new(((self.bits >> 9) & 1) != 0)
139 }
140 #[doc = "Bit 10 - Multi-Processor Address Frame Interrupt Enable"]
141 #[inline(always)]
142 pub fn mpaf(&self) -> MPAF_R {
143 MPAF_R::new(((self.bits >> 10) & 1) != 0)
144 }
145 #[doc = "Bit 11 - Slave-Select In Master Mode Interrupt Enable"]
146 #[inline(always)]
147 pub fn ssm(&self) -> SSM_R {
148 SSM_R::new(((self.bits >> 11) & 1) != 0)
149 }
150 #[doc = "Bit 12 - Collision Check Fail Interrupt Enable"]
151 #[inline(always)]
152 pub fn ccf(&self) -> CCF_R {
153 CCF_R::new(((self.bits >> 12) & 1) != 0)
154 }
155}
156impl W {
157 #[doc = "Bit 0 - TX Complete Interrupt Enable"]
158 #[inline(always)]
159 #[must_use]
160 pub fn txc(&mut self) -> TXC_W<0> {
161 TXC_W::new(self)
162 }
163 #[doc = "Bit 1 - TX Buffer Level Interrupt Enable"]
164 #[inline(always)]
165 #[must_use]
166 pub fn txbl(&mut self) -> TXBL_W<1> {
167 TXBL_W::new(self)
168 }
169 #[doc = "Bit 2 - RX Data Valid Interrupt Enable"]
170 #[inline(always)]
171 #[must_use]
172 pub fn rxdatav(&mut self) -> RXDATAV_W<2> {
173 RXDATAV_W::new(self)
174 }
175 #[doc = "Bit 3 - RX Buffer Full Interrupt Enable"]
176 #[inline(always)]
177 #[must_use]
178 pub fn rxfull(&mut self) -> RXFULL_W<3> {
179 RXFULL_W::new(self)
180 }
181 #[doc = "Bit 4 - RX Overflow Interrupt Enable"]
182 #[inline(always)]
183 #[must_use]
184 pub fn rxof(&mut self) -> RXOF_W<4> {
185 RXOF_W::new(self)
186 }
187 #[doc = "Bit 5 - RX Underflow Interrupt Enable"]
188 #[inline(always)]
189 #[must_use]
190 pub fn rxuf(&mut self) -> RXUF_W<5> {
191 RXUF_W::new(self)
192 }
193 #[doc = "Bit 6 - TX Overflow Interrupt Enable"]
194 #[inline(always)]
195 #[must_use]
196 pub fn txof(&mut self) -> TXOF_W<6> {
197 TXOF_W::new(self)
198 }
199 #[doc = "Bit 7 - TX Underflow Interrupt Enable"]
200 #[inline(always)]
201 #[must_use]
202 pub fn txuf(&mut self) -> TXUF_W<7> {
203 TXUF_W::new(self)
204 }
205 #[doc = "Bit 8 - Parity Error Interrupt Enable"]
206 #[inline(always)]
207 #[must_use]
208 pub fn perr(&mut self) -> PERR_W<8> {
209 PERR_W::new(self)
210 }
211 #[doc = "Bit 9 - Framing Error Interrupt Enable"]
212 #[inline(always)]
213 #[must_use]
214 pub fn ferr(&mut self) -> FERR_W<9> {
215 FERR_W::new(self)
216 }
217 #[doc = "Bit 10 - Multi-Processor Address Frame Interrupt Enable"]
218 #[inline(always)]
219 #[must_use]
220 pub fn mpaf(&mut self) -> MPAF_W<10> {
221 MPAF_W::new(self)
222 }
223 #[doc = "Bit 11 - Slave-Select In Master Mode Interrupt Enable"]
224 #[inline(always)]
225 #[must_use]
226 pub fn ssm(&mut self) -> SSM_W<11> {
227 SSM_W::new(self)
228 }
229 #[doc = "Bit 12 - Collision Check Fail Interrupt Enable"]
230 #[inline(always)]
231 #[must_use]
232 pub fn ccf(&mut self) -> CCF_W<12> {
233 CCF_W::new(self)
234 }
235 #[doc = "Writes raw bits to the register."]
236 #[inline(always)]
237 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
238 self.0.bits(bits);
239 self
240 }
241}
242#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ien](index.html) module"]
243pub struct IEN_SPEC;
244impl crate::RegisterSpec for IEN_SPEC {
245 type Ux = u32;
246}
247#[doc = "`read()` method returns [ien::R](R) reader structure"]
248impl crate::Readable for IEN_SPEC {
249 type Reader = R;
250}
251#[doc = "`write(|w| ..)` method takes [ien::W](W) writer structure"]
252impl crate::Writable for IEN_SPEC {
253 type Writer = W;
254 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
255 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
256}
257#[doc = "`reset()` method sets IEN to value 0"]
258impl crate::Resettable for IEN_SPEC {
259 const RESET_VALUE: Self::Ux = 0;
260}