efm32gg_pac/efm32gg995/prs/
ch7_ctrl.rs

1#[doc = "Register `CH7_CTRL` reader"]
2pub struct R(crate::R<CH7_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH7_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH7_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH7_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH7_CTRL` writer"]
17pub struct W(crate::W<CH7_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH7_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH7_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH7_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CH7_CTRL_SPEC, u8, u8, 3, O>;
41#[doc = "Field `SOURCESEL` reader - Source Select"]
42pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
43#[doc = "Source Select\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45#[repr(u8)]
46pub enum SOURCESEL_A {
47    #[doc = "0: No source selected"]
48    NONE = 0,
49    #[doc = "1: Voltage Comparator"]
50    VCMP = 1,
51    #[doc = "2: Analog Comparator 0"]
52    ACMP0 = 2,
53    #[doc = "3: Analog Comparator 1"]
54    ACMP1 = 3,
55    #[doc = "6: Digital to Analog Converter 0"]
56    DAC0 = 6,
57    #[doc = "8: Analog to Digital Converter 0"]
58    ADC0 = 8,
59    #[doc = "16: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
60    USART0 = 16,
61    #[doc = "17: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
62    USART1 = 17,
63    #[doc = "18: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
64    USART2 = 18,
65    #[doc = "28: Timer 0"]
66    TIMER0 = 28,
67    #[doc = "29: Timer 1"]
68    TIMER1 = 29,
69    #[doc = "30: Timer 2"]
70    TIMER2 = 30,
71    #[doc = "31: Timer 3"]
72    TIMER3 = 31,
73    #[doc = "36: Universal Serial Bus Interface"]
74    USB = 36,
75    #[doc = "40: Real-Time Counter"]
76    RTC = 40,
77    #[doc = "41: Universal Asynchronous Receiver/Transmitter 0"]
78    UART0 = 41,
79    #[doc = "42: Universal Asynchronous Receiver/Transmitter 1"]
80    UART1 = 42,
81    #[doc = "48: General purpose Input/Output"]
82    GPIOL = 48,
83    #[doc = "49: General purpose Input/Output"]
84    GPIOH = 49,
85    #[doc = "52: Low Energy Timer 0"]
86    LETIMER0 = 52,
87    #[doc = "55: Backup RTC"]
88    BURTC = 55,
89    #[doc = "57: Low Energy Sensor Interface"]
90    LESENSEL = 57,
91    #[doc = "58: Low Energy Sensor Interface"]
92    LESENSEH = 58,
93    #[doc = "59: Low Energy Sensor Interface"]
94    LESENSED = 59,
95}
96impl From<SOURCESEL_A> for u8 {
97    #[inline(always)]
98    fn from(variant: SOURCESEL_A) -> Self {
99        variant as _
100    }
101}
102impl SOURCESEL_R {
103    #[doc = "Get enumerated values variant"]
104    #[inline(always)]
105    pub fn variant(&self) -> Option<SOURCESEL_A> {
106        match self.bits {
107            0 => Some(SOURCESEL_A::NONE),
108            1 => Some(SOURCESEL_A::VCMP),
109            2 => Some(SOURCESEL_A::ACMP0),
110            3 => Some(SOURCESEL_A::ACMP1),
111            6 => Some(SOURCESEL_A::DAC0),
112            8 => Some(SOURCESEL_A::ADC0),
113            16 => Some(SOURCESEL_A::USART0),
114            17 => Some(SOURCESEL_A::USART1),
115            18 => Some(SOURCESEL_A::USART2),
116            28 => Some(SOURCESEL_A::TIMER0),
117            29 => Some(SOURCESEL_A::TIMER1),
118            30 => Some(SOURCESEL_A::TIMER2),
119            31 => Some(SOURCESEL_A::TIMER3),
120            36 => Some(SOURCESEL_A::USB),
121            40 => Some(SOURCESEL_A::RTC),
122            41 => Some(SOURCESEL_A::UART0),
123            42 => Some(SOURCESEL_A::UART1),
124            48 => Some(SOURCESEL_A::GPIOL),
125            49 => Some(SOURCESEL_A::GPIOH),
126            52 => Some(SOURCESEL_A::LETIMER0),
127            55 => Some(SOURCESEL_A::BURTC),
128            57 => Some(SOURCESEL_A::LESENSEL),
129            58 => Some(SOURCESEL_A::LESENSEH),
130            59 => Some(SOURCESEL_A::LESENSED),
131            _ => None,
132        }
133    }
134    #[doc = "Checks if the value of the field is `NONE`"]
135    #[inline(always)]
136    pub fn is_none(&self) -> bool {
137        *self == SOURCESEL_A::NONE
138    }
139    #[doc = "Checks if the value of the field is `VCMP`"]
140    #[inline(always)]
141    pub fn is_vcmp(&self) -> bool {
142        *self == SOURCESEL_A::VCMP
143    }
144    #[doc = "Checks if the value of the field is `ACMP0`"]
145    #[inline(always)]
146    pub fn is_acmp0(&self) -> bool {
147        *self == SOURCESEL_A::ACMP0
148    }
149    #[doc = "Checks if the value of the field is `ACMP1`"]
150    #[inline(always)]
151    pub fn is_acmp1(&self) -> bool {
152        *self == SOURCESEL_A::ACMP1
153    }
154    #[doc = "Checks if the value of the field is `DAC0`"]
155    #[inline(always)]
156    pub fn is_dac0(&self) -> bool {
157        *self == SOURCESEL_A::DAC0
158    }
159    #[doc = "Checks if the value of the field is `ADC0`"]
160    #[inline(always)]
161    pub fn is_adc0(&self) -> bool {
162        *self == SOURCESEL_A::ADC0
163    }
164    #[doc = "Checks if the value of the field is `USART0`"]
165    #[inline(always)]
166    pub fn is_usart0(&self) -> bool {
167        *self == SOURCESEL_A::USART0
168    }
169    #[doc = "Checks if the value of the field is `USART1`"]
170    #[inline(always)]
171    pub fn is_usart1(&self) -> bool {
172        *self == SOURCESEL_A::USART1
173    }
174    #[doc = "Checks if the value of the field is `USART2`"]
175    #[inline(always)]
176    pub fn is_usart2(&self) -> bool {
177        *self == SOURCESEL_A::USART2
178    }
179    #[doc = "Checks if the value of the field is `TIMER0`"]
180    #[inline(always)]
181    pub fn is_timer0(&self) -> bool {
182        *self == SOURCESEL_A::TIMER0
183    }
184    #[doc = "Checks if the value of the field is `TIMER1`"]
185    #[inline(always)]
186    pub fn is_timer1(&self) -> bool {
187        *self == SOURCESEL_A::TIMER1
188    }
189    #[doc = "Checks if the value of the field is `TIMER2`"]
190    #[inline(always)]
191    pub fn is_timer2(&self) -> bool {
192        *self == SOURCESEL_A::TIMER2
193    }
194    #[doc = "Checks if the value of the field is `TIMER3`"]
195    #[inline(always)]
196    pub fn is_timer3(&self) -> bool {
197        *self == SOURCESEL_A::TIMER3
198    }
199    #[doc = "Checks if the value of the field is `USB`"]
200    #[inline(always)]
201    pub fn is_usb(&self) -> bool {
202        *self == SOURCESEL_A::USB
203    }
204    #[doc = "Checks if the value of the field is `RTC`"]
205    #[inline(always)]
206    pub fn is_rtc(&self) -> bool {
207        *self == SOURCESEL_A::RTC
208    }
209    #[doc = "Checks if the value of the field is `UART0`"]
210    #[inline(always)]
211    pub fn is_uart0(&self) -> bool {
212        *self == SOURCESEL_A::UART0
213    }
214    #[doc = "Checks if the value of the field is `UART1`"]
215    #[inline(always)]
216    pub fn is_uart1(&self) -> bool {
217        *self == SOURCESEL_A::UART1
218    }
219    #[doc = "Checks if the value of the field is `GPIOL`"]
220    #[inline(always)]
221    pub fn is_gpiol(&self) -> bool {
222        *self == SOURCESEL_A::GPIOL
223    }
224    #[doc = "Checks if the value of the field is `GPIOH`"]
225    #[inline(always)]
226    pub fn is_gpioh(&self) -> bool {
227        *self == SOURCESEL_A::GPIOH
228    }
229    #[doc = "Checks if the value of the field is `LETIMER0`"]
230    #[inline(always)]
231    pub fn is_letimer0(&self) -> bool {
232        *self == SOURCESEL_A::LETIMER0
233    }
234    #[doc = "Checks if the value of the field is `BURTC`"]
235    #[inline(always)]
236    pub fn is_burtc(&self) -> bool {
237        *self == SOURCESEL_A::BURTC
238    }
239    #[doc = "Checks if the value of the field is `LESENSEL`"]
240    #[inline(always)]
241    pub fn is_lesensel(&self) -> bool {
242        *self == SOURCESEL_A::LESENSEL
243    }
244    #[doc = "Checks if the value of the field is `LESENSEH`"]
245    #[inline(always)]
246    pub fn is_lesenseh(&self) -> bool {
247        *self == SOURCESEL_A::LESENSEH
248    }
249    #[doc = "Checks if the value of the field is `LESENSED`"]
250    #[inline(always)]
251    pub fn is_lesensed(&self) -> bool {
252        *self == SOURCESEL_A::LESENSED
253    }
254}
255#[doc = "Field `SOURCESEL` writer - Source Select"]
256pub type SOURCESEL_W<'a, const O: u8> =
257    crate::FieldWriter<'a, u32, CH7_CTRL_SPEC, u8, SOURCESEL_A, 6, O>;
258impl<'a, const O: u8> SOURCESEL_W<'a, O> {
259    #[doc = "No source selected"]
260    #[inline(always)]
261    pub fn none(self) -> &'a mut W {
262        self.variant(SOURCESEL_A::NONE)
263    }
264    #[doc = "Voltage Comparator"]
265    #[inline(always)]
266    pub fn vcmp(self) -> &'a mut W {
267        self.variant(SOURCESEL_A::VCMP)
268    }
269    #[doc = "Analog Comparator 0"]
270    #[inline(always)]
271    pub fn acmp0(self) -> &'a mut W {
272        self.variant(SOURCESEL_A::ACMP0)
273    }
274    #[doc = "Analog Comparator 1"]
275    #[inline(always)]
276    pub fn acmp1(self) -> &'a mut W {
277        self.variant(SOURCESEL_A::ACMP1)
278    }
279    #[doc = "Digital to Analog Converter 0"]
280    #[inline(always)]
281    pub fn dac0(self) -> &'a mut W {
282        self.variant(SOURCESEL_A::DAC0)
283    }
284    #[doc = "Analog to Digital Converter 0"]
285    #[inline(always)]
286    pub fn adc0(self) -> &'a mut W {
287        self.variant(SOURCESEL_A::ADC0)
288    }
289    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
290    #[inline(always)]
291    pub fn usart0(self) -> &'a mut W {
292        self.variant(SOURCESEL_A::USART0)
293    }
294    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
295    #[inline(always)]
296    pub fn usart1(self) -> &'a mut W {
297        self.variant(SOURCESEL_A::USART1)
298    }
299    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
300    #[inline(always)]
301    pub fn usart2(self) -> &'a mut W {
302        self.variant(SOURCESEL_A::USART2)
303    }
304    #[doc = "Timer 0"]
305    #[inline(always)]
306    pub fn timer0(self) -> &'a mut W {
307        self.variant(SOURCESEL_A::TIMER0)
308    }
309    #[doc = "Timer 1"]
310    #[inline(always)]
311    pub fn timer1(self) -> &'a mut W {
312        self.variant(SOURCESEL_A::TIMER1)
313    }
314    #[doc = "Timer 2"]
315    #[inline(always)]
316    pub fn timer2(self) -> &'a mut W {
317        self.variant(SOURCESEL_A::TIMER2)
318    }
319    #[doc = "Timer 3"]
320    #[inline(always)]
321    pub fn timer3(self) -> &'a mut W {
322        self.variant(SOURCESEL_A::TIMER3)
323    }
324    #[doc = "Universal Serial Bus Interface"]
325    #[inline(always)]
326    pub fn usb(self) -> &'a mut W {
327        self.variant(SOURCESEL_A::USB)
328    }
329    #[doc = "Real-Time Counter"]
330    #[inline(always)]
331    pub fn rtc(self) -> &'a mut W {
332        self.variant(SOURCESEL_A::RTC)
333    }
334    #[doc = "Universal Asynchronous Receiver/Transmitter 0"]
335    #[inline(always)]
336    pub fn uart0(self) -> &'a mut W {
337        self.variant(SOURCESEL_A::UART0)
338    }
339    #[doc = "Universal Asynchronous Receiver/Transmitter 1"]
340    #[inline(always)]
341    pub fn uart1(self) -> &'a mut W {
342        self.variant(SOURCESEL_A::UART1)
343    }
344    #[doc = "General purpose Input/Output"]
345    #[inline(always)]
346    pub fn gpiol(self) -> &'a mut W {
347        self.variant(SOURCESEL_A::GPIOL)
348    }
349    #[doc = "General purpose Input/Output"]
350    #[inline(always)]
351    pub fn gpioh(self) -> &'a mut W {
352        self.variant(SOURCESEL_A::GPIOH)
353    }
354    #[doc = "Low Energy Timer 0"]
355    #[inline(always)]
356    pub fn letimer0(self) -> &'a mut W {
357        self.variant(SOURCESEL_A::LETIMER0)
358    }
359    #[doc = "Backup RTC"]
360    #[inline(always)]
361    pub fn burtc(self) -> &'a mut W {
362        self.variant(SOURCESEL_A::BURTC)
363    }
364    #[doc = "Low Energy Sensor Interface"]
365    #[inline(always)]
366    pub fn lesensel(self) -> &'a mut W {
367        self.variant(SOURCESEL_A::LESENSEL)
368    }
369    #[doc = "Low Energy Sensor Interface"]
370    #[inline(always)]
371    pub fn lesenseh(self) -> &'a mut W {
372        self.variant(SOURCESEL_A::LESENSEH)
373    }
374    #[doc = "Low Energy Sensor Interface"]
375    #[inline(always)]
376    pub fn lesensed(self) -> &'a mut W {
377        self.variant(SOURCESEL_A::LESENSED)
378    }
379}
380#[doc = "Field `EDSEL` reader - Edge Detect Select"]
381pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
382#[doc = "Edge Detect Select\n\nValue on reset: 0"]
383#[derive(Clone, Copy, Debug, PartialEq, Eq)]
384#[repr(u8)]
385pub enum EDSEL_A {
386    #[doc = "0: Signal is left as it is"]
387    OFF = 0,
388    #[doc = "1: A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
389    POSEDGE = 1,
390    #[doc = "2: A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
391    NEGEDGE = 2,
392    #[doc = "3: A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
393    BOTHEDGES = 3,
394}
395impl From<EDSEL_A> for u8 {
396    #[inline(always)]
397    fn from(variant: EDSEL_A) -> Self {
398        variant as _
399    }
400}
401impl EDSEL_R {
402    #[doc = "Get enumerated values variant"]
403    #[inline(always)]
404    pub fn variant(&self) -> EDSEL_A {
405        match self.bits {
406            0 => EDSEL_A::OFF,
407            1 => EDSEL_A::POSEDGE,
408            2 => EDSEL_A::NEGEDGE,
409            3 => EDSEL_A::BOTHEDGES,
410            _ => unreachable!(),
411        }
412    }
413    #[doc = "Checks if the value of the field is `OFF`"]
414    #[inline(always)]
415    pub fn is_off(&self) -> bool {
416        *self == EDSEL_A::OFF
417    }
418    #[doc = "Checks if the value of the field is `POSEDGE`"]
419    #[inline(always)]
420    pub fn is_posedge(&self) -> bool {
421        *self == EDSEL_A::POSEDGE
422    }
423    #[doc = "Checks if the value of the field is `NEGEDGE`"]
424    #[inline(always)]
425    pub fn is_negedge(&self) -> bool {
426        *self == EDSEL_A::NEGEDGE
427    }
428    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
429    #[inline(always)]
430    pub fn is_bothedges(&self) -> bool {
431        *self == EDSEL_A::BOTHEDGES
432    }
433}
434#[doc = "Field `EDSEL` writer - Edge Detect Select"]
435pub type EDSEL_W<'a, const O: u8> =
436    crate::FieldWriterSafe<'a, u32, CH7_CTRL_SPEC, u8, EDSEL_A, 2, O>;
437impl<'a, const O: u8> EDSEL_W<'a, O> {
438    #[doc = "Signal is left as it is"]
439    #[inline(always)]
440    pub fn off(self) -> &'a mut W {
441        self.variant(EDSEL_A::OFF)
442    }
443    #[doc = "A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
444    #[inline(always)]
445    pub fn posedge(self) -> &'a mut W {
446        self.variant(EDSEL_A::POSEDGE)
447    }
448    #[doc = "A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
449    #[inline(always)]
450    pub fn negedge(self) -> &'a mut W {
451        self.variant(EDSEL_A::NEGEDGE)
452    }
453    #[doc = "A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
454    #[inline(always)]
455    pub fn bothedges(self) -> &'a mut W {
456        self.variant(EDSEL_A::BOTHEDGES)
457    }
458}
459#[doc = "Field `ASYNC` reader - Asynchronous reflex"]
460pub type ASYNC_R = crate::BitReader<bool>;
461#[doc = "Field `ASYNC` writer - Asynchronous reflex"]
462pub type ASYNC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH7_CTRL_SPEC, bool, O>;
463impl R {
464    #[doc = "Bits 0:2 - Signal Select"]
465    #[inline(always)]
466    pub fn sigsel(&self) -> SIGSEL_R {
467        SIGSEL_R::new((self.bits & 7) as u8)
468    }
469    #[doc = "Bits 16:21 - Source Select"]
470    #[inline(always)]
471    pub fn sourcesel(&self) -> SOURCESEL_R {
472        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
473    }
474    #[doc = "Bits 24:25 - Edge Detect Select"]
475    #[inline(always)]
476    pub fn edsel(&self) -> EDSEL_R {
477        EDSEL_R::new(((self.bits >> 24) & 3) as u8)
478    }
479    #[doc = "Bit 28 - Asynchronous reflex"]
480    #[inline(always)]
481    pub fn async_(&self) -> ASYNC_R {
482        ASYNC_R::new(((self.bits >> 28) & 1) != 0)
483    }
484}
485impl W {
486    #[doc = "Bits 0:2 - Signal Select"]
487    #[inline(always)]
488    #[must_use]
489    pub fn sigsel(&mut self) -> SIGSEL_W<0> {
490        SIGSEL_W::new(self)
491    }
492    #[doc = "Bits 16:21 - Source Select"]
493    #[inline(always)]
494    #[must_use]
495    pub fn sourcesel(&mut self) -> SOURCESEL_W<16> {
496        SOURCESEL_W::new(self)
497    }
498    #[doc = "Bits 24:25 - Edge Detect Select"]
499    #[inline(always)]
500    #[must_use]
501    pub fn edsel(&mut self) -> EDSEL_W<24> {
502        EDSEL_W::new(self)
503    }
504    #[doc = "Bit 28 - Asynchronous reflex"]
505    #[inline(always)]
506    #[must_use]
507    pub fn async_(&mut self) -> ASYNC_W<28> {
508        ASYNC_W::new(self)
509    }
510    #[doc = "Writes raw bits to the register."]
511    #[inline(always)]
512    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
513        self.0.bits(bits);
514        self
515    }
516}
517#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch7_ctrl](index.html) module"]
518pub struct CH7_CTRL_SPEC;
519impl crate::RegisterSpec for CH7_CTRL_SPEC {
520    type Ux = u32;
521}
522#[doc = "`read()` method returns [ch7_ctrl::R](R) reader structure"]
523impl crate::Readable for CH7_CTRL_SPEC {
524    type Reader = R;
525}
526#[doc = "`write(|w| ..)` method takes [ch7_ctrl::W](W) writer structure"]
527impl crate::Writable for CH7_CTRL_SPEC {
528    type Writer = W;
529    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
530    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
531}
532#[doc = "`reset()` method sets CH7_CTRL to value 0"]
533impl crate::Resettable for CH7_CTRL_SPEC {
534    const RESET_VALUE: Self::Ux = 0;
535}
efm32gg_pac/efm32gg995/prs/ch7_ctrl.rs

efm32gg_pac/efm32gg995/prs/
ch7_ctrl.rs
