efm32gg_pac/efm32gg995/ebi/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MODE` reader - Mode"]
38pub type MODE_R = crate::FieldReader<u8, MODE_A>;
39#[doc = "Mode\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum MODE_A {
43    #[doc = "0: EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
44    D8A8 = 0,
45    #[doc = "1: EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
46    D16A16ALE = 1,
47    #[doc = "2: EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
48    D8A24ALE = 2,
49    #[doc = "3: EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
50    D16 = 3,
51}
52impl From<MODE_A> for u8 {
53    #[inline(always)]
54    fn from(variant: MODE_A) -> Self {
55        variant as _
56    }
57}
58impl MODE_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> MODE_A {
62        match self.bits {
63            0 => MODE_A::D8A8,
64            1 => MODE_A::D16A16ALE,
65            2 => MODE_A::D8A24ALE,
66            3 => MODE_A::D16,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `D8A8`"]
71    #[inline(always)]
72    pub fn is_d8a8(&self) -> bool {
73        *self == MODE_A::D8A8
74    }
75    #[doc = "Checks if the value of the field is `D16A16ALE`"]
76    #[inline(always)]
77    pub fn is_d16a16ale(&self) -> bool {
78        *self == MODE_A::D16A16ALE
79    }
80    #[doc = "Checks if the value of the field is `D8A24ALE`"]
81    #[inline(always)]
82    pub fn is_d8a24ale(&self) -> bool {
83        *self == MODE_A::D8A24ALE
84    }
85    #[doc = "Checks if the value of the field is `D16`"]
86    #[inline(always)]
87    pub fn is_d16(&self) -> bool {
88        *self == MODE_A::D16
89    }
90}
91#[doc = "Field `MODE` writer - Mode"]
92pub type MODE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, MODE_A, 2, O>;
93impl<'a, const O: u8> MODE_W<'a, O> {
94    #[doc = "EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
95    #[inline(always)]
96    pub fn d8a8(self) -> &'a mut W {
97        self.variant(MODE_A::D8A8)
98    }
99    #[doc = "EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
100    #[inline(always)]
101    pub fn d16a16ale(self) -> &'a mut W {
102        self.variant(MODE_A::D16A16ALE)
103    }
104    #[doc = "EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
105    #[inline(always)]
106    pub fn d8a24ale(self) -> &'a mut W {
107        self.variant(MODE_A::D8A24ALE)
108    }
109    #[doc = "EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
110    #[inline(always)]
111    pub fn d16(self) -> &'a mut W {
112        self.variant(MODE_A::D16)
113    }
114}
115#[doc = "Field `MODE1` reader - Mode 1"]
116pub type MODE1_R = crate::FieldReader<u8, MODE1_A>;
117#[doc = "Mode 1\n\nValue on reset: 0"]
118#[derive(Clone, Copy, Debug, PartialEq, Eq)]
119#[repr(u8)]
120pub enum MODE1_A {
121    #[doc = "0: EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
122    D8A8 = 0,
123    #[doc = "1: EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
124    D16A16ALE = 1,
125    #[doc = "2: EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
126    D8A24ALE = 2,
127    #[doc = "3: EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
128    D16 = 3,
129}
130impl From<MODE1_A> for u8 {
131    #[inline(always)]
132    fn from(variant: MODE1_A) -> Self {
133        variant as _
134    }
135}
136impl MODE1_R {
137    #[doc = "Get enumerated values variant"]
138    #[inline(always)]
139    pub fn variant(&self) -> MODE1_A {
140        match self.bits {
141            0 => MODE1_A::D8A8,
142            1 => MODE1_A::D16A16ALE,
143            2 => MODE1_A::D8A24ALE,
144            3 => MODE1_A::D16,
145            _ => unreachable!(),
146        }
147    }
148    #[doc = "Checks if the value of the field is `D8A8`"]
149    #[inline(always)]
150    pub fn is_d8a8(&self) -> bool {
151        *self == MODE1_A::D8A8
152    }
153    #[doc = "Checks if the value of the field is `D16A16ALE`"]
154    #[inline(always)]
155    pub fn is_d16a16ale(&self) -> bool {
156        *self == MODE1_A::D16A16ALE
157    }
158    #[doc = "Checks if the value of the field is `D8A24ALE`"]
159    #[inline(always)]
160    pub fn is_d8a24ale(&self) -> bool {
161        *self == MODE1_A::D8A24ALE
162    }
163    #[doc = "Checks if the value of the field is `D16`"]
164    #[inline(always)]
165    pub fn is_d16(&self) -> bool {
166        *self == MODE1_A::D16
167    }
168}
169#[doc = "Field `MODE1` writer - Mode 1"]
170pub type MODE1_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, MODE1_A, 2, O>;
171impl<'a, const O: u8> MODE1_W<'a, O> {
172    #[doc = "EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
173    #[inline(always)]
174    pub fn d8a8(self) -> &'a mut W {
175        self.variant(MODE1_A::D8A8)
176    }
177    #[doc = "EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
178    #[inline(always)]
179    pub fn d16a16ale(self) -> &'a mut W {
180        self.variant(MODE1_A::D16A16ALE)
181    }
182    #[doc = "EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
183    #[inline(always)]
184    pub fn d8a24ale(self) -> &'a mut W {
185        self.variant(MODE1_A::D8A24ALE)
186    }
187    #[doc = "EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
188    #[inline(always)]
189    pub fn d16(self) -> &'a mut W {
190        self.variant(MODE1_A::D16)
191    }
192}
193#[doc = "Field `MODE2` reader - Mode 2"]
194pub type MODE2_R = crate::FieldReader<u8, MODE2_A>;
195#[doc = "Mode 2\n\nValue on reset: 0"]
196#[derive(Clone, Copy, Debug, PartialEq, Eq)]
197#[repr(u8)]
198pub enum MODE2_A {
199    #[doc = "0: EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
200    D8A8 = 0,
201    #[doc = "1: EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
202    D16A16ALE = 1,
203    #[doc = "2: EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
204    D8A24ALE = 2,
205    #[doc = "3: EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
206    D16 = 3,
207}
208impl From<MODE2_A> for u8 {
209    #[inline(always)]
210    fn from(variant: MODE2_A) -> Self {
211        variant as _
212    }
213}
214impl MODE2_R {
215    #[doc = "Get enumerated values variant"]
216    #[inline(always)]
217    pub fn variant(&self) -> MODE2_A {
218        match self.bits {
219            0 => MODE2_A::D8A8,
220            1 => MODE2_A::D16A16ALE,
221            2 => MODE2_A::D8A24ALE,
222            3 => MODE2_A::D16,
223            _ => unreachable!(),
224        }
225    }
226    #[doc = "Checks if the value of the field is `D8A8`"]
227    #[inline(always)]
228    pub fn is_d8a8(&self) -> bool {
229        *self == MODE2_A::D8A8
230    }
231    #[doc = "Checks if the value of the field is `D16A16ALE`"]
232    #[inline(always)]
233    pub fn is_d16a16ale(&self) -> bool {
234        *self == MODE2_A::D16A16ALE
235    }
236    #[doc = "Checks if the value of the field is `D8A24ALE`"]
237    #[inline(always)]
238    pub fn is_d8a24ale(&self) -> bool {
239        *self == MODE2_A::D8A24ALE
240    }
241    #[doc = "Checks if the value of the field is `D16`"]
242    #[inline(always)]
243    pub fn is_d16(&self) -> bool {
244        *self == MODE2_A::D16
245    }
246}
247#[doc = "Field `MODE2` writer - Mode 2"]
248pub type MODE2_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, MODE2_A, 2, O>;
249impl<'a, const O: u8> MODE2_W<'a, O> {
250    #[doc = "EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
251    #[inline(always)]
252    pub fn d8a8(self) -> &'a mut W {
253        self.variant(MODE2_A::D8A8)
254    }
255    #[doc = "EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
256    #[inline(always)]
257    pub fn d16a16ale(self) -> &'a mut W {
258        self.variant(MODE2_A::D16A16ALE)
259    }
260    #[doc = "EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
261    #[inline(always)]
262    pub fn d8a24ale(self) -> &'a mut W {
263        self.variant(MODE2_A::D8A24ALE)
264    }
265    #[doc = "EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
266    #[inline(always)]
267    pub fn d16(self) -> &'a mut W {
268        self.variant(MODE2_A::D16)
269    }
270}
271#[doc = "Field `MODE3` reader - Mode 3"]
272pub type MODE3_R = crate::FieldReader<u8, MODE3_A>;
273#[doc = "Mode 3\n\nValue on reset: 0"]
274#[derive(Clone, Copy, Debug, PartialEq, Eq)]
275#[repr(u8)]
276pub enum MODE3_A {
277    #[doc = "0: EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
278    D8A8 = 0,
279    #[doc = "1: EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
280    D16A16ALE = 1,
281    #[doc = "2: EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
282    D8A24ALE = 2,
283    #[doc = "3: EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
284    D16 = 3,
285}
286impl From<MODE3_A> for u8 {
287    #[inline(always)]
288    fn from(variant: MODE3_A) -> Self {
289        variant as _
290    }
291}
292impl MODE3_R {
293    #[doc = "Get enumerated values variant"]
294    #[inline(always)]
295    pub fn variant(&self) -> MODE3_A {
296        match self.bits {
297            0 => MODE3_A::D8A8,
298            1 => MODE3_A::D16A16ALE,
299            2 => MODE3_A::D8A24ALE,
300            3 => MODE3_A::D16,
301            _ => unreachable!(),
302        }
303    }
304    #[doc = "Checks if the value of the field is `D8A8`"]
305    #[inline(always)]
306    pub fn is_d8a8(&self) -> bool {
307        *self == MODE3_A::D8A8
308    }
309    #[doc = "Checks if the value of the field is `D16A16ALE`"]
310    #[inline(always)]
311    pub fn is_d16a16ale(&self) -> bool {
312        *self == MODE3_A::D16A16ALE
313    }
314    #[doc = "Checks if the value of the field is `D8A24ALE`"]
315    #[inline(always)]
316    pub fn is_d8a24ale(&self) -> bool {
317        *self == MODE3_A::D8A24ALE
318    }
319    #[doc = "Checks if the value of the field is `D16`"]
320    #[inline(always)]
321    pub fn is_d16(&self) -> bool {
322        *self == MODE3_A::D16
323    }
324}
325#[doc = "Field `MODE3` writer - Mode 3"]
326pub type MODE3_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, MODE3_A, 2, O>;
327impl<'a, const O: u8> MODE3_W<'a, O> {
328    #[doc = "EBI_AD drives 8 bit data, 8 bit address, ALE not used. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
329    #[inline(always)]
330    pub fn d8a8(self) -> &'a mut W {
331        self.variant(MODE3_A::D8A8)
332    }
333    #[doc = "EBI_AD drives 16 bit data, 16 bit address, ALE is used for address latching. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
334    #[inline(always)]
335    pub fn d16a16ale(self) -> &'a mut W {
336        self.variant(MODE3_A::D16A16ALE)
337    }
338    #[doc = "EBI_AD drives 8 bit data, 24 bit address, ALE is used for address latching. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
339    #[inline(always)]
340    pub fn d8a24ale(self) -> &'a mut W {
341        self.variant(MODE3_A::D8A24ALE)
342    }
343    #[doc = "EBI_AD drives 16 bit data, ALE not used. Extended address bits can be enabled on EBI_A in the EBI_ROUTE register."]
344    #[inline(always)]
345    pub fn d16(self) -> &'a mut W {
346        self.variant(MODE3_A::D16)
347    }
348}
349#[doc = "Field `BANK0EN` reader - Bank 0 Enable"]
350pub type BANK0EN_R = crate::BitReader<bool>;
351#[doc = "Field `BANK0EN` writer - Bank 0 Enable"]
352pub type BANK0EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
353#[doc = "Field `BANK1EN` reader - Bank 1 Enable"]
354pub type BANK1EN_R = crate::BitReader<bool>;
355#[doc = "Field `BANK1EN` writer - Bank 1 Enable"]
356pub type BANK1EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
357#[doc = "Field `BANK2EN` reader - Bank 2 Enable"]
358pub type BANK2EN_R = crate::BitReader<bool>;
359#[doc = "Field `BANK2EN` writer - Bank 2 Enable"]
360pub type BANK2EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
361#[doc = "Field `BANK3EN` reader - Bank 3 Enable"]
362pub type BANK3EN_R = crate::BitReader<bool>;
363#[doc = "Field `BANK3EN` writer - Bank 3 Enable"]
364pub type BANK3EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
365#[doc = "Field `NOIDLE` reader - No idle cycle insertion on bank 0."]
366pub type NOIDLE_R = crate::BitReader<bool>;
367#[doc = "Field `NOIDLE` writer - No idle cycle insertion on bank 0."]
368pub type NOIDLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
369#[doc = "Field `NOIDLE1` reader - No idle cycle insertion on bank 1."]
370pub type NOIDLE1_R = crate::BitReader<bool>;
371#[doc = "Field `NOIDLE1` writer - No idle cycle insertion on bank 1."]
372pub type NOIDLE1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
373#[doc = "Field `NOIDLE2` reader - No idle cycle insertion on bank 2."]
374pub type NOIDLE2_R = crate::BitReader<bool>;
375#[doc = "Field `NOIDLE2` writer - No idle cycle insertion on bank 2."]
376pub type NOIDLE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
377#[doc = "Field `NOIDLE3` reader - No idle cycle insertion on bank 3."]
378pub type NOIDLE3_R = crate::BitReader<bool>;
379#[doc = "Field `NOIDLE3` writer - No idle cycle insertion on bank 3."]
380pub type NOIDLE3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
381#[doc = "Field `ARDYEN` reader - ARDY Enable"]
382pub type ARDYEN_R = crate::BitReader<bool>;
383#[doc = "Field `ARDYEN` writer - ARDY Enable"]
384pub type ARDYEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
385#[doc = "Field `ARDYTODIS` reader - ARDY Timeout Disable"]
386pub type ARDYTODIS_R = crate::BitReader<bool>;
387#[doc = "Field `ARDYTODIS` writer - ARDY Timeout Disable"]
388pub type ARDYTODIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
389#[doc = "Field `ARDY1EN` reader - ARDY Enable for bank 1"]
390pub type ARDY1EN_R = crate::BitReader<bool>;
391#[doc = "Field `ARDY1EN` writer - ARDY Enable for bank 1"]
392pub type ARDY1EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
393#[doc = "Field `ARDYTO1DIS` reader - ARDY Timeout Disable for bank 1"]
394pub type ARDYTO1DIS_R = crate::BitReader<bool>;
395#[doc = "Field `ARDYTO1DIS` writer - ARDY Timeout Disable for bank 1"]
396pub type ARDYTO1DIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
397#[doc = "Field `ARDY2EN` reader - ARDY Enable for bank 2"]
398pub type ARDY2EN_R = crate::BitReader<bool>;
399#[doc = "Field `ARDY2EN` writer - ARDY Enable for bank 2"]
400pub type ARDY2EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
401#[doc = "Field `ARDYTO2DIS` reader - ARDY Timeout Disable for bank 2"]
402pub type ARDYTO2DIS_R = crate::BitReader<bool>;
403#[doc = "Field `ARDYTO2DIS` writer - ARDY Timeout Disable for bank 2"]
404pub type ARDYTO2DIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
405#[doc = "Field `ARDY3EN` reader - ARDY Enable for bank 3"]
406pub type ARDY3EN_R = crate::BitReader<bool>;
407#[doc = "Field `ARDY3EN` writer - ARDY Enable for bank 3"]
408pub type ARDY3EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
409#[doc = "Field `ARDYTO3DIS` reader - ARDY Timeout Disable for bank 3"]
410pub type ARDYTO3DIS_R = crate::BitReader<bool>;
411#[doc = "Field `ARDYTO3DIS` writer - ARDY Timeout Disable for bank 3"]
412pub type ARDYTO3DIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
413#[doc = "Field `BL` reader - Byte Lane Enable for bank 0"]
414pub type BL_R = crate::BitReader<bool>;
415#[doc = "Field `BL` writer - Byte Lane Enable for bank 0"]
416pub type BL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
417#[doc = "Field `BL1` reader - Byte Lane Enable for bank 1"]
418pub type BL1_R = crate::BitReader<bool>;
419#[doc = "Field `BL1` writer - Byte Lane Enable for bank 1"]
420pub type BL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
421#[doc = "Field `BL2` reader - Byte Lane Enable for bank 2"]
422pub type BL2_R = crate::BitReader<bool>;
423#[doc = "Field `BL2` writer - Byte Lane Enable for bank 2"]
424pub type BL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
425#[doc = "Field `BL3` reader - Byte Lane Enable for bank 3"]
426pub type BL3_R = crate::BitReader<bool>;
427#[doc = "Field `BL3` writer - Byte Lane Enable for bank 3"]
428pub type BL3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
429#[doc = "Field `ITS` reader - Individual Timing Set, Line Polarity and Mode Definition Enable"]
430pub type ITS_R = crate::BitReader<bool>;
431#[doc = "Field `ITS` writer - Individual Timing Set, Line Polarity and Mode Definition Enable"]
432pub type ITS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
433#[doc = "Field `ALTMAP` reader - Alternative Address Map Enable"]
434pub type ALTMAP_R = crate::BitReader<bool>;
435#[doc = "Field `ALTMAP` writer - Alternative Address Map Enable"]
436pub type ALTMAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
437impl R {
438    #[doc = "Bits 0:1 - Mode"]
439    #[inline(always)]
440    pub fn mode(&self) -> MODE_R {
441        MODE_R::new((self.bits & 3) as u8)
442    }
443    #[doc = "Bits 2:3 - Mode 1"]
444    #[inline(always)]
445    pub fn mode1(&self) -> MODE1_R {
446        MODE1_R::new(((self.bits >> 2) & 3) as u8)
447    }
448    #[doc = "Bits 4:5 - Mode 2"]
449    #[inline(always)]
450    pub fn mode2(&self) -> MODE2_R {
451        MODE2_R::new(((self.bits >> 4) & 3) as u8)
452    }
453    #[doc = "Bits 6:7 - Mode 3"]
454    #[inline(always)]
455    pub fn mode3(&self) -> MODE3_R {
456        MODE3_R::new(((self.bits >> 6) & 3) as u8)
457    }
458    #[doc = "Bit 8 - Bank 0 Enable"]
459    #[inline(always)]
460    pub fn bank0en(&self) -> BANK0EN_R {
461        BANK0EN_R::new(((self.bits >> 8) & 1) != 0)
462    }
463    #[doc = "Bit 9 - Bank 1 Enable"]
464    #[inline(always)]
465    pub fn bank1en(&self) -> BANK1EN_R {
466        BANK1EN_R::new(((self.bits >> 9) & 1) != 0)
467    }
468    #[doc = "Bit 10 - Bank 2 Enable"]
469    #[inline(always)]
470    pub fn bank2en(&self) -> BANK2EN_R {
471        BANK2EN_R::new(((self.bits >> 10) & 1) != 0)
472    }
473    #[doc = "Bit 11 - Bank 3 Enable"]
474    #[inline(always)]
475    pub fn bank3en(&self) -> BANK3EN_R {
476        BANK3EN_R::new(((self.bits >> 11) & 1) != 0)
477    }
478    #[doc = "Bit 12 - No idle cycle insertion on bank 0."]
479    #[inline(always)]
480    pub fn noidle(&self) -> NOIDLE_R {
481        NOIDLE_R::new(((self.bits >> 12) & 1) != 0)
482    }
483    #[doc = "Bit 13 - No idle cycle insertion on bank 1."]
484    #[inline(always)]
485    pub fn noidle1(&self) -> NOIDLE1_R {
486        NOIDLE1_R::new(((self.bits >> 13) & 1) != 0)
487    }
488    #[doc = "Bit 14 - No idle cycle insertion on bank 2."]
489    #[inline(always)]
490    pub fn noidle2(&self) -> NOIDLE2_R {
491        NOIDLE2_R::new(((self.bits >> 14) & 1) != 0)
492    }
493    #[doc = "Bit 15 - No idle cycle insertion on bank 3."]
494    #[inline(always)]
495    pub fn noidle3(&self) -> NOIDLE3_R {
496        NOIDLE3_R::new(((self.bits >> 15) & 1) != 0)
497    }
498    #[doc = "Bit 16 - ARDY Enable"]
499    #[inline(always)]
500    pub fn ardyen(&self) -> ARDYEN_R {
501        ARDYEN_R::new(((self.bits >> 16) & 1) != 0)
502    }
503    #[doc = "Bit 17 - ARDY Timeout Disable"]
504    #[inline(always)]
505    pub fn ardytodis(&self) -> ARDYTODIS_R {
506        ARDYTODIS_R::new(((self.bits >> 17) & 1) != 0)
507    }
508    #[doc = "Bit 18 - ARDY Enable for bank 1"]
509    #[inline(always)]
510    pub fn ardy1en(&self) -> ARDY1EN_R {
511        ARDY1EN_R::new(((self.bits >> 18) & 1) != 0)
512    }
513    #[doc = "Bit 19 - ARDY Timeout Disable for bank 1"]
514    #[inline(always)]
515    pub fn ardyto1dis(&self) -> ARDYTO1DIS_R {
516        ARDYTO1DIS_R::new(((self.bits >> 19) & 1) != 0)
517    }
518    #[doc = "Bit 20 - ARDY Enable for bank 2"]
519    #[inline(always)]
520    pub fn ardy2en(&self) -> ARDY2EN_R {
521        ARDY2EN_R::new(((self.bits >> 20) & 1) != 0)
522    }
523    #[doc = "Bit 21 - ARDY Timeout Disable for bank 2"]
524    #[inline(always)]
525    pub fn ardyto2dis(&self) -> ARDYTO2DIS_R {
526        ARDYTO2DIS_R::new(((self.bits >> 21) & 1) != 0)
527    }
528    #[doc = "Bit 22 - ARDY Enable for bank 3"]
529    #[inline(always)]
530    pub fn ardy3en(&self) -> ARDY3EN_R {
531        ARDY3EN_R::new(((self.bits >> 22) & 1) != 0)
532    }
533    #[doc = "Bit 23 - ARDY Timeout Disable for bank 3"]
534    #[inline(always)]
535    pub fn ardyto3dis(&self) -> ARDYTO3DIS_R {
536        ARDYTO3DIS_R::new(((self.bits >> 23) & 1) != 0)
537    }
538    #[doc = "Bit 24 - Byte Lane Enable for bank 0"]
539    #[inline(always)]
540    pub fn bl(&self) -> BL_R {
541        BL_R::new(((self.bits >> 24) & 1) != 0)
542    }
543    #[doc = "Bit 25 - Byte Lane Enable for bank 1"]
544    #[inline(always)]
545    pub fn bl1(&self) -> BL1_R {
546        BL1_R::new(((self.bits >> 25) & 1) != 0)
547    }
548    #[doc = "Bit 26 - Byte Lane Enable for bank 2"]
549    #[inline(always)]
550    pub fn bl2(&self) -> BL2_R {
551        BL2_R::new(((self.bits >> 26) & 1) != 0)
552    }
553    #[doc = "Bit 27 - Byte Lane Enable for bank 3"]
554    #[inline(always)]
555    pub fn bl3(&self) -> BL3_R {
556        BL3_R::new(((self.bits >> 27) & 1) != 0)
557    }
558    #[doc = "Bit 30 - Individual Timing Set, Line Polarity and Mode Definition Enable"]
559    #[inline(always)]
560    pub fn its(&self) -> ITS_R {
561        ITS_R::new(((self.bits >> 30) & 1) != 0)
562    }
563    #[doc = "Bit 31 - Alternative Address Map Enable"]
564    #[inline(always)]
565    pub fn altmap(&self) -> ALTMAP_R {
566        ALTMAP_R::new(((self.bits >> 31) & 1) != 0)
567    }
568}
569impl W {
570    #[doc = "Bits 0:1 - Mode"]
571    #[inline(always)]
572    #[must_use]
573    pub fn mode(&mut self) -> MODE_W<0> {
574        MODE_W::new(self)
575    }
576    #[doc = "Bits 2:3 - Mode 1"]
577    #[inline(always)]
578    #[must_use]
579    pub fn mode1(&mut self) -> MODE1_W<2> {
580        MODE1_W::new(self)
581    }
582    #[doc = "Bits 4:5 - Mode 2"]
583    #[inline(always)]
584    #[must_use]
585    pub fn mode2(&mut self) -> MODE2_W<4> {
586        MODE2_W::new(self)
587    }
588    #[doc = "Bits 6:7 - Mode 3"]
589    #[inline(always)]
590    #[must_use]
591    pub fn mode3(&mut self) -> MODE3_W<6> {
592        MODE3_W::new(self)
593    }
594    #[doc = "Bit 8 - Bank 0 Enable"]
595    #[inline(always)]
596    #[must_use]
597    pub fn bank0en(&mut self) -> BANK0EN_W<8> {
598        BANK0EN_W::new(self)
599    }
600    #[doc = "Bit 9 - Bank 1 Enable"]
601    #[inline(always)]
602    #[must_use]
603    pub fn bank1en(&mut self) -> BANK1EN_W<9> {
604        BANK1EN_W::new(self)
605    }
606    #[doc = "Bit 10 - Bank 2 Enable"]
607    #[inline(always)]
608    #[must_use]
609    pub fn bank2en(&mut self) -> BANK2EN_W<10> {
610        BANK2EN_W::new(self)
611    }
612    #[doc = "Bit 11 - Bank 3 Enable"]
613    #[inline(always)]
614    #[must_use]
615    pub fn bank3en(&mut self) -> BANK3EN_W<11> {
616        BANK3EN_W::new(self)
617    }
618    #[doc = "Bit 12 - No idle cycle insertion on bank 0."]
619    #[inline(always)]
620    #[must_use]
621    pub fn noidle(&mut self) -> NOIDLE_W<12> {
622        NOIDLE_W::new(self)
623    }
624    #[doc = "Bit 13 - No idle cycle insertion on bank 1."]
625    #[inline(always)]
626    #[must_use]
627    pub fn noidle1(&mut self) -> NOIDLE1_W<13> {
628        NOIDLE1_W::new(self)
629    }
630    #[doc = "Bit 14 - No idle cycle insertion on bank 2."]
631    #[inline(always)]
632    #[must_use]
633    pub fn noidle2(&mut self) -> NOIDLE2_W<14> {
634        NOIDLE2_W::new(self)
635    }
636    #[doc = "Bit 15 - No idle cycle insertion on bank 3."]
637    #[inline(always)]
638    #[must_use]
639    pub fn noidle3(&mut self) -> NOIDLE3_W<15> {
640        NOIDLE3_W::new(self)
641    }
642    #[doc = "Bit 16 - ARDY Enable"]
643    #[inline(always)]
644    #[must_use]
645    pub fn ardyen(&mut self) -> ARDYEN_W<16> {
646        ARDYEN_W::new(self)
647    }
648    #[doc = "Bit 17 - ARDY Timeout Disable"]
649    #[inline(always)]
650    #[must_use]
651    pub fn ardytodis(&mut self) -> ARDYTODIS_W<17> {
652        ARDYTODIS_W::new(self)
653    }
654    #[doc = "Bit 18 - ARDY Enable for bank 1"]
655    #[inline(always)]
656    #[must_use]
657    pub fn ardy1en(&mut self) -> ARDY1EN_W<18> {
658        ARDY1EN_W::new(self)
659    }
660    #[doc = "Bit 19 - ARDY Timeout Disable for bank 1"]
661    #[inline(always)]
662    #[must_use]
663    pub fn ardyto1dis(&mut self) -> ARDYTO1DIS_W<19> {
664        ARDYTO1DIS_W::new(self)
665    }
666    #[doc = "Bit 20 - ARDY Enable for bank 2"]
667    #[inline(always)]
668    #[must_use]
669    pub fn ardy2en(&mut self) -> ARDY2EN_W<20> {
670        ARDY2EN_W::new(self)
671    }
672    #[doc = "Bit 21 - ARDY Timeout Disable for bank 2"]
673    #[inline(always)]
674    #[must_use]
675    pub fn ardyto2dis(&mut self) -> ARDYTO2DIS_W<21> {
676        ARDYTO2DIS_W::new(self)
677    }
678    #[doc = "Bit 22 - ARDY Enable for bank 3"]
679    #[inline(always)]
680    #[must_use]
681    pub fn ardy3en(&mut self) -> ARDY3EN_W<22> {
682        ARDY3EN_W::new(self)
683    }
684    #[doc = "Bit 23 - ARDY Timeout Disable for bank 3"]
685    #[inline(always)]
686    #[must_use]
687    pub fn ardyto3dis(&mut self) -> ARDYTO3DIS_W<23> {
688        ARDYTO3DIS_W::new(self)
689    }
690    #[doc = "Bit 24 - Byte Lane Enable for bank 0"]
691    #[inline(always)]
692    #[must_use]
693    pub fn bl(&mut self) -> BL_W<24> {
694        BL_W::new(self)
695    }
696    #[doc = "Bit 25 - Byte Lane Enable for bank 1"]
697    #[inline(always)]
698    #[must_use]
699    pub fn bl1(&mut self) -> BL1_W<25> {
700        BL1_W::new(self)
701    }
702    #[doc = "Bit 26 - Byte Lane Enable for bank 2"]
703    #[inline(always)]
704    #[must_use]
705    pub fn bl2(&mut self) -> BL2_W<26> {
706        BL2_W::new(self)
707    }
708    #[doc = "Bit 27 - Byte Lane Enable for bank 3"]
709    #[inline(always)]
710    #[must_use]
711    pub fn bl3(&mut self) -> BL3_W<27> {
712        BL3_W::new(self)
713    }
714    #[doc = "Bit 30 - Individual Timing Set, Line Polarity and Mode Definition Enable"]
715    #[inline(always)]
716    #[must_use]
717    pub fn its(&mut self) -> ITS_W<30> {
718        ITS_W::new(self)
719    }
720    #[doc = "Bit 31 - Alternative Address Map Enable"]
721    #[inline(always)]
722    #[must_use]
723    pub fn altmap(&mut self) -> ALTMAP_W<31> {
724        ALTMAP_W::new(self)
725    }
726    #[doc = "Writes raw bits to the register."]
727    #[inline(always)]
728    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
729        self.0.bits(bits);
730        self
731    }
732}
733#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
734pub struct CTRL_SPEC;
735impl crate::RegisterSpec for CTRL_SPEC {
736    type Ux = u32;
737}
738#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
739impl crate::Readable for CTRL_SPEC {
740    type Reader = R;
741}
742#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
743impl crate::Writable for CTRL_SPEC {
744    type Writer = W;
745    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
746    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
747}
748#[doc = "`reset()` method sets CTRL to value 0"]
749impl crate::Resettable for CTRL_SPEC {
750    const RESET_VALUE: Self::Ux = 0;
751}
efm32gg_pac/efm32gg995/ebi/ctrl.rs

efm32gg_pac/efm32gg995/ebi/
ctrl.rs
