efm32gg_pac/efm32gg995/dma/
chens.rs

1#[doc = "Register `CHENS` writer"]
2pub struct W(crate::W<CHENS_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<CHENS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<CHENS_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<CHENS_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `CH0ENS` writer - Channel 0 Enable Set"]
23pub type CH0ENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, O>;
24#[doc = "Field `CH1ENS` writer - Channel 1 Enable Set"]
25pub type CH1ENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, O>;
26#[doc = "Field `CH2ENS` writer - Channel 2 Enable Set"]
27pub type CH2ENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, O>;
28#[doc = "Field `CH3ENS` writer - Channel 3 Enable Set"]
29pub type CH3ENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, O>;
30#[doc = "Field `CH4ENS` writer - Channel 4 Enable Set"]
31pub type CH4ENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, O>;
32#[doc = "Field `CH5ENS` writer - Channel 5 Enable Set"]
33pub type CH5ENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, O>;
34#[doc = "Field `CH6ENS` writer - Channel 6 Enable Set"]
35pub type CH6ENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, O>;
36#[doc = "Field `CH7ENS` writer - Channel 7 Enable Set"]
37pub type CH7ENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, O>;
38#[doc = "Field `CH8ENS` writer - Channel 8 Enable Set"]
39pub type CH8ENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, O>;
40#[doc = "Field `CH9ENS` writer - Channel 9 Enable Set"]
41pub type CH9ENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, O>;
42#[doc = "Field `CH10ENS` writer - Channel 10 Enable Set"]
43pub type CH10ENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, O>;
44#[doc = "Field `CH11ENS` writer - Channel 11 Enable Set"]
45pub type CH11ENS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENS_SPEC, bool, O>;
46impl W {
47    #[doc = "Bit 0 - Channel 0 Enable Set"]
48    #[inline(always)]
49    #[must_use]
50    pub fn ch0ens(&mut self) -> CH0ENS_W<0> {
51        CH0ENS_W::new(self)
52    }
53    #[doc = "Bit 1 - Channel 1 Enable Set"]
54    #[inline(always)]
55    #[must_use]
56    pub fn ch1ens(&mut self) -> CH1ENS_W<1> {
57        CH1ENS_W::new(self)
58    }
59    #[doc = "Bit 2 - Channel 2 Enable Set"]
60    #[inline(always)]
61    #[must_use]
62    pub fn ch2ens(&mut self) -> CH2ENS_W<2> {
63        CH2ENS_W::new(self)
64    }
65    #[doc = "Bit 3 - Channel 3 Enable Set"]
66    #[inline(always)]
67    #[must_use]
68    pub fn ch3ens(&mut self) -> CH3ENS_W<3> {
69        CH3ENS_W::new(self)
70    }
71    #[doc = "Bit 4 - Channel 4 Enable Set"]
72    #[inline(always)]
73    #[must_use]
74    pub fn ch4ens(&mut self) -> CH4ENS_W<4> {
75        CH4ENS_W::new(self)
76    }
77    #[doc = "Bit 5 - Channel 5 Enable Set"]
78    #[inline(always)]
79    #[must_use]
80    pub fn ch5ens(&mut self) -> CH5ENS_W<5> {
81        CH5ENS_W::new(self)
82    }
83    #[doc = "Bit 6 - Channel 6 Enable Set"]
84    #[inline(always)]
85    #[must_use]
86    pub fn ch6ens(&mut self) -> CH6ENS_W<6> {
87        CH6ENS_W::new(self)
88    }
89    #[doc = "Bit 7 - Channel 7 Enable Set"]
90    #[inline(always)]
91    #[must_use]
92    pub fn ch7ens(&mut self) -> CH7ENS_W<7> {
93        CH7ENS_W::new(self)
94    }
95    #[doc = "Bit 8 - Channel 8 Enable Set"]
96    #[inline(always)]
97    #[must_use]
98    pub fn ch8ens(&mut self) -> CH8ENS_W<8> {
99        CH8ENS_W::new(self)
100    }
101    #[doc = "Bit 9 - Channel 9 Enable Set"]
102    #[inline(always)]
103    #[must_use]
104    pub fn ch9ens(&mut self) -> CH9ENS_W<9> {
105        CH9ENS_W::new(self)
106    }
107    #[doc = "Bit 10 - Channel 10 Enable Set"]
108    #[inline(always)]
109    #[must_use]
110    pub fn ch10ens(&mut self) -> CH10ENS_W<10> {
111        CH10ENS_W::new(self)
112    }
113    #[doc = "Bit 11 - Channel 11 Enable Set"]
114    #[inline(always)]
115    #[must_use]
116    pub fn ch11ens(&mut self) -> CH11ENS_W<11> {
117        CH11ENS_W::new(self)
118    }
119    #[doc = "Writes raw bits to the register."]
120    #[inline(always)]
121    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
122        self.0.bits(bits);
123        self
124    }
125}
126#[doc = "Channel Enable Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chens](index.html) module"]
127pub struct CHENS_SPEC;
128impl crate::RegisterSpec for CHENS_SPEC {
129    type Ux = u32;
130}
131#[doc = "`write(|w| ..)` method takes [chens::W](W) writer structure"]
132impl crate::Writable for CHENS_SPEC {
133    type Writer = W;
134    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
135    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
136}
137#[doc = "`reset()` method sets CHENS to value 0"]
138impl crate::Resettable for CHENS_SPEC {
139    const RESET_VALUE: Self::Ux = 0;
140}
efm32gg_pac/efm32gg995/dma/chens.rs

efm32gg_pac/efm32gg995/dma/
chens.rs
