efm32gg_pac/efm32gg995/dma/
chenc.rs

1#[doc = "Register `CHENC` writer"]
2pub struct W(crate::W<CHENC_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<CHENC_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<CHENC_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<CHENC_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `CH0ENC` writer - Channel 0 Enable Clear"]
23pub type CH0ENC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, O>;
24#[doc = "Field `CH1ENC` writer - Channel 1 Enable Clear"]
25pub type CH1ENC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, O>;
26#[doc = "Field `CH2ENC` writer - Channel 2 Enable Clear"]
27pub type CH2ENC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, O>;
28#[doc = "Field `CH3ENC` writer - Channel 3 Enable Clear"]
29pub type CH3ENC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, O>;
30#[doc = "Field `CH4ENC` writer - Channel 4 Enable Clear"]
31pub type CH4ENC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, O>;
32#[doc = "Field `CH5ENC` writer - Channel 5 Enable Clear"]
33pub type CH5ENC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, O>;
34#[doc = "Field `CH6ENC` writer - Channel 6 Enable Clear"]
35pub type CH6ENC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, O>;
36#[doc = "Field `CH7ENC` writer - Channel 7 Enable Clear"]
37pub type CH7ENC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, O>;
38#[doc = "Field `CH8ENC` writer - Channel 8 Enable Clear"]
39pub type CH8ENC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, O>;
40#[doc = "Field `CH9ENC` writer - Channel 9 Enable Clear"]
41pub type CH9ENC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, O>;
42#[doc = "Field `CH10ENC` writer - Channel 10 Enable Clear"]
43pub type CH10ENC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, O>;
44#[doc = "Field `CH11ENC` writer - Channel 11 Enable Clear"]
45pub type CH11ENC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHENC_SPEC, bool, O>;
46impl W {
47    #[doc = "Bit 0 - Channel 0 Enable Clear"]
48    #[inline(always)]
49    #[must_use]
50    pub fn ch0enc(&mut self) -> CH0ENC_W<0> {
51        CH0ENC_W::new(self)
52    }
53    #[doc = "Bit 1 - Channel 1 Enable Clear"]
54    #[inline(always)]
55    #[must_use]
56    pub fn ch1enc(&mut self) -> CH1ENC_W<1> {
57        CH1ENC_W::new(self)
58    }
59    #[doc = "Bit 2 - Channel 2 Enable Clear"]
60    #[inline(always)]
61    #[must_use]
62    pub fn ch2enc(&mut self) -> CH2ENC_W<2> {
63        CH2ENC_W::new(self)
64    }
65    #[doc = "Bit 3 - Channel 3 Enable Clear"]
66    #[inline(always)]
67    #[must_use]
68    pub fn ch3enc(&mut self) -> CH3ENC_W<3> {
69        CH3ENC_W::new(self)
70    }
71    #[doc = "Bit 4 - Channel 4 Enable Clear"]
72    #[inline(always)]
73    #[must_use]
74    pub fn ch4enc(&mut self) -> CH4ENC_W<4> {
75        CH4ENC_W::new(self)
76    }
77    #[doc = "Bit 5 - Channel 5 Enable Clear"]
78    #[inline(always)]
79    #[must_use]
80    pub fn ch5enc(&mut self) -> CH5ENC_W<5> {
81        CH5ENC_W::new(self)
82    }
83    #[doc = "Bit 6 - Channel 6 Enable Clear"]
84    #[inline(always)]
85    #[must_use]
86    pub fn ch6enc(&mut self) -> CH6ENC_W<6> {
87        CH6ENC_W::new(self)
88    }
89    #[doc = "Bit 7 - Channel 7 Enable Clear"]
90    #[inline(always)]
91    #[must_use]
92    pub fn ch7enc(&mut self) -> CH7ENC_W<7> {
93        CH7ENC_W::new(self)
94    }
95    #[doc = "Bit 8 - Channel 8 Enable Clear"]
96    #[inline(always)]
97    #[must_use]
98    pub fn ch8enc(&mut self) -> CH8ENC_W<8> {
99        CH8ENC_W::new(self)
100    }
101    #[doc = "Bit 9 - Channel 9 Enable Clear"]
102    #[inline(always)]
103    #[must_use]
104    pub fn ch9enc(&mut self) -> CH9ENC_W<9> {
105        CH9ENC_W::new(self)
106    }
107    #[doc = "Bit 10 - Channel 10 Enable Clear"]
108    #[inline(always)]
109    #[must_use]
110    pub fn ch10enc(&mut self) -> CH10ENC_W<10> {
111        CH10ENC_W::new(self)
112    }
113    #[doc = "Bit 11 - Channel 11 Enable Clear"]
114    #[inline(always)]
115    #[must_use]
116    pub fn ch11enc(&mut self) -> CH11ENC_W<11> {
117        CH11ENC_W::new(self)
118    }
119    #[doc = "Writes raw bits to the register."]
120    #[inline(always)]
121    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
122        self.0.bits(bits);
123        self
124    }
125}
126#[doc = "Channel Enable Clear Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chenc](index.html) module"]
127pub struct CHENC_SPEC;
128impl crate::RegisterSpec for CHENC_SPEC {
129    type Ux = u32;
130}
131#[doc = "`write(|w| ..)` method takes [chenc::W](W) writer structure"]
132impl crate::Writable for CHENC_SPEC {
133    type Writer = W;
134    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
135    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
136}
137#[doc = "`reset()` method sets CHENC to value 0"]
138impl crate::Resettable for CHENC_SPEC {
139    const RESET_VALUE: Self::Ux = 0;
140}
efm32gg_pac/efm32gg995/dma/chenc.rs

efm32gg_pac/efm32gg995/dma/
chenc.rs
