efm32gg_pac/efm32gg230/vcmp/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `EN` reader - Voltage Supply Comparator Enable"]
38pub type EN_R = crate::BitReader<bool>;
39#[doc = "Field `EN` writer - Voltage Supply Comparator Enable"]
40pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
41#[doc = "Field `INACTVAL` reader - Inactive Value"]
42pub type INACTVAL_R = crate::BitReader<bool>;
43#[doc = "Field `INACTVAL` writer - Inactive Value"]
44pub type INACTVAL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
45#[doc = "Field `HYSTEN` reader - Hysteresis Enable"]
46pub type HYSTEN_R = crate::BitReader<bool>;
47#[doc = "Field `HYSTEN` writer - Hysteresis Enable"]
48pub type HYSTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
49#[doc = "Field `WARMTIME` reader - Warm-Up Time"]
50pub type WARMTIME_R = crate::FieldReader<u8, WARMTIME_A>;
51#[doc = "Warm-Up Time\n\nValue on reset: 0"]
52#[derive(Clone, Copy, Debug, PartialEq, Eq)]
53#[repr(u8)]
54pub enum WARMTIME_A {
55    #[doc = "0: 4 HFPERCLK cycles"]
56    _4CYCLES = 0,
57    #[doc = "1: 8 HFPERCLK cycles"]
58    _8CYCLES = 1,
59    #[doc = "2: 16 HFPERCLK cycles"]
60    _16CYCLES = 2,
61    #[doc = "3: 32 HFPERCLK cycles"]
62    _32CYCLES = 3,
63    #[doc = "4: 64 HFPERCLK cycles"]
64    _64CYCLES = 4,
65    #[doc = "5: 128 HFPERCLK cycles"]
66    _128CYCLES = 5,
67    #[doc = "6: 256 HFPERCLK cycles"]
68    _256CYCLES = 6,
69    #[doc = "7: 512 HFPERCLK cycles"]
70    _512CYCLES = 7,
71}
72impl From<WARMTIME_A> for u8 {
73    #[inline(always)]
74    fn from(variant: WARMTIME_A) -> Self {
75        variant as _
76    }
77}
78impl WARMTIME_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub fn variant(&self) -> WARMTIME_A {
82        match self.bits {
83            0 => WARMTIME_A::_4CYCLES,
84            1 => WARMTIME_A::_8CYCLES,
85            2 => WARMTIME_A::_16CYCLES,
86            3 => WARMTIME_A::_32CYCLES,
87            4 => WARMTIME_A::_64CYCLES,
88            5 => WARMTIME_A::_128CYCLES,
89            6 => WARMTIME_A::_256CYCLES,
90            7 => WARMTIME_A::_512CYCLES,
91            _ => unreachable!(),
92        }
93    }
94    #[doc = "Checks if the value of the field is `_4CYCLES`"]
95    #[inline(always)]
96    pub fn is_4cycles(&self) -> bool {
97        *self == WARMTIME_A::_4CYCLES
98    }
99    #[doc = "Checks if the value of the field is `_8CYCLES`"]
100    #[inline(always)]
101    pub fn is_8cycles(&self) -> bool {
102        *self == WARMTIME_A::_8CYCLES
103    }
104    #[doc = "Checks if the value of the field is `_16CYCLES`"]
105    #[inline(always)]
106    pub fn is_16cycles(&self) -> bool {
107        *self == WARMTIME_A::_16CYCLES
108    }
109    #[doc = "Checks if the value of the field is `_32CYCLES`"]
110    #[inline(always)]
111    pub fn is_32cycles(&self) -> bool {
112        *self == WARMTIME_A::_32CYCLES
113    }
114    #[doc = "Checks if the value of the field is `_64CYCLES`"]
115    #[inline(always)]
116    pub fn is_64cycles(&self) -> bool {
117        *self == WARMTIME_A::_64CYCLES
118    }
119    #[doc = "Checks if the value of the field is `_128CYCLES`"]
120    #[inline(always)]
121    pub fn is_128cycles(&self) -> bool {
122        *self == WARMTIME_A::_128CYCLES
123    }
124    #[doc = "Checks if the value of the field is `_256CYCLES`"]
125    #[inline(always)]
126    pub fn is_256cycles(&self) -> bool {
127        *self == WARMTIME_A::_256CYCLES
128    }
129    #[doc = "Checks if the value of the field is `_512CYCLES`"]
130    #[inline(always)]
131    pub fn is_512cycles(&self) -> bool {
132        *self == WARMTIME_A::_512CYCLES
133    }
134}
135#[doc = "Field `WARMTIME` writer - Warm-Up Time"]
136pub type WARMTIME_W<'a, const O: u8> =
137    crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, WARMTIME_A, 3, O>;
138impl<'a, const O: u8> WARMTIME_W<'a, O> {
139    #[doc = "4 HFPERCLK cycles"]
140    #[inline(always)]
141    pub fn _4cycles(self) -> &'a mut W {
142        self.variant(WARMTIME_A::_4CYCLES)
143    }
144    #[doc = "8 HFPERCLK cycles"]
145    #[inline(always)]
146    pub fn _8cycles(self) -> &'a mut W {
147        self.variant(WARMTIME_A::_8CYCLES)
148    }
149    #[doc = "16 HFPERCLK cycles"]
150    #[inline(always)]
151    pub fn _16cycles(self) -> &'a mut W {
152        self.variant(WARMTIME_A::_16CYCLES)
153    }
154    #[doc = "32 HFPERCLK cycles"]
155    #[inline(always)]
156    pub fn _32cycles(self) -> &'a mut W {
157        self.variant(WARMTIME_A::_32CYCLES)
158    }
159    #[doc = "64 HFPERCLK cycles"]
160    #[inline(always)]
161    pub fn _64cycles(self) -> &'a mut W {
162        self.variant(WARMTIME_A::_64CYCLES)
163    }
164    #[doc = "128 HFPERCLK cycles"]
165    #[inline(always)]
166    pub fn _128cycles(self) -> &'a mut W {
167        self.variant(WARMTIME_A::_128CYCLES)
168    }
169    #[doc = "256 HFPERCLK cycles"]
170    #[inline(always)]
171    pub fn _256cycles(self) -> &'a mut W {
172        self.variant(WARMTIME_A::_256CYCLES)
173    }
174    #[doc = "512 HFPERCLK cycles"]
175    #[inline(always)]
176    pub fn _512cycles(self) -> &'a mut W {
177        self.variant(WARMTIME_A::_512CYCLES)
178    }
179}
180#[doc = "Field `IRISE` reader - Rising Edge Interrupt Sense"]
181pub type IRISE_R = crate::BitReader<bool>;
182#[doc = "Field `IRISE` writer - Rising Edge Interrupt Sense"]
183pub type IRISE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
184#[doc = "Field `IFALL` reader - Falling Edge Interrupt Sense"]
185pub type IFALL_R = crate::BitReader<bool>;
186#[doc = "Field `IFALL` writer - Falling Edge Interrupt Sense"]
187pub type IFALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
188#[doc = "Field `BIASPROG` reader - VCMP Bias Programming Value"]
189pub type BIASPROG_R = crate::FieldReader<u8, u8>;
190#[doc = "Field `BIASPROG` writer - VCMP Bias Programming Value"]
191pub type BIASPROG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, u8, 4, O>;
192#[doc = "Field `HALFBIAS` reader - Half Bias Current"]
193pub type HALFBIAS_R = crate::BitReader<bool>;
194#[doc = "Field `HALFBIAS` writer - Half Bias Current"]
195pub type HALFBIAS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
196impl R {
197    #[doc = "Bit 0 - Voltage Supply Comparator Enable"]
198    #[inline(always)]
199    pub fn en(&self) -> EN_R {
200        EN_R::new((self.bits & 1) != 0)
201    }
202    #[doc = "Bit 2 - Inactive Value"]
203    #[inline(always)]
204    pub fn inactval(&self) -> INACTVAL_R {
205        INACTVAL_R::new(((self.bits >> 2) & 1) != 0)
206    }
207    #[doc = "Bit 4 - Hysteresis Enable"]
208    #[inline(always)]
209    pub fn hysten(&self) -> HYSTEN_R {
210        HYSTEN_R::new(((self.bits >> 4) & 1) != 0)
211    }
212    #[doc = "Bits 8:10 - Warm-Up Time"]
213    #[inline(always)]
214    pub fn warmtime(&self) -> WARMTIME_R {
215        WARMTIME_R::new(((self.bits >> 8) & 7) as u8)
216    }
217    #[doc = "Bit 16 - Rising Edge Interrupt Sense"]
218    #[inline(always)]
219    pub fn irise(&self) -> IRISE_R {
220        IRISE_R::new(((self.bits >> 16) & 1) != 0)
221    }
222    #[doc = "Bit 17 - Falling Edge Interrupt Sense"]
223    #[inline(always)]
224    pub fn ifall(&self) -> IFALL_R {
225        IFALL_R::new(((self.bits >> 17) & 1) != 0)
226    }
227    #[doc = "Bits 24:27 - VCMP Bias Programming Value"]
228    #[inline(always)]
229    pub fn biasprog(&self) -> BIASPROG_R {
230        BIASPROG_R::new(((self.bits >> 24) & 0x0f) as u8)
231    }
232    #[doc = "Bit 30 - Half Bias Current"]
233    #[inline(always)]
234    pub fn halfbias(&self) -> HALFBIAS_R {
235        HALFBIAS_R::new(((self.bits >> 30) & 1) != 0)
236    }
237}
238impl W {
239    #[doc = "Bit 0 - Voltage Supply Comparator Enable"]
240    #[inline(always)]
241    #[must_use]
242    pub fn en(&mut self) -> EN_W<0> {
243        EN_W::new(self)
244    }
245    #[doc = "Bit 2 - Inactive Value"]
246    #[inline(always)]
247    #[must_use]
248    pub fn inactval(&mut self) -> INACTVAL_W<2> {
249        INACTVAL_W::new(self)
250    }
251    #[doc = "Bit 4 - Hysteresis Enable"]
252    #[inline(always)]
253    #[must_use]
254    pub fn hysten(&mut self) -> HYSTEN_W<4> {
255        HYSTEN_W::new(self)
256    }
257    #[doc = "Bits 8:10 - Warm-Up Time"]
258    #[inline(always)]
259    #[must_use]
260    pub fn warmtime(&mut self) -> WARMTIME_W<8> {
261        WARMTIME_W::new(self)
262    }
263    #[doc = "Bit 16 - Rising Edge Interrupt Sense"]
264    #[inline(always)]
265    #[must_use]
266    pub fn irise(&mut self) -> IRISE_W<16> {
267        IRISE_W::new(self)
268    }
269    #[doc = "Bit 17 - Falling Edge Interrupt Sense"]
270    #[inline(always)]
271    #[must_use]
272    pub fn ifall(&mut self) -> IFALL_W<17> {
273        IFALL_W::new(self)
274    }
275    #[doc = "Bits 24:27 - VCMP Bias Programming Value"]
276    #[inline(always)]
277    #[must_use]
278    pub fn biasprog(&mut self) -> BIASPROG_W<24> {
279        BIASPROG_W::new(self)
280    }
281    #[doc = "Bit 30 - Half Bias Current"]
282    #[inline(always)]
283    #[must_use]
284    pub fn halfbias(&mut self) -> HALFBIAS_W<30> {
285        HALFBIAS_W::new(self)
286    }
287    #[doc = "Writes raw bits to the register."]
288    #[inline(always)]
289    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
290        self.0.bits(bits);
291        self
292    }
293}
294#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
295pub struct CTRL_SPEC;
296impl crate::RegisterSpec for CTRL_SPEC {
297    type Ux = u32;
298}
299#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
300impl crate::Readable for CTRL_SPEC {
301    type Reader = R;
302}
303#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
304impl crate::Writable for CTRL_SPEC {
305    type Writer = W;
306    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
307    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
308}
309#[doc = "`reset()` method sets CTRL to value 0x4700_0000"]
310impl crate::Resettable for CTRL_SPEC {
311    const RESET_VALUE: Self::Ux = 0x4700_0000;
312}
efm32gg_pac/efm32gg230/vcmp/ctrl.rs

efm32gg_pac/efm32gg230/vcmp/
ctrl.rs
