efm32gg_pac/efm32gg230/prs/
ch7_ctrl.rs

1#[doc = "Register `CH7_CTRL` reader"]
2pub struct R(crate::R<CH7_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH7_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH7_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH7_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH7_CTRL` writer"]
17pub struct W(crate::W<CH7_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH7_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH7_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH7_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CH7_CTRL_SPEC, u8, u8, 3, O>;
41#[doc = "Field `SOURCESEL` reader - Source Select"]
42pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
43#[doc = "Source Select\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45#[repr(u8)]
46pub enum SOURCESEL_A {
47    #[doc = "0: No source selected"]
48    NONE = 0,
49    #[doc = "1: Voltage Comparator"]
50    VCMP = 1,
51    #[doc = "2: Analog Comparator 0"]
52    ACMP0 = 2,
53    #[doc = "3: Analog Comparator 1"]
54    ACMP1 = 3,
55    #[doc = "6: Digital to Analog Converter 0"]
56    DAC0 = 6,
57    #[doc = "8: Analog to Digital Converter 0"]
58    ADC0 = 8,
59    #[doc = "16: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
60    USART0 = 16,
61    #[doc = "17: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
62    USART1 = 17,
63    #[doc = "18: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
64    USART2 = 18,
65    #[doc = "28: Timer 0"]
66    TIMER0 = 28,
67    #[doc = "29: Timer 1"]
68    TIMER1 = 29,
69    #[doc = "30: Timer 2"]
70    TIMER2 = 30,
71    #[doc = "31: Timer 3"]
72    TIMER3 = 31,
73    #[doc = "40: Real-Time Counter"]
74    RTC = 40,
75    #[doc = "48: General purpose Input/Output"]
76    GPIOL = 48,
77    #[doc = "49: General purpose Input/Output"]
78    GPIOH = 49,
79    #[doc = "52: Low Energy Timer 0"]
80    LETIMER0 = 52,
81    #[doc = "55: Backup RTC"]
82    BURTC = 55,
83    #[doc = "57: Low Energy Sensor Interface"]
84    LESENSEL = 57,
85    #[doc = "58: Low Energy Sensor Interface"]
86    LESENSEH = 58,
87    #[doc = "59: Low Energy Sensor Interface"]
88    LESENSED = 59,
89}
90impl From<SOURCESEL_A> for u8 {
91    #[inline(always)]
92    fn from(variant: SOURCESEL_A) -> Self {
93        variant as _
94    }
95}
96impl SOURCESEL_R {
97    #[doc = "Get enumerated values variant"]
98    #[inline(always)]
99    pub fn variant(&self) -> Option<SOURCESEL_A> {
100        match self.bits {
101            0 => Some(SOURCESEL_A::NONE),
102            1 => Some(SOURCESEL_A::VCMP),
103            2 => Some(SOURCESEL_A::ACMP0),
104            3 => Some(SOURCESEL_A::ACMP1),
105            6 => Some(SOURCESEL_A::DAC0),
106            8 => Some(SOURCESEL_A::ADC0),
107            16 => Some(SOURCESEL_A::USART0),
108            17 => Some(SOURCESEL_A::USART1),
109            18 => Some(SOURCESEL_A::USART2),
110            28 => Some(SOURCESEL_A::TIMER0),
111            29 => Some(SOURCESEL_A::TIMER1),
112            30 => Some(SOURCESEL_A::TIMER2),
113            31 => Some(SOURCESEL_A::TIMER3),
114            40 => Some(SOURCESEL_A::RTC),
115            48 => Some(SOURCESEL_A::GPIOL),
116            49 => Some(SOURCESEL_A::GPIOH),
117            52 => Some(SOURCESEL_A::LETIMER0),
118            55 => Some(SOURCESEL_A::BURTC),
119            57 => Some(SOURCESEL_A::LESENSEL),
120            58 => Some(SOURCESEL_A::LESENSEH),
121            59 => Some(SOURCESEL_A::LESENSED),
122            _ => None,
123        }
124    }
125    #[doc = "Checks if the value of the field is `NONE`"]
126    #[inline(always)]
127    pub fn is_none(&self) -> bool {
128        *self == SOURCESEL_A::NONE
129    }
130    #[doc = "Checks if the value of the field is `VCMP`"]
131    #[inline(always)]
132    pub fn is_vcmp(&self) -> bool {
133        *self == SOURCESEL_A::VCMP
134    }
135    #[doc = "Checks if the value of the field is `ACMP0`"]
136    #[inline(always)]
137    pub fn is_acmp0(&self) -> bool {
138        *self == SOURCESEL_A::ACMP0
139    }
140    #[doc = "Checks if the value of the field is `ACMP1`"]
141    #[inline(always)]
142    pub fn is_acmp1(&self) -> bool {
143        *self == SOURCESEL_A::ACMP1
144    }
145    #[doc = "Checks if the value of the field is `DAC0`"]
146    #[inline(always)]
147    pub fn is_dac0(&self) -> bool {
148        *self == SOURCESEL_A::DAC0
149    }
150    #[doc = "Checks if the value of the field is `ADC0`"]
151    #[inline(always)]
152    pub fn is_adc0(&self) -> bool {
153        *self == SOURCESEL_A::ADC0
154    }
155    #[doc = "Checks if the value of the field is `USART0`"]
156    #[inline(always)]
157    pub fn is_usart0(&self) -> bool {
158        *self == SOURCESEL_A::USART0
159    }
160    #[doc = "Checks if the value of the field is `USART1`"]
161    #[inline(always)]
162    pub fn is_usart1(&self) -> bool {
163        *self == SOURCESEL_A::USART1
164    }
165    #[doc = "Checks if the value of the field is `USART2`"]
166    #[inline(always)]
167    pub fn is_usart2(&self) -> bool {
168        *self == SOURCESEL_A::USART2
169    }
170    #[doc = "Checks if the value of the field is `TIMER0`"]
171    #[inline(always)]
172    pub fn is_timer0(&self) -> bool {
173        *self == SOURCESEL_A::TIMER0
174    }
175    #[doc = "Checks if the value of the field is `TIMER1`"]
176    #[inline(always)]
177    pub fn is_timer1(&self) -> bool {
178        *self == SOURCESEL_A::TIMER1
179    }
180    #[doc = "Checks if the value of the field is `TIMER2`"]
181    #[inline(always)]
182    pub fn is_timer2(&self) -> bool {
183        *self == SOURCESEL_A::TIMER2
184    }
185    #[doc = "Checks if the value of the field is `TIMER3`"]
186    #[inline(always)]
187    pub fn is_timer3(&self) -> bool {
188        *self == SOURCESEL_A::TIMER3
189    }
190    #[doc = "Checks if the value of the field is `RTC`"]
191    #[inline(always)]
192    pub fn is_rtc(&self) -> bool {
193        *self == SOURCESEL_A::RTC
194    }
195    #[doc = "Checks if the value of the field is `GPIOL`"]
196    #[inline(always)]
197    pub fn is_gpiol(&self) -> bool {
198        *self == SOURCESEL_A::GPIOL
199    }
200    #[doc = "Checks if the value of the field is `GPIOH`"]
201    #[inline(always)]
202    pub fn is_gpioh(&self) -> bool {
203        *self == SOURCESEL_A::GPIOH
204    }
205    #[doc = "Checks if the value of the field is `LETIMER0`"]
206    #[inline(always)]
207    pub fn is_letimer0(&self) -> bool {
208        *self == SOURCESEL_A::LETIMER0
209    }
210    #[doc = "Checks if the value of the field is `BURTC`"]
211    #[inline(always)]
212    pub fn is_burtc(&self) -> bool {
213        *self == SOURCESEL_A::BURTC
214    }
215    #[doc = "Checks if the value of the field is `LESENSEL`"]
216    #[inline(always)]
217    pub fn is_lesensel(&self) -> bool {
218        *self == SOURCESEL_A::LESENSEL
219    }
220    #[doc = "Checks if the value of the field is `LESENSEH`"]
221    #[inline(always)]
222    pub fn is_lesenseh(&self) -> bool {
223        *self == SOURCESEL_A::LESENSEH
224    }
225    #[doc = "Checks if the value of the field is `LESENSED`"]
226    #[inline(always)]
227    pub fn is_lesensed(&self) -> bool {
228        *self == SOURCESEL_A::LESENSED
229    }
230}
231#[doc = "Field `SOURCESEL` writer - Source Select"]
232pub type SOURCESEL_W<'a, const O: u8> =
233    crate::FieldWriter<'a, u32, CH7_CTRL_SPEC, u8, SOURCESEL_A, 6, O>;
234impl<'a, const O: u8> SOURCESEL_W<'a, O> {
235    #[doc = "No source selected"]
236    #[inline(always)]
237    pub fn none(self) -> &'a mut W {
238        self.variant(SOURCESEL_A::NONE)
239    }
240    #[doc = "Voltage Comparator"]
241    #[inline(always)]
242    pub fn vcmp(self) -> &'a mut W {
243        self.variant(SOURCESEL_A::VCMP)
244    }
245    #[doc = "Analog Comparator 0"]
246    #[inline(always)]
247    pub fn acmp0(self) -> &'a mut W {
248        self.variant(SOURCESEL_A::ACMP0)
249    }
250    #[doc = "Analog Comparator 1"]
251    #[inline(always)]
252    pub fn acmp1(self) -> &'a mut W {
253        self.variant(SOURCESEL_A::ACMP1)
254    }
255    #[doc = "Digital to Analog Converter 0"]
256    #[inline(always)]
257    pub fn dac0(self) -> &'a mut W {
258        self.variant(SOURCESEL_A::DAC0)
259    }
260    #[doc = "Analog to Digital Converter 0"]
261    #[inline(always)]
262    pub fn adc0(self) -> &'a mut W {
263        self.variant(SOURCESEL_A::ADC0)
264    }
265    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
266    #[inline(always)]
267    pub fn usart0(self) -> &'a mut W {
268        self.variant(SOURCESEL_A::USART0)
269    }
270    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
271    #[inline(always)]
272    pub fn usart1(self) -> &'a mut W {
273        self.variant(SOURCESEL_A::USART1)
274    }
275    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
276    #[inline(always)]
277    pub fn usart2(self) -> &'a mut W {
278        self.variant(SOURCESEL_A::USART2)
279    }
280    #[doc = "Timer 0"]
281    #[inline(always)]
282    pub fn timer0(self) -> &'a mut W {
283        self.variant(SOURCESEL_A::TIMER0)
284    }
285    #[doc = "Timer 1"]
286    #[inline(always)]
287    pub fn timer1(self) -> &'a mut W {
288        self.variant(SOURCESEL_A::TIMER1)
289    }
290    #[doc = "Timer 2"]
291    #[inline(always)]
292    pub fn timer2(self) -> &'a mut W {
293        self.variant(SOURCESEL_A::TIMER2)
294    }
295    #[doc = "Timer 3"]
296    #[inline(always)]
297    pub fn timer3(self) -> &'a mut W {
298        self.variant(SOURCESEL_A::TIMER3)
299    }
300    #[doc = "Real-Time Counter"]
301    #[inline(always)]
302    pub fn rtc(self) -> &'a mut W {
303        self.variant(SOURCESEL_A::RTC)
304    }
305    #[doc = "General purpose Input/Output"]
306    #[inline(always)]
307    pub fn gpiol(self) -> &'a mut W {
308        self.variant(SOURCESEL_A::GPIOL)
309    }
310    #[doc = "General purpose Input/Output"]
311    #[inline(always)]
312    pub fn gpioh(self) -> &'a mut W {
313        self.variant(SOURCESEL_A::GPIOH)
314    }
315    #[doc = "Low Energy Timer 0"]
316    #[inline(always)]
317    pub fn letimer0(self) -> &'a mut W {
318        self.variant(SOURCESEL_A::LETIMER0)
319    }
320    #[doc = "Backup RTC"]
321    #[inline(always)]
322    pub fn burtc(self) -> &'a mut W {
323        self.variant(SOURCESEL_A::BURTC)
324    }
325    #[doc = "Low Energy Sensor Interface"]
326    #[inline(always)]
327    pub fn lesensel(self) -> &'a mut W {
328        self.variant(SOURCESEL_A::LESENSEL)
329    }
330    #[doc = "Low Energy Sensor Interface"]
331    #[inline(always)]
332    pub fn lesenseh(self) -> &'a mut W {
333        self.variant(SOURCESEL_A::LESENSEH)
334    }
335    #[doc = "Low Energy Sensor Interface"]
336    #[inline(always)]
337    pub fn lesensed(self) -> &'a mut W {
338        self.variant(SOURCESEL_A::LESENSED)
339    }
340}
341#[doc = "Field `EDSEL` reader - Edge Detect Select"]
342pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
343#[doc = "Edge Detect Select\n\nValue on reset: 0"]
344#[derive(Clone, Copy, Debug, PartialEq, Eq)]
345#[repr(u8)]
346pub enum EDSEL_A {
347    #[doc = "0: Signal is left as it is"]
348    OFF = 0,
349    #[doc = "1: A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
350    POSEDGE = 1,
351    #[doc = "2: A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
352    NEGEDGE = 2,
353    #[doc = "3: A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
354    BOTHEDGES = 3,
355}
356impl From<EDSEL_A> for u8 {
357    #[inline(always)]
358    fn from(variant: EDSEL_A) -> Self {
359        variant as _
360    }
361}
362impl EDSEL_R {
363    #[doc = "Get enumerated values variant"]
364    #[inline(always)]
365    pub fn variant(&self) -> EDSEL_A {
366        match self.bits {
367            0 => EDSEL_A::OFF,
368            1 => EDSEL_A::POSEDGE,
369            2 => EDSEL_A::NEGEDGE,
370            3 => EDSEL_A::BOTHEDGES,
371            _ => unreachable!(),
372        }
373    }
374    #[doc = "Checks if the value of the field is `OFF`"]
375    #[inline(always)]
376    pub fn is_off(&self) -> bool {
377        *self == EDSEL_A::OFF
378    }
379    #[doc = "Checks if the value of the field is `POSEDGE`"]
380    #[inline(always)]
381    pub fn is_posedge(&self) -> bool {
382        *self == EDSEL_A::POSEDGE
383    }
384    #[doc = "Checks if the value of the field is `NEGEDGE`"]
385    #[inline(always)]
386    pub fn is_negedge(&self) -> bool {
387        *self == EDSEL_A::NEGEDGE
388    }
389    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
390    #[inline(always)]
391    pub fn is_bothedges(&self) -> bool {
392        *self == EDSEL_A::BOTHEDGES
393    }
394}
395#[doc = "Field `EDSEL` writer - Edge Detect Select"]
396pub type EDSEL_W<'a, const O: u8> =
397    crate::FieldWriterSafe<'a, u32, CH7_CTRL_SPEC, u8, EDSEL_A, 2, O>;
398impl<'a, const O: u8> EDSEL_W<'a, O> {
399    #[doc = "Signal is left as it is"]
400    #[inline(always)]
401    pub fn off(self) -> &'a mut W {
402        self.variant(EDSEL_A::OFF)
403    }
404    #[doc = "A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
405    #[inline(always)]
406    pub fn posedge(self) -> &'a mut W {
407        self.variant(EDSEL_A::POSEDGE)
408    }
409    #[doc = "A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
410    #[inline(always)]
411    pub fn negedge(self) -> &'a mut W {
412        self.variant(EDSEL_A::NEGEDGE)
413    }
414    #[doc = "A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
415    #[inline(always)]
416    pub fn bothedges(self) -> &'a mut W {
417        self.variant(EDSEL_A::BOTHEDGES)
418    }
419}
420#[doc = "Field `ASYNC` reader - Asynchronous reflex"]
421pub type ASYNC_R = crate::BitReader<bool>;
422#[doc = "Field `ASYNC` writer - Asynchronous reflex"]
423pub type ASYNC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CH7_CTRL_SPEC, bool, O>;
424impl R {
425    #[doc = "Bits 0:2 - Signal Select"]
426    #[inline(always)]
427    pub fn sigsel(&self) -> SIGSEL_R {
428        SIGSEL_R::new((self.bits & 7) as u8)
429    }
430    #[doc = "Bits 16:21 - Source Select"]
431    #[inline(always)]
432    pub fn sourcesel(&self) -> SOURCESEL_R {
433        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
434    }
435    #[doc = "Bits 24:25 - Edge Detect Select"]
436    #[inline(always)]
437    pub fn edsel(&self) -> EDSEL_R {
438        EDSEL_R::new(((self.bits >> 24) & 3) as u8)
439    }
440    #[doc = "Bit 28 - Asynchronous reflex"]
441    #[inline(always)]
442    pub fn async_(&self) -> ASYNC_R {
443        ASYNC_R::new(((self.bits >> 28) & 1) != 0)
444    }
445}
446impl W {
447    #[doc = "Bits 0:2 - Signal Select"]
448    #[inline(always)]
449    #[must_use]
450    pub fn sigsel(&mut self) -> SIGSEL_W<0> {
451        SIGSEL_W::new(self)
452    }
453    #[doc = "Bits 16:21 - Source Select"]
454    #[inline(always)]
455    #[must_use]
456    pub fn sourcesel(&mut self) -> SOURCESEL_W<16> {
457        SOURCESEL_W::new(self)
458    }
459    #[doc = "Bits 24:25 - Edge Detect Select"]
460    #[inline(always)]
461    #[must_use]
462    pub fn edsel(&mut self) -> EDSEL_W<24> {
463        EDSEL_W::new(self)
464    }
465    #[doc = "Bit 28 - Asynchronous reflex"]
466    #[inline(always)]
467    #[must_use]
468    pub fn async_(&mut self) -> ASYNC_W<28> {
469        ASYNC_W::new(self)
470    }
471    #[doc = "Writes raw bits to the register."]
472    #[inline(always)]
473    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
474        self.0.bits(bits);
475        self
476    }
477}
478#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch7_ctrl](index.html) module"]
479pub struct CH7_CTRL_SPEC;
480impl crate::RegisterSpec for CH7_CTRL_SPEC {
481    type Ux = u32;
482}
483#[doc = "`read()` method returns [ch7_ctrl::R](R) reader structure"]
484impl crate::Readable for CH7_CTRL_SPEC {
485    type Reader = R;
486}
487#[doc = "`write(|w| ..)` method takes [ch7_ctrl::W](W) writer structure"]
488impl crate::Writable for CH7_CTRL_SPEC {
489    type Writer = W;
490    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
491    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
492}
493#[doc = "`reset()` method sets CH7_CTRL to value 0"]
494impl crate::Resettable for CH7_CTRL_SPEC {
495    const RESET_VALUE: Self::Ux = 0;
496}
efm32gg_pac/efm32gg230/prs/ch7_ctrl.rs

efm32gg_pac/efm32gg230/prs/
ch7_ctrl.rs
