efm32gg_pac/efm32gg230/msc/
readctrl.rs

1#[doc = "Register `READCTRL` reader"]
2pub struct R(crate::R<READCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<READCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<READCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<READCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `READCTRL` writer"]
17pub struct W(crate::W<READCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<READCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<READCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<READCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MODE` reader - Read Mode"]
38pub type MODE_R = crate::FieldReader<u8, MODE_A>;
39#[doc = "Read Mode\n\nValue on reset: 1"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum MODE_A {
43    #[doc = "0: Zero wait-states inserted in fetch or read transfers."]
44    WS0 = 0,
45    #[doc = "1: One wait-state inserted for each fetch or read transfer. This mode is required for a core frequency above 16 MHz."]
46    WS1 = 1,
47    #[doc = "2: Zero wait-states inserted with the Suppressed Conditional Branch Target Prefetch (SCBTP) function enabled. SCBTP saves energy by delaying the Cortex' conditional branch target prefetches until the conditional branch instruction is in the execute stage. When the instruction reaches this stage, the evaluation of the branch condition is completed and the core does not perform a speculative prefetch of both the branch target address and the next sequential address. With the SCBTP function enabled, one instruction fetch is saved for each branch not taken, with a negligible performance penalty."]
48    WS0SCBTP = 2,
49    #[doc = "3: One wait-state access with SCBTP enabled."]
50    WS1SCBTP = 3,
51    #[doc = "4: Two wait-states inserted for each fetch or read transfer. This mode is required for a core frequency above 32 MHz."]
52    WS2 = 4,
53    #[doc = "5: Two wait-state access with SCBTP enabled."]
54    WS2SCBTP = 5,
55}
56impl From<MODE_A> for u8 {
57    #[inline(always)]
58    fn from(variant: MODE_A) -> Self {
59        variant as _
60    }
61}
62impl MODE_R {
63    #[doc = "Get enumerated values variant"]
64    #[inline(always)]
65    pub fn variant(&self) -> Option<MODE_A> {
66        match self.bits {
67            0 => Some(MODE_A::WS0),
68            1 => Some(MODE_A::WS1),
69            2 => Some(MODE_A::WS0SCBTP),
70            3 => Some(MODE_A::WS1SCBTP),
71            4 => Some(MODE_A::WS2),
72            5 => Some(MODE_A::WS2SCBTP),
73            _ => None,
74        }
75    }
76    #[doc = "Checks if the value of the field is `WS0`"]
77    #[inline(always)]
78    pub fn is_ws0(&self) -> bool {
79        *self == MODE_A::WS0
80    }
81    #[doc = "Checks if the value of the field is `WS1`"]
82    #[inline(always)]
83    pub fn is_ws1(&self) -> bool {
84        *self == MODE_A::WS1
85    }
86    #[doc = "Checks if the value of the field is `WS0SCBTP`"]
87    #[inline(always)]
88    pub fn is_ws0scbtp(&self) -> bool {
89        *self == MODE_A::WS0SCBTP
90    }
91    #[doc = "Checks if the value of the field is `WS1SCBTP`"]
92    #[inline(always)]
93    pub fn is_ws1scbtp(&self) -> bool {
94        *self == MODE_A::WS1SCBTP
95    }
96    #[doc = "Checks if the value of the field is `WS2`"]
97    #[inline(always)]
98    pub fn is_ws2(&self) -> bool {
99        *self == MODE_A::WS2
100    }
101    #[doc = "Checks if the value of the field is `WS2SCBTP`"]
102    #[inline(always)]
103    pub fn is_ws2scbtp(&self) -> bool {
104        *self == MODE_A::WS2SCBTP
105    }
106}
107#[doc = "Field `MODE` writer - Read Mode"]
108pub type MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, READCTRL_SPEC, u8, MODE_A, 3, O>;
109impl<'a, const O: u8> MODE_W<'a, O> {
110    #[doc = "Zero wait-states inserted in fetch or read transfers."]
111    #[inline(always)]
112    pub fn ws0(self) -> &'a mut W {
113        self.variant(MODE_A::WS0)
114    }
115    #[doc = "One wait-state inserted for each fetch or read transfer. This mode is required for a core frequency above 16 MHz."]
116    #[inline(always)]
117    pub fn ws1(self) -> &'a mut W {
118        self.variant(MODE_A::WS1)
119    }
120    #[doc = "Zero wait-states inserted with the Suppressed Conditional Branch Target Prefetch (SCBTP) function enabled. SCBTP saves energy by delaying the Cortex' conditional branch target prefetches until the conditional branch instruction is in the execute stage. When the instruction reaches this stage, the evaluation of the branch condition is completed and the core does not perform a speculative prefetch of both the branch target address and the next sequential address. With the SCBTP function enabled, one instruction fetch is saved for each branch not taken, with a negligible performance penalty."]
121    #[inline(always)]
122    pub fn ws0scbtp(self) -> &'a mut W {
123        self.variant(MODE_A::WS0SCBTP)
124    }
125    #[doc = "One wait-state access with SCBTP enabled."]
126    #[inline(always)]
127    pub fn ws1scbtp(self) -> &'a mut W {
128        self.variant(MODE_A::WS1SCBTP)
129    }
130    #[doc = "Two wait-states inserted for each fetch or read transfer. This mode is required for a core frequency above 32 MHz."]
131    #[inline(always)]
132    pub fn ws2(self) -> &'a mut W {
133        self.variant(MODE_A::WS2)
134    }
135    #[doc = "Two wait-state access with SCBTP enabled."]
136    #[inline(always)]
137    pub fn ws2scbtp(self) -> &'a mut W {
138        self.variant(MODE_A::WS2SCBTP)
139    }
140}
141#[doc = "Field `IFCDIS` reader - Internal Flash Cache Disable"]
142pub type IFCDIS_R = crate::BitReader<bool>;
143#[doc = "Field `IFCDIS` writer - Internal Flash Cache Disable"]
144pub type IFCDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, O>;
145#[doc = "Field `AIDIS` reader - Automatic Invalidate Disable"]
146pub type AIDIS_R = crate::BitReader<bool>;
147#[doc = "Field `AIDIS` writer - Automatic Invalidate Disable"]
148pub type AIDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, O>;
149#[doc = "Field `ICCDIS` reader - Interrupt Context Cache Disable"]
150pub type ICCDIS_R = crate::BitReader<bool>;
151#[doc = "Field `ICCDIS` writer - Interrupt Context Cache Disable"]
152pub type ICCDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, O>;
153#[doc = "Field `EBICDIS` reader - External Bus Interface Cache Disable"]
154pub type EBICDIS_R = crate::BitReader<bool>;
155#[doc = "Field `EBICDIS` writer - External Bus Interface Cache Disable"]
156pub type EBICDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, O>;
157#[doc = "Field `RAMCEN` reader - RAM Cache Enable"]
158pub type RAMCEN_R = crate::BitReader<bool>;
159#[doc = "Field `RAMCEN` writer - RAM Cache Enable"]
160pub type RAMCEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, O>;
161#[doc = "Field `PREFETCH` reader - Prefetch Mode"]
162pub type PREFETCH_R = crate::BitReader<bool>;
163#[doc = "Field `PREFETCH` writer - Prefetch Mode"]
164pub type PREFETCH_W<'a, const O: u8> = crate::BitWriter<'a, u32, READCTRL_SPEC, bool, O>;
165#[doc = "Field `BUSSTRATEGY` reader - Strategy for bus matrix"]
166pub type BUSSTRATEGY_R = crate::FieldReader<u8, BUSSTRATEGY_A>;
167#[doc = "Strategy for bus matrix\n\nValue on reset: 0"]
168#[derive(Clone, Copy, Debug, PartialEq, Eq)]
169#[repr(u8)]
170pub enum BUSSTRATEGY_A {
171    #[doc = "0: `0`"]
172    CPU = 0,
173    #[doc = "1: `1`"]
174    DMA = 1,
175    #[doc = "2: `10`"]
176    DMAEM1 = 2,
177    #[doc = "3: `11`"]
178    NONE = 3,
179}
180impl From<BUSSTRATEGY_A> for u8 {
181    #[inline(always)]
182    fn from(variant: BUSSTRATEGY_A) -> Self {
183        variant as _
184    }
185}
186impl BUSSTRATEGY_R {
187    #[doc = "Get enumerated values variant"]
188    #[inline(always)]
189    pub fn variant(&self) -> BUSSTRATEGY_A {
190        match self.bits {
191            0 => BUSSTRATEGY_A::CPU,
192            1 => BUSSTRATEGY_A::DMA,
193            2 => BUSSTRATEGY_A::DMAEM1,
194            3 => BUSSTRATEGY_A::NONE,
195            _ => unreachable!(),
196        }
197    }
198    #[doc = "Checks if the value of the field is `CPU`"]
199    #[inline(always)]
200    pub fn is_cpu(&self) -> bool {
201        *self == BUSSTRATEGY_A::CPU
202    }
203    #[doc = "Checks if the value of the field is `DMA`"]
204    #[inline(always)]
205    pub fn is_dma(&self) -> bool {
206        *self == BUSSTRATEGY_A::DMA
207    }
208    #[doc = "Checks if the value of the field is `DMAEM1`"]
209    #[inline(always)]
210    pub fn is_dmaem1(&self) -> bool {
211        *self == BUSSTRATEGY_A::DMAEM1
212    }
213    #[doc = "Checks if the value of the field is `NONE`"]
214    #[inline(always)]
215    pub fn is_none(&self) -> bool {
216        *self == BUSSTRATEGY_A::NONE
217    }
218}
219#[doc = "Field `BUSSTRATEGY` writer - Strategy for bus matrix"]
220pub type BUSSTRATEGY_W<'a, const O: u8> =
221    crate::FieldWriterSafe<'a, u32, READCTRL_SPEC, u8, BUSSTRATEGY_A, 2, O>;
222impl<'a, const O: u8> BUSSTRATEGY_W<'a, O> {
223    #[doc = "`0`"]
224    #[inline(always)]
225    pub fn cpu(self) -> &'a mut W {
226        self.variant(BUSSTRATEGY_A::CPU)
227    }
228    #[doc = "`1`"]
229    #[inline(always)]
230    pub fn dma(self) -> &'a mut W {
231        self.variant(BUSSTRATEGY_A::DMA)
232    }
233    #[doc = "`10`"]
234    #[inline(always)]
235    pub fn dmaem1(self) -> &'a mut W {
236        self.variant(BUSSTRATEGY_A::DMAEM1)
237    }
238    #[doc = "`11`"]
239    #[inline(always)]
240    pub fn none(self) -> &'a mut W {
241        self.variant(BUSSTRATEGY_A::NONE)
242    }
243}
244impl R {
245    #[doc = "Bits 0:2 - Read Mode"]
246    #[inline(always)]
247    pub fn mode(&self) -> MODE_R {
248        MODE_R::new((self.bits & 7) as u8)
249    }
250    #[doc = "Bit 3 - Internal Flash Cache Disable"]
251    #[inline(always)]
252    pub fn ifcdis(&self) -> IFCDIS_R {
253        IFCDIS_R::new(((self.bits >> 3) & 1) != 0)
254    }
255    #[doc = "Bit 4 - Automatic Invalidate Disable"]
256    #[inline(always)]
257    pub fn aidis(&self) -> AIDIS_R {
258        AIDIS_R::new(((self.bits >> 4) & 1) != 0)
259    }
260    #[doc = "Bit 5 - Interrupt Context Cache Disable"]
261    #[inline(always)]
262    pub fn iccdis(&self) -> ICCDIS_R {
263        ICCDIS_R::new(((self.bits >> 5) & 1) != 0)
264    }
265    #[doc = "Bit 6 - External Bus Interface Cache Disable"]
266    #[inline(always)]
267    pub fn ebicdis(&self) -> EBICDIS_R {
268        EBICDIS_R::new(((self.bits >> 6) & 1) != 0)
269    }
270    #[doc = "Bit 7 - RAM Cache Enable"]
271    #[inline(always)]
272    pub fn ramcen(&self) -> RAMCEN_R {
273        RAMCEN_R::new(((self.bits >> 7) & 1) != 0)
274    }
275    #[doc = "Bit 8 - Prefetch Mode"]
276    #[inline(always)]
277    pub fn prefetch(&self) -> PREFETCH_R {
278        PREFETCH_R::new(((self.bits >> 8) & 1) != 0)
279    }
280    #[doc = "Bits 16:17 - Strategy for bus matrix"]
281    #[inline(always)]
282    pub fn busstrategy(&self) -> BUSSTRATEGY_R {
283        BUSSTRATEGY_R::new(((self.bits >> 16) & 3) as u8)
284    }
285}
286impl W {
287    #[doc = "Bits 0:2 - Read Mode"]
288    #[inline(always)]
289    #[must_use]
290    pub fn mode(&mut self) -> MODE_W<0> {
291        MODE_W::new(self)
292    }
293    #[doc = "Bit 3 - Internal Flash Cache Disable"]
294    #[inline(always)]
295    #[must_use]
296    pub fn ifcdis(&mut self) -> IFCDIS_W<3> {
297        IFCDIS_W::new(self)
298    }
299    #[doc = "Bit 4 - Automatic Invalidate Disable"]
300    #[inline(always)]
301    #[must_use]
302    pub fn aidis(&mut self) -> AIDIS_W<4> {
303        AIDIS_W::new(self)
304    }
305    #[doc = "Bit 5 - Interrupt Context Cache Disable"]
306    #[inline(always)]
307    #[must_use]
308    pub fn iccdis(&mut self) -> ICCDIS_W<5> {
309        ICCDIS_W::new(self)
310    }
311    #[doc = "Bit 6 - External Bus Interface Cache Disable"]
312    #[inline(always)]
313    #[must_use]
314    pub fn ebicdis(&mut self) -> EBICDIS_W<6> {
315        EBICDIS_W::new(self)
316    }
317    #[doc = "Bit 7 - RAM Cache Enable"]
318    #[inline(always)]
319    #[must_use]
320    pub fn ramcen(&mut self) -> RAMCEN_W<7> {
321        RAMCEN_W::new(self)
322    }
323    #[doc = "Bit 8 - Prefetch Mode"]
324    #[inline(always)]
325    #[must_use]
326    pub fn prefetch(&mut self) -> PREFETCH_W<8> {
327        PREFETCH_W::new(self)
328    }
329    #[doc = "Bits 16:17 - Strategy for bus matrix"]
330    #[inline(always)]
331    #[must_use]
332    pub fn busstrategy(&mut self) -> BUSSTRATEGY_W<16> {
333        BUSSTRATEGY_W::new(self)
334    }
335    #[doc = "Writes raw bits to the register."]
336    #[inline(always)]
337    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
338        self.0.bits(bits);
339        self
340    }
341}
342#[doc = "Read Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [readctrl](index.html) module"]
343pub struct READCTRL_SPEC;
344impl crate::RegisterSpec for READCTRL_SPEC {
345    type Ux = u32;
346}
347#[doc = "`read()` method returns [readctrl::R](R) reader structure"]
348impl crate::Readable for READCTRL_SPEC {
349    type Reader = R;
350}
351#[doc = "`write(|w| ..)` method takes [readctrl::W](W) writer structure"]
352impl crate::Writable for READCTRL_SPEC {
353    type Writer = W;
354    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
355    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
356}
357#[doc = "`reset()` method sets READCTRL to value 0x01"]
358impl crate::Resettable for READCTRL_SPEC {
359    const RESET_VALUE: Self::Ux = 0x01;
360}
efm32gg_pac/efm32gg230/msc/readctrl.rs

efm32gg_pac/efm32gg230/msc/
readctrl.rs
