efm32gg_pac/efm32gg230/leuart0/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `AUTOTRI` reader - Automatic Transmitter Tristate"]
38pub type AUTOTRI_R = crate::BitReader<bool>;
39#[doc = "Field `AUTOTRI` writer - Automatic Transmitter Tristate"]
40pub type AUTOTRI_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
41#[doc = "Field `DATABITS` reader - Data-Bit Mode"]
42pub type DATABITS_R = crate::BitReader<bool>;
43#[doc = "Field `DATABITS` writer - Data-Bit Mode"]
44pub type DATABITS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
45#[doc = "Field `PARITY` reader - Parity-Bit Mode"]
46pub type PARITY_R = crate::FieldReader<u8, PARITY_A>;
47#[doc = "Parity-Bit Mode\n\nValue on reset: 0"]
48#[derive(Clone, Copy, Debug, PartialEq, Eq)]
49#[repr(u8)]
50pub enum PARITY_A {
51    #[doc = "0: Parity bits are not used"]
52    NONE = 0,
53    #[doc = "2: Even parity are used. Parity bits are automatically generated and checked by hardware."]
54    EVEN = 2,
55    #[doc = "3: Odd parity is used. Parity bits are automatically generated and checked by hardware."]
56    ODD = 3,
57}
58impl From<PARITY_A> for u8 {
59    #[inline(always)]
60    fn from(variant: PARITY_A) -> Self {
61        variant as _
62    }
63}
64impl PARITY_R {
65    #[doc = "Get enumerated values variant"]
66    #[inline(always)]
67    pub fn variant(&self) -> Option<PARITY_A> {
68        match self.bits {
69            0 => Some(PARITY_A::NONE),
70            2 => Some(PARITY_A::EVEN),
71            3 => Some(PARITY_A::ODD),
72            _ => None,
73        }
74    }
75    #[doc = "Checks if the value of the field is `NONE`"]
76    #[inline(always)]
77    pub fn is_none(&self) -> bool {
78        *self == PARITY_A::NONE
79    }
80    #[doc = "Checks if the value of the field is `EVEN`"]
81    #[inline(always)]
82    pub fn is_even(&self) -> bool {
83        *self == PARITY_A::EVEN
84    }
85    #[doc = "Checks if the value of the field is `ODD`"]
86    #[inline(always)]
87    pub fn is_odd(&self) -> bool {
88        *self == PARITY_A::ODD
89    }
90}
91#[doc = "Field `PARITY` writer - Parity-Bit Mode"]
92pub type PARITY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL_SPEC, u8, PARITY_A, 2, O>;
93impl<'a, const O: u8> PARITY_W<'a, O> {
94    #[doc = "Parity bits are not used"]
95    #[inline(always)]
96    pub fn none(self) -> &'a mut W {
97        self.variant(PARITY_A::NONE)
98    }
99    #[doc = "Even parity are used. Parity bits are automatically generated and checked by hardware."]
100    #[inline(always)]
101    pub fn even(self) -> &'a mut W {
102        self.variant(PARITY_A::EVEN)
103    }
104    #[doc = "Odd parity is used. Parity bits are automatically generated and checked by hardware."]
105    #[inline(always)]
106    pub fn odd(self) -> &'a mut W {
107        self.variant(PARITY_A::ODD)
108    }
109}
110#[doc = "Field `STOPBITS` reader - Stop-Bit Mode"]
111pub type STOPBITS_R = crate::BitReader<bool>;
112#[doc = "Field `STOPBITS` writer - Stop-Bit Mode"]
113pub type STOPBITS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
114#[doc = "Field `INV` reader - Invert Input And Output"]
115pub type INV_R = crate::BitReader<bool>;
116#[doc = "Field `INV` writer - Invert Input And Output"]
117pub type INV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
118#[doc = "Field `ERRSDMA` reader - Clear RX DMA On Error"]
119pub type ERRSDMA_R = crate::BitReader<bool>;
120#[doc = "Field `ERRSDMA` writer - Clear RX DMA On Error"]
121pub type ERRSDMA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
122#[doc = "Field `LOOPBK` reader - Loopback Enable"]
123pub type LOOPBK_R = crate::BitReader<bool>;
124#[doc = "Field `LOOPBK` writer - Loopback Enable"]
125pub type LOOPBK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
126#[doc = "Field `SFUBRX` reader - Start-Frame UnBlock RX"]
127pub type SFUBRX_R = crate::BitReader<bool>;
128#[doc = "Field `SFUBRX` writer - Start-Frame UnBlock RX"]
129pub type SFUBRX_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
130#[doc = "Field `MPM` reader - Multi-Processor Mode"]
131pub type MPM_R = crate::BitReader<bool>;
132#[doc = "Field `MPM` writer - Multi-Processor Mode"]
133pub type MPM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
134#[doc = "Field `MPAB` reader - Multi-Processor Address-Bit"]
135pub type MPAB_R = crate::BitReader<bool>;
136#[doc = "Field `MPAB` writer - Multi-Processor Address-Bit"]
137pub type MPAB_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
138#[doc = "Field `BIT8DV` reader - Bit 8 Default Value"]
139pub type BIT8DV_R = crate::BitReader<bool>;
140#[doc = "Field `BIT8DV` writer - Bit 8 Default Value"]
141pub type BIT8DV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
142#[doc = "Field `RXDMAWU` reader - RX DMA Wakeup"]
143pub type RXDMAWU_R = crate::BitReader<bool>;
144#[doc = "Field `RXDMAWU` writer - RX DMA Wakeup"]
145pub type RXDMAWU_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
146#[doc = "Field `TXDMAWU` reader - TX DMA Wakeup"]
147pub type TXDMAWU_R = crate::BitReader<bool>;
148#[doc = "Field `TXDMAWU` writer - TX DMA Wakeup"]
149pub type TXDMAWU_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
150#[doc = "Field `TXDELAY` reader - TX Delay Transmission"]
151pub type TXDELAY_R = crate::FieldReader<u8, TXDELAY_A>;
152#[doc = "TX Delay Transmission\n\nValue on reset: 0"]
153#[derive(Clone, Copy, Debug, PartialEq, Eq)]
154#[repr(u8)]
155pub enum TXDELAY_A {
156    #[doc = "0: Frames are transmitted immediately"]
157    NONE = 0,
158    #[doc = "1: Transmission of new frames are delayed by a single baud period"]
159    SINGLE = 1,
160    #[doc = "2: Transmission of new frames are delayed by two baud periods"]
161    DOUBLE = 2,
162    #[doc = "3: Transmission of new frames are delayed by three baud periods"]
163    TRIPLE = 3,
164}
165impl From<TXDELAY_A> for u8 {
166    #[inline(always)]
167    fn from(variant: TXDELAY_A) -> Self {
168        variant as _
169    }
170}
171impl TXDELAY_R {
172    #[doc = "Get enumerated values variant"]
173    #[inline(always)]
174    pub fn variant(&self) -> TXDELAY_A {
175        match self.bits {
176            0 => TXDELAY_A::NONE,
177            1 => TXDELAY_A::SINGLE,
178            2 => TXDELAY_A::DOUBLE,
179            3 => TXDELAY_A::TRIPLE,
180            _ => unreachable!(),
181        }
182    }
183    #[doc = "Checks if the value of the field is `NONE`"]
184    #[inline(always)]
185    pub fn is_none(&self) -> bool {
186        *self == TXDELAY_A::NONE
187    }
188    #[doc = "Checks if the value of the field is `SINGLE`"]
189    #[inline(always)]
190    pub fn is_single(&self) -> bool {
191        *self == TXDELAY_A::SINGLE
192    }
193    #[doc = "Checks if the value of the field is `DOUBLE`"]
194    #[inline(always)]
195    pub fn is_double(&self) -> bool {
196        *self == TXDELAY_A::DOUBLE
197    }
198    #[doc = "Checks if the value of the field is `TRIPLE`"]
199    #[inline(always)]
200    pub fn is_triple(&self) -> bool {
201        *self == TXDELAY_A::TRIPLE
202    }
203}
204#[doc = "Field `TXDELAY` writer - TX Delay Transmission"]
205pub type TXDELAY_W<'a, const O: u8> =
206    crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, TXDELAY_A, 2, O>;
207impl<'a, const O: u8> TXDELAY_W<'a, O> {
208    #[doc = "Frames are transmitted immediately"]
209    #[inline(always)]
210    pub fn none(self) -> &'a mut W {
211        self.variant(TXDELAY_A::NONE)
212    }
213    #[doc = "Transmission of new frames are delayed by a single baud period"]
214    #[inline(always)]
215    pub fn single(self) -> &'a mut W {
216        self.variant(TXDELAY_A::SINGLE)
217    }
218    #[doc = "Transmission of new frames are delayed by two baud periods"]
219    #[inline(always)]
220    pub fn double(self) -> &'a mut W {
221        self.variant(TXDELAY_A::DOUBLE)
222    }
223    #[doc = "Transmission of new frames are delayed by three baud periods"]
224    #[inline(always)]
225    pub fn triple(self) -> &'a mut W {
226        self.variant(TXDELAY_A::TRIPLE)
227    }
228}
229impl R {
230    #[doc = "Bit 0 - Automatic Transmitter Tristate"]
231    #[inline(always)]
232    pub fn autotri(&self) -> AUTOTRI_R {
233        AUTOTRI_R::new((self.bits & 1) != 0)
234    }
235    #[doc = "Bit 1 - Data-Bit Mode"]
236    #[inline(always)]
237    pub fn databits(&self) -> DATABITS_R {
238        DATABITS_R::new(((self.bits >> 1) & 1) != 0)
239    }
240    #[doc = "Bits 2:3 - Parity-Bit Mode"]
241    #[inline(always)]
242    pub fn parity(&self) -> PARITY_R {
243        PARITY_R::new(((self.bits >> 2) & 3) as u8)
244    }
245    #[doc = "Bit 4 - Stop-Bit Mode"]
246    #[inline(always)]
247    pub fn stopbits(&self) -> STOPBITS_R {
248        STOPBITS_R::new(((self.bits >> 4) & 1) != 0)
249    }
250    #[doc = "Bit 5 - Invert Input And Output"]
251    #[inline(always)]
252    pub fn inv(&self) -> INV_R {
253        INV_R::new(((self.bits >> 5) & 1) != 0)
254    }
255    #[doc = "Bit 6 - Clear RX DMA On Error"]
256    #[inline(always)]
257    pub fn errsdma(&self) -> ERRSDMA_R {
258        ERRSDMA_R::new(((self.bits >> 6) & 1) != 0)
259    }
260    #[doc = "Bit 7 - Loopback Enable"]
261    #[inline(always)]
262    pub fn loopbk(&self) -> LOOPBK_R {
263        LOOPBK_R::new(((self.bits >> 7) & 1) != 0)
264    }
265    #[doc = "Bit 8 - Start-Frame UnBlock RX"]
266    #[inline(always)]
267    pub fn sfubrx(&self) -> SFUBRX_R {
268        SFUBRX_R::new(((self.bits >> 8) & 1) != 0)
269    }
270    #[doc = "Bit 9 - Multi-Processor Mode"]
271    #[inline(always)]
272    pub fn mpm(&self) -> MPM_R {
273        MPM_R::new(((self.bits >> 9) & 1) != 0)
274    }
275    #[doc = "Bit 10 - Multi-Processor Address-Bit"]
276    #[inline(always)]
277    pub fn mpab(&self) -> MPAB_R {
278        MPAB_R::new(((self.bits >> 10) & 1) != 0)
279    }
280    #[doc = "Bit 11 - Bit 8 Default Value"]
281    #[inline(always)]
282    pub fn bit8dv(&self) -> BIT8DV_R {
283        BIT8DV_R::new(((self.bits >> 11) & 1) != 0)
284    }
285    #[doc = "Bit 12 - RX DMA Wakeup"]
286    #[inline(always)]
287    pub fn rxdmawu(&self) -> RXDMAWU_R {
288        RXDMAWU_R::new(((self.bits >> 12) & 1) != 0)
289    }
290    #[doc = "Bit 13 - TX DMA Wakeup"]
291    #[inline(always)]
292    pub fn txdmawu(&self) -> TXDMAWU_R {
293        TXDMAWU_R::new(((self.bits >> 13) & 1) != 0)
294    }
295    #[doc = "Bits 14:15 - TX Delay Transmission"]
296    #[inline(always)]
297    pub fn txdelay(&self) -> TXDELAY_R {
298        TXDELAY_R::new(((self.bits >> 14) & 3) as u8)
299    }
300}
301impl W {
302    #[doc = "Bit 0 - Automatic Transmitter Tristate"]
303    #[inline(always)]
304    #[must_use]
305    pub fn autotri(&mut self) -> AUTOTRI_W<0> {
306        AUTOTRI_W::new(self)
307    }
308    #[doc = "Bit 1 - Data-Bit Mode"]
309    #[inline(always)]
310    #[must_use]
311    pub fn databits(&mut self) -> DATABITS_W<1> {
312        DATABITS_W::new(self)
313    }
314    #[doc = "Bits 2:3 - Parity-Bit Mode"]
315    #[inline(always)]
316    #[must_use]
317    pub fn parity(&mut self) -> PARITY_W<2> {
318        PARITY_W::new(self)
319    }
320    #[doc = "Bit 4 - Stop-Bit Mode"]
321    #[inline(always)]
322    #[must_use]
323    pub fn stopbits(&mut self) -> STOPBITS_W<4> {
324        STOPBITS_W::new(self)
325    }
326    #[doc = "Bit 5 - Invert Input And Output"]
327    #[inline(always)]
328    #[must_use]
329    pub fn inv(&mut self) -> INV_W<5> {
330        INV_W::new(self)
331    }
332    #[doc = "Bit 6 - Clear RX DMA On Error"]
333    #[inline(always)]
334    #[must_use]
335    pub fn errsdma(&mut self) -> ERRSDMA_W<6> {
336        ERRSDMA_W::new(self)
337    }
338    #[doc = "Bit 7 - Loopback Enable"]
339    #[inline(always)]
340    #[must_use]
341    pub fn loopbk(&mut self) -> LOOPBK_W<7> {
342        LOOPBK_W::new(self)
343    }
344    #[doc = "Bit 8 - Start-Frame UnBlock RX"]
345    #[inline(always)]
346    #[must_use]
347    pub fn sfubrx(&mut self) -> SFUBRX_W<8> {
348        SFUBRX_W::new(self)
349    }
350    #[doc = "Bit 9 - Multi-Processor Mode"]
351    #[inline(always)]
352    #[must_use]
353    pub fn mpm(&mut self) -> MPM_W<9> {
354        MPM_W::new(self)
355    }
356    #[doc = "Bit 10 - Multi-Processor Address-Bit"]
357    #[inline(always)]
358    #[must_use]
359    pub fn mpab(&mut self) -> MPAB_W<10> {
360        MPAB_W::new(self)
361    }
362    #[doc = "Bit 11 - Bit 8 Default Value"]
363    #[inline(always)]
364    #[must_use]
365    pub fn bit8dv(&mut self) -> BIT8DV_W<11> {
366        BIT8DV_W::new(self)
367    }
368    #[doc = "Bit 12 - RX DMA Wakeup"]
369    #[inline(always)]
370    #[must_use]
371    pub fn rxdmawu(&mut self) -> RXDMAWU_W<12> {
372        RXDMAWU_W::new(self)
373    }
374    #[doc = "Bit 13 - TX DMA Wakeup"]
375    #[inline(always)]
376    #[must_use]
377    pub fn txdmawu(&mut self) -> TXDMAWU_W<13> {
378        TXDMAWU_W::new(self)
379    }
380    #[doc = "Bits 14:15 - TX Delay Transmission"]
381    #[inline(always)]
382    #[must_use]
383    pub fn txdelay(&mut self) -> TXDELAY_W<14> {
384        TXDELAY_W::new(self)
385    }
386    #[doc = "Writes raw bits to the register."]
387    #[inline(always)]
388    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
389        self.0.bits(bits);
390        self
391    }
392}
393#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
394pub struct CTRL_SPEC;
395impl crate::RegisterSpec for CTRL_SPEC {
396    type Ux = u32;
397}
398#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
399impl crate::Readable for CTRL_SPEC {
400    type Reader = R;
401}
402#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
403impl crate::Writable for CTRL_SPEC {
404    type Writer = W;
405    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
406    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
407}
408#[doc = "`reset()` method sets CTRL to value 0"]
409impl crate::Resettable for CTRL_SPEC {
410    const RESET_VALUE: Self::Ux = 0;
411}
efm32gg_pac/efm32gg230/leuart0/ctrl.rs

efm32gg_pac/efm32gg230/leuart0/
ctrl.rs
