efm32gg_pac/efm32gg230/etm/
etmcr.rs

1#[doc = "Register `ETMCR` reader"]
2pub struct R(crate::R<ETMCR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ETMCR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ETMCR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ETMCR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ETMCR` writer"]
17pub struct W(crate::W<ETMCR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ETMCR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ETMCR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ETMCR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `POWERDWN` reader - ETM Control in low power mode"]
38pub type POWERDWN_R = crate::BitReader<bool>;
39#[doc = "Field `POWERDWN` writer - ETM Control in low power mode"]
40pub type POWERDWN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ETMCR_SPEC, bool, O>;
41#[doc = "Field `PORTSIZE` reader - ETM Port Size"]
42pub type PORTSIZE_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `PORTSIZE` writer - ETM Port Size"]
44pub type PORTSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ETMCR_SPEC, u8, u8, 3, O>;
45#[doc = "Field `STALL` reader - Stall Processor"]
46pub type STALL_R = crate::BitReader<bool>;
47#[doc = "Field `STALL` writer - Stall Processor"]
48pub type STALL_W<'a, const O: u8> = crate::BitWriter<'a, u32, ETMCR_SPEC, bool, O>;
49#[doc = "Field `BRANCHOUTPUT` reader - Branch Output"]
50pub type BRANCHOUTPUT_R = crate::BitReader<bool>;
51#[doc = "Field `BRANCHOUTPUT` writer - Branch Output"]
52pub type BRANCHOUTPUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, ETMCR_SPEC, bool, O>;
53#[doc = "Field `DBGREQCTRL` reader - Debug Request Control"]
54pub type DBGREQCTRL_R = crate::BitReader<bool>;
55#[doc = "Field `DBGREQCTRL` writer - Debug Request Control"]
56pub type DBGREQCTRL_W<'a, const O: u8> = crate::BitWriter<'a, u32, ETMCR_SPEC, bool, O>;
57#[doc = "Field `ETMPROG` reader - ETM Programming"]
58pub type ETMPROG_R = crate::BitReader<bool>;
59#[doc = "Field `ETMPROG` writer - ETM Programming"]
60pub type ETMPROG_W<'a, const O: u8> = crate::BitWriter<'a, u32, ETMCR_SPEC, bool, O>;
61#[doc = "Field `ETMPORTSEL` reader - ETM Port Selection"]
62pub type ETMPORTSEL_R = crate::BitReader<bool>;
63#[doc = "Field `ETMPORTSEL` writer - ETM Port Selection"]
64pub type ETMPORTSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, ETMCR_SPEC, bool, O>;
65#[doc = "Field `PORTMODE2` reader - Port Mode\\[2\\]"]
66pub type PORTMODE2_R = crate::BitReader<bool>;
67#[doc = "Field `PORTMODE2` writer - Port Mode\\[2\\]"]
68pub type PORTMODE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, ETMCR_SPEC, bool, O>;
69#[doc = "Field `PORTMODE` reader - Port Mode Control"]
70pub type PORTMODE_R = crate::FieldReader<u8, u8>;
71#[doc = "Field `PORTMODE` writer - Port Mode Control"]
72pub type PORTMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ETMCR_SPEC, u8, u8, 2, O>;
73#[doc = "Field `EPORTSIZE` reader - Port Size\\[3\\]"]
74pub type EPORTSIZE_R = crate::FieldReader<u8, u8>;
75#[doc = "Field `EPORTSIZE` writer - Port Size\\[3\\]"]
76pub type EPORTSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ETMCR_SPEC, u8, u8, 2, O>;
77#[doc = "Field `TSTAMPEN` reader - Time Stamp Enable"]
78pub type TSTAMPEN_R = crate::BitReader<bool>;
79#[doc = "Field `TSTAMPEN` writer - Time Stamp Enable"]
80pub type TSTAMPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ETMCR_SPEC, bool, O>;
81impl R {
82    #[doc = "Bit 0 - ETM Control in low power mode"]
83    #[inline(always)]
84    pub fn powerdwn(&self) -> POWERDWN_R {
85        POWERDWN_R::new((self.bits & 1) != 0)
86    }
87    #[doc = "Bits 4:6 - ETM Port Size"]
88    #[inline(always)]
89    pub fn portsize(&self) -> PORTSIZE_R {
90        PORTSIZE_R::new(((self.bits >> 4) & 7) as u8)
91    }
92    #[doc = "Bit 7 - Stall Processor"]
93    #[inline(always)]
94    pub fn stall(&self) -> STALL_R {
95        STALL_R::new(((self.bits >> 7) & 1) != 0)
96    }
97    #[doc = "Bit 8 - Branch Output"]
98    #[inline(always)]
99    pub fn branchoutput(&self) -> BRANCHOUTPUT_R {
100        BRANCHOUTPUT_R::new(((self.bits >> 8) & 1) != 0)
101    }
102    #[doc = "Bit 9 - Debug Request Control"]
103    #[inline(always)]
104    pub fn dbgreqctrl(&self) -> DBGREQCTRL_R {
105        DBGREQCTRL_R::new(((self.bits >> 9) & 1) != 0)
106    }
107    #[doc = "Bit 10 - ETM Programming"]
108    #[inline(always)]
109    pub fn etmprog(&self) -> ETMPROG_R {
110        ETMPROG_R::new(((self.bits >> 10) & 1) != 0)
111    }
112    #[doc = "Bit 11 - ETM Port Selection"]
113    #[inline(always)]
114    pub fn etmportsel(&self) -> ETMPORTSEL_R {
115        ETMPORTSEL_R::new(((self.bits >> 11) & 1) != 0)
116    }
117    #[doc = "Bit 13 - Port Mode\\[2\\]"]
118    #[inline(always)]
119    pub fn portmode2(&self) -> PORTMODE2_R {
120        PORTMODE2_R::new(((self.bits >> 13) & 1) != 0)
121    }
122    #[doc = "Bits 16:17 - Port Mode Control"]
123    #[inline(always)]
124    pub fn portmode(&self) -> PORTMODE_R {
125        PORTMODE_R::new(((self.bits >> 16) & 3) as u8)
126    }
127    #[doc = "Bits 21:22 - Port Size\\[3\\]"]
128    #[inline(always)]
129    pub fn eportsize(&self) -> EPORTSIZE_R {
130        EPORTSIZE_R::new(((self.bits >> 21) & 3) as u8)
131    }
132    #[doc = "Bit 28 - Time Stamp Enable"]
133    #[inline(always)]
134    pub fn tstampen(&self) -> TSTAMPEN_R {
135        TSTAMPEN_R::new(((self.bits >> 28) & 1) != 0)
136    }
137}
138impl W {
139    #[doc = "Bit 0 - ETM Control in low power mode"]
140    #[inline(always)]
141    #[must_use]
142    pub fn powerdwn(&mut self) -> POWERDWN_W<0> {
143        POWERDWN_W::new(self)
144    }
145    #[doc = "Bits 4:6 - ETM Port Size"]
146    #[inline(always)]
147    #[must_use]
148    pub fn portsize(&mut self) -> PORTSIZE_W<4> {
149        PORTSIZE_W::new(self)
150    }
151    #[doc = "Bit 7 - Stall Processor"]
152    #[inline(always)]
153    #[must_use]
154    pub fn stall(&mut self) -> STALL_W<7> {
155        STALL_W::new(self)
156    }
157    #[doc = "Bit 8 - Branch Output"]
158    #[inline(always)]
159    #[must_use]
160    pub fn branchoutput(&mut self) -> BRANCHOUTPUT_W<8> {
161        BRANCHOUTPUT_W::new(self)
162    }
163    #[doc = "Bit 9 - Debug Request Control"]
164    #[inline(always)]
165    #[must_use]
166    pub fn dbgreqctrl(&mut self) -> DBGREQCTRL_W<9> {
167        DBGREQCTRL_W::new(self)
168    }
169    #[doc = "Bit 10 - ETM Programming"]
170    #[inline(always)]
171    #[must_use]
172    pub fn etmprog(&mut self) -> ETMPROG_W<10> {
173        ETMPROG_W::new(self)
174    }
175    #[doc = "Bit 11 - ETM Port Selection"]
176    #[inline(always)]
177    #[must_use]
178    pub fn etmportsel(&mut self) -> ETMPORTSEL_W<11> {
179        ETMPORTSEL_W::new(self)
180    }
181    #[doc = "Bit 13 - Port Mode\\[2\\]"]
182    #[inline(always)]
183    #[must_use]
184    pub fn portmode2(&mut self) -> PORTMODE2_W<13> {
185        PORTMODE2_W::new(self)
186    }
187    #[doc = "Bits 16:17 - Port Mode Control"]
188    #[inline(always)]
189    #[must_use]
190    pub fn portmode(&mut self) -> PORTMODE_W<16> {
191        PORTMODE_W::new(self)
192    }
193    #[doc = "Bits 21:22 - Port Size\\[3\\]"]
194    #[inline(always)]
195    #[must_use]
196    pub fn eportsize(&mut self) -> EPORTSIZE_W<21> {
197        EPORTSIZE_W::new(self)
198    }
199    #[doc = "Bit 28 - Time Stamp Enable"]
200    #[inline(always)]
201    #[must_use]
202    pub fn tstampen(&mut self) -> TSTAMPEN_W<28> {
203        TSTAMPEN_W::new(self)
204    }
205    #[doc = "Writes raw bits to the register."]
206    #[inline(always)]
207    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
208        self.0.bits(bits);
209        self
210    }
211}
212#[doc = "Main Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [etmcr](index.html) module"]
213pub struct ETMCR_SPEC;
214impl crate::RegisterSpec for ETMCR_SPEC {
215    type Ux = u32;
216}
217#[doc = "`read()` method returns [etmcr::R](R) reader structure"]
218impl crate::Readable for ETMCR_SPEC {
219    type Reader = R;
220}
221#[doc = "`write(|w| ..)` method takes [etmcr::W](W) writer structure"]
222impl crate::Writable for ETMCR_SPEC {
223    type Writer = W;
224    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
225    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
226}
227#[doc = "`reset()` method sets ETMCR to value 0x0411"]
228impl crate::Resettable for ETMCR_SPEC {
229    const RESET_VALUE: Self::Ux = 0x0411;
230}
efm32gg_pac/efm32gg230/etm/etmcr.rs

efm32gg_pac/efm32gg230/etm/
etmcr.rs
