efm32gg_pac/efm32gg230/emu/
pwrconf.rs

1#[doc = "Register `PWRCONF` reader"]
2pub struct R(crate::R<PWRCONF_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PWRCONF_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PWRCONF_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PWRCONF_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PWRCONF` writer"]
17pub struct W(crate::W<PWRCONF_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PWRCONF_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PWRCONF_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PWRCONF_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `VOUTWEAK` reader - BU_VOUT weak enable"]
38pub type VOUTWEAK_R = crate::BitReader<bool>;
39#[doc = "Field `VOUTWEAK` writer - BU_VOUT weak enable"]
40pub type VOUTWEAK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PWRCONF_SPEC, bool, O>;
41#[doc = "Field `VOUTMED` reader - BU_VOUT medium enable"]
42pub type VOUTMED_R = crate::BitReader<bool>;
43#[doc = "Field `VOUTMED` writer - BU_VOUT medium enable"]
44pub type VOUTMED_W<'a, const O: u8> = crate::BitWriter<'a, u32, PWRCONF_SPEC, bool, O>;
45#[doc = "Field `VOUTSTRONG` reader - BU_VOUT strong enable"]
46pub type VOUTSTRONG_R = crate::BitReader<bool>;
47#[doc = "Field `VOUTSTRONG` writer - BU_VOUT strong enable"]
48pub type VOUTSTRONG_W<'a, const O: u8> = crate::BitWriter<'a, u32, PWRCONF_SPEC, bool, O>;
49#[doc = "Field `PWRRES` reader - Power domain resistor select"]
50pub type PWRRES_R = crate::FieldReader<u8, PWRRES_A>;
51#[doc = "Power domain resistor select\n\nValue on reset: 0"]
52#[derive(Clone, Copy, Debug, PartialEq, Eq)]
53#[repr(u8)]
54pub enum PWRRES_A {
55    #[doc = "0: Main power and backup power connected with RES0 series resistance."]
56    RES0 = 0,
57    #[doc = "1: Main power and backup power connected with RES1 series resistance."]
58    RES1 = 1,
59    #[doc = "2: Main power and backup power connected with RES2 series resistance."]
60    RES2 = 2,
61    #[doc = "3: Main power and backup power connected with RES3 series resistance."]
62    RES3 = 3,
63}
64impl From<PWRRES_A> for u8 {
65    #[inline(always)]
66    fn from(variant: PWRRES_A) -> Self {
67        variant as _
68    }
69}
70impl PWRRES_R {
71    #[doc = "Get enumerated values variant"]
72    #[inline(always)]
73    pub fn variant(&self) -> PWRRES_A {
74        match self.bits {
75            0 => PWRRES_A::RES0,
76            1 => PWRRES_A::RES1,
77            2 => PWRRES_A::RES2,
78            3 => PWRRES_A::RES3,
79            _ => unreachable!(),
80        }
81    }
82    #[doc = "Checks if the value of the field is `RES0`"]
83    #[inline(always)]
84    pub fn is_res0(&self) -> bool {
85        *self == PWRRES_A::RES0
86    }
87    #[doc = "Checks if the value of the field is `RES1`"]
88    #[inline(always)]
89    pub fn is_res1(&self) -> bool {
90        *self == PWRRES_A::RES1
91    }
92    #[doc = "Checks if the value of the field is `RES2`"]
93    #[inline(always)]
94    pub fn is_res2(&self) -> bool {
95        *self == PWRRES_A::RES2
96    }
97    #[doc = "Checks if the value of the field is `RES3`"]
98    #[inline(always)]
99    pub fn is_res3(&self) -> bool {
100        *self == PWRRES_A::RES3
101    }
102}
103#[doc = "Field `PWRRES` writer - Power domain resistor select"]
104pub type PWRRES_W<'a, const O: u8> =
105    crate::FieldWriterSafe<'a, u32, PWRCONF_SPEC, u8, PWRRES_A, 2, O>;
106impl<'a, const O: u8> PWRRES_W<'a, O> {
107    #[doc = "Main power and backup power connected with RES0 series resistance."]
108    #[inline(always)]
109    pub fn res0(self) -> &'a mut W {
110        self.variant(PWRRES_A::RES0)
111    }
112    #[doc = "Main power and backup power connected with RES1 series resistance."]
113    #[inline(always)]
114    pub fn res1(self) -> &'a mut W {
115        self.variant(PWRRES_A::RES1)
116    }
117    #[doc = "Main power and backup power connected with RES2 series resistance."]
118    #[inline(always)]
119    pub fn res2(self) -> &'a mut W {
120        self.variant(PWRRES_A::RES2)
121    }
122    #[doc = "Main power and backup power connected with RES3 series resistance."]
123    #[inline(always)]
124    pub fn res3(self) -> &'a mut W {
125        self.variant(PWRRES_A::RES3)
126    }
127}
128impl R {
129    #[doc = "Bit 0 - BU_VOUT weak enable"]
130    #[inline(always)]
131    pub fn voutweak(&self) -> VOUTWEAK_R {
132        VOUTWEAK_R::new((self.bits & 1) != 0)
133    }
134    #[doc = "Bit 1 - BU_VOUT medium enable"]
135    #[inline(always)]
136    pub fn voutmed(&self) -> VOUTMED_R {
137        VOUTMED_R::new(((self.bits >> 1) & 1) != 0)
138    }
139    #[doc = "Bit 2 - BU_VOUT strong enable"]
140    #[inline(always)]
141    pub fn voutstrong(&self) -> VOUTSTRONG_R {
142        VOUTSTRONG_R::new(((self.bits >> 2) & 1) != 0)
143    }
144    #[doc = "Bits 3:4 - Power domain resistor select"]
145    #[inline(always)]
146    pub fn pwrres(&self) -> PWRRES_R {
147        PWRRES_R::new(((self.bits >> 3) & 3) as u8)
148    }
149}
150impl W {
151    #[doc = "Bit 0 - BU_VOUT weak enable"]
152    #[inline(always)]
153    #[must_use]
154    pub fn voutweak(&mut self) -> VOUTWEAK_W<0> {
155        VOUTWEAK_W::new(self)
156    }
157    #[doc = "Bit 1 - BU_VOUT medium enable"]
158    #[inline(always)]
159    #[must_use]
160    pub fn voutmed(&mut self) -> VOUTMED_W<1> {
161        VOUTMED_W::new(self)
162    }
163    #[doc = "Bit 2 - BU_VOUT strong enable"]
164    #[inline(always)]
165    #[must_use]
166    pub fn voutstrong(&mut self) -> VOUTSTRONG_W<2> {
167        VOUTSTRONG_W::new(self)
168    }
169    #[doc = "Bits 3:4 - Power domain resistor select"]
170    #[inline(always)]
171    #[must_use]
172    pub fn pwrres(&mut self) -> PWRRES_W<3> {
173        PWRRES_W::new(self)
174    }
175    #[doc = "Writes raw bits to the register."]
176    #[inline(always)]
177    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
178        self.0.bits(bits);
179        self
180    }
181}
182#[doc = "Power connection configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pwrconf](index.html) module"]
183pub struct PWRCONF_SPEC;
184impl crate::RegisterSpec for PWRCONF_SPEC {
185    type Ux = u32;
186}
187#[doc = "`read()` method returns [pwrconf::R](R) reader structure"]
188impl crate::Readable for PWRCONF_SPEC {
189    type Reader = R;
190}
191#[doc = "`write(|w| ..)` method takes [pwrconf::W](W) writer structure"]
192impl crate::Writable for PWRCONF_SPEC {
193    type Writer = W;
194    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
195    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
196}
197#[doc = "`reset()` method sets PWRCONF to value 0"]
198impl crate::Resettable for PWRCONF_SPEC {
199    const RESET_VALUE: Self::Ux = 0;
200}
efm32gg_pac/efm32gg230/emu/pwrconf.rs

efm32gg_pac/efm32gg230/emu/
pwrconf.rs
