efm32gg_pac/efm32gg995/usb/
diep0_tsiz.rs

1#[doc = "Register `DIEP0_TSIZ` reader"]
2pub struct R(crate::R<DIEP0_TSIZ_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DIEP0_TSIZ_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DIEP0_TSIZ_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DIEP0_TSIZ_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DIEP0_TSIZ` writer"]
17pub struct W(crate::W<DIEP0_TSIZ_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DIEP0_TSIZ_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DIEP0_TSIZ_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DIEP0_TSIZ_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `XFERSIZE` reader - Transfer Size"]
38pub type XFERSIZE_R = crate::FieldReader<u32, u32>;
39#[doc = "Field `XFERSIZE` writer - Transfer Size"]
40pub type XFERSIZE_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, DIEP0_TSIZ_SPEC, u32, u32, 19, O>;
42#[doc = "Field `PKTCNT` reader - Packet Count"]
43pub type PKTCNT_R = crate::FieldReader<u16, u16>;
44#[doc = "Field `PKTCNT` writer - Packet Count"]
45pub type PKTCNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEP0_TSIZ_SPEC, u16, u16, 10, O>;
46#[doc = "Field `MC` reader - Multi Count"]
47pub type MC_R = crate::FieldReader<u8, u8>;
48#[doc = "Field `MC` writer - Multi Count"]
49pub type MC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DIEP0_TSIZ_SPEC, u8, u8, 2, O>;
50impl R {
51    #[doc = "Bits 0:18 - Transfer Size"]
52    #[inline(always)]
53    pub fn xfersize(&self) -> XFERSIZE_R {
54        XFERSIZE_R::new(self.bits & 0x0007_ffff)
55    }
56    #[doc = "Bits 19:28 - Packet Count"]
57    #[inline(always)]
58    pub fn pktcnt(&self) -> PKTCNT_R {
59        PKTCNT_R::new(((self.bits >> 19) & 0x03ff) as u16)
60    }
61    #[doc = "Bits 29:30 - Multi Count"]
62    #[inline(always)]
63    pub fn mc(&self) -> MC_R {
64        MC_R::new(((self.bits >> 29) & 3) as u8)
65    }
66}
67impl W {
68    #[doc = "Bits 0:18 - Transfer Size"]
69    #[inline(always)]
70    #[must_use]
71    pub fn xfersize(&mut self) -> XFERSIZE_W<0> {
72        XFERSIZE_W::new(self)
73    }
74    #[doc = "Bits 19:28 - Packet Count"]
75    #[inline(always)]
76    #[must_use]
77    pub fn pktcnt(&mut self) -> PKTCNT_W<19> {
78        PKTCNT_W::new(self)
79    }
80    #[doc = "Bits 29:30 - Multi Count"]
81    #[inline(always)]
82    #[must_use]
83    pub fn mc(&mut self) -> MC_W<29> {
84        MC_W::new(self)
85    }
86    #[doc = "Writes raw bits to the register."]
87    #[inline(always)]
88    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
89        self.0.bits(bits);
90        self
91    }
92}
93#[doc = "Device IN Endpoint x+1 Transfer Size Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [diep0_tsiz](index.html) module"]
94pub struct DIEP0_TSIZ_SPEC;
95impl crate::RegisterSpec for DIEP0_TSIZ_SPEC {
96    type Ux = u32;
97}
98#[doc = "`read()` method returns [diep0_tsiz::R](R) reader structure"]
99impl crate::Readable for DIEP0_TSIZ_SPEC {
100    type Reader = R;
101}
102#[doc = "`write(|w| ..)` method takes [diep0_tsiz::W](W) writer structure"]
103impl crate::Writable for DIEP0_TSIZ_SPEC {
104    type Writer = W;
105    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
106    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
107}
108#[doc = "`reset()` method sets DIEP0_TSIZ to value 0"]
109impl crate::Resettable for DIEP0_TSIZ_SPEC {
110    const RESET_VALUE: Self::Ux = 0;
111}
efm32gg_pac/efm32gg995/usb/diep0_tsiz.rs

efm32gg_pac/efm32gg995/usb/
diep0_tsiz.rs
