efm32gg_pac/efm32gg995/pcnt1/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub struct R(crate::R<CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRL` writer"]
17pub struct W(crate::W<CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MODE` reader - Mode Select"]
38pub type MODE_R = crate::FieldReader<u8, MODE_A>;
39#[doc = "Mode Select\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum MODE_A {
43    #[doc = "0: The module is disabled."]
44    DISABLE = 0,
45    #[doc = "1: Single input LFACLK oversampling mode (available in EM0-EM2)."]
46    OVSSINGLE = 1,
47    #[doc = "2: Externally clocked single input counter mode (available in EM0-EM3)."]
48    EXTCLKSINGLE = 2,
49    #[doc = "3: Externally clocked quadrature decoder mode (available in EM0-EM3)."]
50    EXTCLKQUAD = 3,
51}
52impl From<MODE_A> for u8 {
53    #[inline(always)]
54    fn from(variant: MODE_A) -> Self {
55        variant as _
56    }
57}
58impl MODE_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> MODE_A {
62        match self.bits {
63            0 => MODE_A::DISABLE,
64            1 => MODE_A::OVSSINGLE,
65            2 => MODE_A::EXTCLKSINGLE,
66            3 => MODE_A::EXTCLKQUAD,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `DISABLE`"]
71    #[inline(always)]
72    pub fn is_disable(&self) -> bool {
73        *self == MODE_A::DISABLE
74    }
75    #[doc = "Checks if the value of the field is `OVSSINGLE`"]
76    #[inline(always)]
77    pub fn is_ovssingle(&self) -> bool {
78        *self == MODE_A::OVSSINGLE
79    }
80    #[doc = "Checks if the value of the field is `EXTCLKSINGLE`"]
81    #[inline(always)]
82    pub fn is_extclksingle(&self) -> bool {
83        *self == MODE_A::EXTCLKSINGLE
84    }
85    #[doc = "Checks if the value of the field is `EXTCLKQUAD`"]
86    #[inline(always)]
87    pub fn is_extclkquad(&self) -> bool {
88        *self == MODE_A::EXTCLKQUAD
89    }
90}
91#[doc = "Field `MODE` writer - Mode Select"]
92pub type MODE_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, MODE_A, 2, O>;
93impl<'a, const O: u8> MODE_W<'a, O> {
94    #[doc = "The module is disabled."]
95    #[inline(always)]
96    pub fn disable(self) -> &'a mut W {
97        self.variant(MODE_A::DISABLE)
98    }
99    #[doc = "Single input LFACLK oversampling mode (available in EM0-EM2)."]
100    #[inline(always)]
101    pub fn ovssingle(self) -> &'a mut W {
102        self.variant(MODE_A::OVSSINGLE)
103    }
104    #[doc = "Externally clocked single input counter mode (available in EM0-EM3)."]
105    #[inline(always)]
106    pub fn extclksingle(self) -> &'a mut W {
107        self.variant(MODE_A::EXTCLKSINGLE)
108    }
109    #[doc = "Externally clocked quadrature decoder mode (available in EM0-EM3)."]
110    #[inline(always)]
111    pub fn extclkquad(self) -> &'a mut W {
112        self.variant(MODE_A::EXTCLKQUAD)
113    }
114}
115#[doc = "Field `CNTDIR` reader - Non-Quadrature Mode Counter Direction Control"]
116pub type CNTDIR_R = crate::BitReader<bool>;
117#[doc = "Field `CNTDIR` writer - Non-Quadrature Mode Counter Direction Control"]
118pub type CNTDIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
119#[doc = "Field `EDGE` reader - Edge Select"]
120pub type EDGE_R = crate::BitReader<bool>;
121#[doc = "Field `EDGE` writer - Edge Select"]
122pub type EDGE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
123#[doc = "Field `FILT` reader - Enable Digital Pulse Width Filter"]
124pub type FILT_R = crate::BitReader<bool>;
125#[doc = "Field `FILT` writer - Enable Digital Pulse Width Filter"]
126pub type FILT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
127#[doc = "Field `RSTEN` reader - Enable PCNT Clock Domain Reset"]
128pub type RSTEN_R = crate::BitReader<bool>;
129#[doc = "Field `RSTEN` writer - Enable PCNT Clock Domain Reset"]
130pub type RSTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
131#[doc = "Field `HYST` reader - Enable Hysteresis"]
132pub type HYST_R = crate::BitReader<bool>;
133#[doc = "Field `HYST` writer - Enable Hysteresis"]
134pub type HYST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
135#[doc = "Field `S1CDIR` reader - Count direction determined by S1"]
136pub type S1CDIR_R = crate::BitReader<bool>;
137#[doc = "Field `S1CDIR` writer - Count direction determined by S1"]
138pub type S1CDIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRL_SPEC, bool, O>;
139#[doc = "Field `CNTEV` reader - Controls when the counter counts"]
140pub type CNTEV_R = crate::FieldReader<u8, CNTEV_A>;
141#[doc = "Controls when the counter counts\n\nValue on reset: 0"]
142#[derive(Clone, Copy, Debug, PartialEq, Eq)]
143#[repr(u8)]
144pub enum CNTEV_A {
145    #[doc = "0: Counts up on up-count and down on down-count events."]
146    BOTH = 0,
147    #[doc = "1: Only counts up on up-count events."]
148    UP = 1,
149    #[doc = "2: Only counts down on down-count events."]
150    DOWN = 2,
151    #[doc = "3: Never counts."]
152    NONE = 3,
153}
154impl From<CNTEV_A> for u8 {
155    #[inline(always)]
156    fn from(variant: CNTEV_A) -> Self {
157        variant as _
158    }
159}
160impl CNTEV_R {
161    #[doc = "Get enumerated values variant"]
162    #[inline(always)]
163    pub fn variant(&self) -> CNTEV_A {
164        match self.bits {
165            0 => CNTEV_A::BOTH,
166            1 => CNTEV_A::UP,
167            2 => CNTEV_A::DOWN,
168            3 => CNTEV_A::NONE,
169            _ => unreachable!(),
170        }
171    }
172    #[doc = "Checks if the value of the field is `BOTH`"]
173    #[inline(always)]
174    pub fn is_both(&self) -> bool {
175        *self == CNTEV_A::BOTH
176    }
177    #[doc = "Checks if the value of the field is `UP`"]
178    #[inline(always)]
179    pub fn is_up(&self) -> bool {
180        *self == CNTEV_A::UP
181    }
182    #[doc = "Checks if the value of the field is `DOWN`"]
183    #[inline(always)]
184    pub fn is_down(&self) -> bool {
185        *self == CNTEV_A::DOWN
186    }
187    #[doc = "Checks if the value of the field is `NONE`"]
188    #[inline(always)]
189    pub fn is_none(&self) -> bool {
190        *self == CNTEV_A::NONE
191    }
192}
193#[doc = "Field `CNTEV` writer - Controls when the counter counts"]
194pub type CNTEV_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, CNTEV_A, 2, O>;
195impl<'a, const O: u8> CNTEV_W<'a, O> {
196    #[doc = "Counts up on up-count and down on down-count events."]
197    #[inline(always)]
198    pub fn both(self) -> &'a mut W {
199        self.variant(CNTEV_A::BOTH)
200    }
201    #[doc = "Only counts up on up-count events."]
202    #[inline(always)]
203    pub fn up(self) -> &'a mut W {
204        self.variant(CNTEV_A::UP)
205    }
206    #[doc = "Only counts down on down-count events."]
207    #[inline(always)]
208    pub fn down(self) -> &'a mut W {
209        self.variant(CNTEV_A::DOWN)
210    }
211    #[doc = "Never counts."]
212    #[inline(always)]
213    pub fn none(self) -> &'a mut W {
214        self.variant(CNTEV_A::NONE)
215    }
216}
217#[doc = "Field `AUXCNTEV` reader - Controls when the auxiliary counter counts"]
218pub type AUXCNTEV_R = crate::FieldReader<u8, AUXCNTEV_A>;
219#[doc = "Controls when the auxiliary counter counts\n\nValue on reset: 0"]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221#[repr(u8)]
222pub enum AUXCNTEV_A {
223    #[doc = "0: Never counts."]
224    NONE = 0,
225    #[doc = "1: Counts up on up-count events."]
226    UP = 1,
227    #[doc = "2: Counts up on down-count events."]
228    DOWN = 2,
229    #[doc = "3: Counts up on both up-count and down-count events."]
230    BOTH = 3,
231}
232impl From<AUXCNTEV_A> for u8 {
233    #[inline(always)]
234    fn from(variant: AUXCNTEV_A) -> Self {
235        variant as _
236    }
237}
238impl AUXCNTEV_R {
239    #[doc = "Get enumerated values variant"]
240    #[inline(always)]
241    pub fn variant(&self) -> AUXCNTEV_A {
242        match self.bits {
243            0 => AUXCNTEV_A::NONE,
244            1 => AUXCNTEV_A::UP,
245            2 => AUXCNTEV_A::DOWN,
246            3 => AUXCNTEV_A::BOTH,
247            _ => unreachable!(),
248        }
249    }
250    #[doc = "Checks if the value of the field is `NONE`"]
251    #[inline(always)]
252    pub fn is_none(&self) -> bool {
253        *self == AUXCNTEV_A::NONE
254    }
255    #[doc = "Checks if the value of the field is `UP`"]
256    #[inline(always)]
257    pub fn is_up(&self) -> bool {
258        *self == AUXCNTEV_A::UP
259    }
260    #[doc = "Checks if the value of the field is `DOWN`"]
261    #[inline(always)]
262    pub fn is_down(&self) -> bool {
263        *self == AUXCNTEV_A::DOWN
264    }
265    #[doc = "Checks if the value of the field is `BOTH`"]
266    #[inline(always)]
267    pub fn is_both(&self) -> bool {
268        *self == AUXCNTEV_A::BOTH
269    }
270}
271#[doc = "Field `AUXCNTEV` writer - Controls when the auxiliary counter counts"]
272pub type AUXCNTEV_W<'a, const O: u8> =
273    crate::FieldWriterSafe<'a, u32, CTRL_SPEC, u8, AUXCNTEV_A, 2, O>;
274impl<'a, const O: u8> AUXCNTEV_W<'a, O> {
275    #[doc = "Never counts."]
276    #[inline(always)]
277    pub fn none(self) -> &'a mut W {
278        self.variant(AUXCNTEV_A::NONE)
279    }
280    #[doc = "Counts up on up-count events."]
281    #[inline(always)]
282    pub fn up(self) -> &'a mut W {
283        self.variant(AUXCNTEV_A::UP)
284    }
285    #[doc = "Counts up on down-count events."]
286    #[inline(always)]
287    pub fn down(self) -> &'a mut W {
288        self.variant(AUXCNTEV_A::DOWN)
289    }
290    #[doc = "Counts up on both up-count and down-count events."]
291    #[inline(always)]
292    pub fn both(self) -> &'a mut W {
293        self.variant(AUXCNTEV_A::BOTH)
294    }
295}
296impl R {
297    #[doc = "Bits 0:1 - Mode Select"]
298    #[inline(always)]
299    pub fn mode(&self) -> MODE_R {
300        MODE_R::new((self.bits & 3) as u8)
301    }
302    #[doc = "Bit 2 - Non-Quadrature Mode Counter Direction Control"]
303    #[inline(always)]
304    pub fn cntdir(&self) -> CNTDIR_R {
305        CNTDIR_R::new(((self.bits >> 2) & 1) != 0)
306    }
307    #[doc = "Bit 3 - Edge Select"]
308    #[inline(always)]
309    pub fn edge(&self) -> EDGE_R {
310        EDGE_R::new(((self.bits >> 3) & 1) != 0)
311    }
312    #[doc = "Bit 4 - Enable Digital Pulse Width Filter"]
313    #[inline(always)]
314    pub fn filt(&self) -> FILT_R {
315        FILT_R::new(((self.bits >> 4) & 1) != 0)
316    }
317    #[doc = "Bit 5 - Enable PCNT Clock Domain Reset"]
318    #[inline(always)]
319    pub fn rsten(&self) -> RSTEN_R {
320        RSTEN_R::new(((self.bits >> 5) & 1) != 0)
321    }
322    #[doc = "Bit 8 - Enable Hysteresis"]
323    #[inline(always)]
324    pub fn hyst(&self) -> HYST_R {
325        HYST_R::new(((self.bits >> 8) & 1) != 0)
326    }
327    #[doc = "Bit 9 - Count direction determined by S1"]
328    #[inline(always)]
329    pub fn s1cdir(&self) -> S1CDIR_R {
330        S1CDIR_R::new(((self.bits >> 9) & 1) != 0)
331    }
332    #[doc = "Bits 10:11 - Controls when the counter counts"]
333    #[inline(always)]
334    pub fn cntev(&self) -> CNTEV_R {
335        CNTEV_R::new(((self.bits >> 10) & 3) as u8)
336    }
337    #[doc = "Bits 14:15 - Controls when the auxiliary counter counts"]
338    #[inline(always)]
339    pub fn auxcntev(&self) -> AUXCNTEV_R {
340        AUXCNTEV_R::new(((self.bits >> 14) & 3) as u8)
341    }
342}
343impl W {
344    #[doc = "Bits 0:1 - Mode Select"]
345    #[inline(always)]
346    #[must_use]
347    pub fn mode(&mut self) -> MODE_W<0> {
348        MODE_W::new(self)
349    }
350    #[doc = "Bit 2 - Non-Quadrature Mode Counter Direction Control"]
351    #[inline(always)]
352    #[must_use]
353    pub fn cntdir(&mut self) -> CNTDIR_W<2> {
354        CNTDIR_W::new(self)
355    }
356    #[doc = "Bit 3 - Edge Select"]
357    #[inline(always)]
358    #[must_use]
359    pub fn edge(&mut self) -> EDGE_W<3> {
360        EDGE_W::new(self)
361    }
362    #[doc = "Bit 4 - Enable Digital Pulse Width Filter"]
363    #[inline(always)]
364    #[must_use]
365    pub fn filt(&mut self) -> FILT_W<4> {
366        FILT_W::new(self)
367    }
368    #[doc = "Bit 5 - Enable PCNT Clock Domain Reset"]
369    #[inline(always)]
370    #[must_use]
371    pub fn rsten(&mut self) -> RSTEN_W<5> {
372        RSTEN_W::new(self)
373    }
374    #[doc = "Bit 8 - Enable Hysteresis"]
375    #[inline(always)]
376    #[must_use]
377    pub fn hyst(&mut self) -> HYST_W<8> {
378        HYST_W::new(self)
379    }
380    #[doc = "Bit 9 - Count direction determined by S1"]
381    #[inline(always)]
382    #[must_use]
383    pub fn s1cdir(&mut self) -> S1CDIR_W<9> {
384        S1CDIR_W::new(self)
385    }
386    #[doc = "Bits 10:11 - Controls when the counter counts"]
387    #[inline(always)]
388    #[must_use]
389    pub fn cntev(&mut self) -> CNTEV_W<10> {
390        CNTEV_W::new(self)
391    }
392    #[doc = "Bits 14:15 - Controls when the auxiliary counter counts"]
393    #[inline(always)]
394    #[must_use]
395    pub fn auxcntev(&mut self) -> AUXCNTEV_W<14> {
396        AUXCNTEV_W::new(self)
397    }
398    #[doc = "Writes raw bits to the register."]
399    #[inline(always)]
400    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
401        self.0.bits(bits);
402        self
403    }
404}
405#[doc = "Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"]
406pub struct CTRL_SPEC;
407impl crate::RegisterSpec for CTRL_SPEC {
408    type Ux = u32;
409}
410#[doc = "`read()` method returns [ctrl::R](R) reader structure"]
411impl crate::Readable for CTRL_SPEC {
412    type Reader = R;
413}
414#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"]
415impl crate::Writable for CTRL_SPEC {
416    type Writer = W;
417    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
418    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
419}
420#[doc = "`reset()` method sets CTRL to value 0"]
421impl crate::Resettable for CTRL_SPEC {
422    const RESET_VALUE: Self::Ux = 0;
423}
efm32gg_pac/efm32gg995/pcnt1/ctrl.rs

efm32gg_pac/efm32gg995/pcnt1/
ctrl.rs
