efm32gg_pac/efm32gg230/usart0/
route.rs

1#[doc = "Register `ROUTE` reader"]
2pub struct R(crate::R<ROUTE_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ROUTE_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ROUTE_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ROUTE_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ROUTE` writer"]
17pub struct W(crate::W<ROUTE_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ROUTE_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ROUTE_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ROUTE_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `RXPEN` reader - RX Pin Enable"]
38pub type RXPEN_R = crate::BitReader<bool>;
39#[doc = "Field `RXPEN` writer - RX Pin Enable"]
40pub type RXPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTE_SPEC, bool, O>;
41#[doc = "Field `TXPEN` reader - TX Pin Enable"]
42pub type TXPEN_R = crate::BitReader<bool>;
43#[doc = "Field `TXPEN` writer - TX Pin Enable"]
44pub type TXPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTE_SPEC, bool, O>;
45#[doc = "Field `CSPEN` reader - CS Pin Enable"]
46pub type CSPEN_R = crate::BitReader<bool>;
47#[doc = "Field `CSPEN` writer - CS Pin Enable"]
48pub type CSPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTE_SPEC, bool, O>;
49#[doc = "Field `CLKPEN` reader - CLK Pin Enable"]
50pub type CLKPEN_R = crate::BitReader<bool>;
51#[doc = "Field `CLKPEN` writer - CLK Pin Enable"]
52pub type CLKPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ROUTE_SPEC, bool, O>;
53#[doc = "Field `LOCATION` reader - I/O Location"]
54pub type LOCATION_R = crate::FieldReader<u8, LOCATION_A>;
55#[doc = "I/O Location\n\nValue on reset: 0"]
56#[derive(Clone, Copy, Debug, PartialEq, Eq)]
57#[repr(u8)]
58pub enum LOCATION_A {
59    #[doc = "0: Location 0"]
60    LOC0 = 0,
61    #[doc = "1: Location 1"]
62    LOC1 = 1,
63    #[doc = "2: Location 2"]
64    LOC2 = 2,
65    #[doc = "3: Location 3"]
66    LOC3 = 3,
67    #[doc = "4: Location 4"]
68    LOC4 = 4,
69    #[doc = "5: Location 5"]
70    LOC5 = 5,
71}
72impl From<LOCATION_A> for u8 {
73    #[inline(always)]
74    fn from(variant: LOCATION_A) -> Self {
75        variant as _
76    }
77}
78impl LOCATION_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub fn variant(&self) -> Option<LOCATION_A> {
82        match self.bits {
83            0 => Some(LOCATION_A::LOC0),
84            1 => Some(LOCATION_A::LOC1),
85            2 => Some(LOCATION_A::LOC2),
86            3 => Some(LOCATION_A::LOC3),
87            4 => Some(LOCATION_A::LOC4),
88            5 => Some(LOCATION_A::LOC5),
89            _ => None,
90        }
91    }
92    #[doc = "Checks if the value of the field is `LOC0`"]
93    #[inline(always)]
94    pub fn is_loc0(&self) -> bool {
95        *self == LOCATION_A::LOC0
96    }
97    #[doc = "Checks if the value of the field is `LOC1`"]
98    #[inline(always)]
99    pub fn is_loc1(&self) -> bool {
100        *self == LOCATION_A::LOC1
101    }
102    #[doc = "Checks if the value of the field is `LOC2`"]
103    #[inline(always)]
104    pub fn is_loc2(&self) -> bool {
105        *self == LOCATION_A::LOC2
106    }
107    #[doc = "Checks if the value of the field is `LOC3`"]
108    #[inline(always)]
109    pub fn is_loc3(&self) -> bool {
110        *self == LOCATION_A::LOC3
111    }
112    #[doc = "Checks if the value of the field is `LOC4`"]
113    #[inline(always)]
114    pub fn is_loc4(&self) -> bool {
115        *self == LOCATION_A::LOC4
116    }
117    #[doc = "Checks if the value of the field is `LOC5`"]
118    #[inline(always)]
119    pub fn is_loc5(&self) -> bool {
120        *self == LOCATION_A::LOC5
121    }
122}
123#[doc = "Field `LOCATION` writer - I/O Location"]
124pub type LOCATION_W<'a, const O: u8> =
125    crate::FieldWriter<'a, u32, ROUTE_SPEC, u8, LOCATION_A, 3, O>;
126impl<'a, const O: u8> LOCATION_W<'a, O> {
127    #[doc = "Location 0"]
128    #[inline(always)]
129    pub fn loc0(self) -> &'a mut W {
130        self.variant(LOCATION_A::LOC0)
131    }
132    #[doc = "Location 1"]
133    #[inline(always)]
134    pub fn loc1(self) -> &'a mut W {
135        self.variant(LOCATION_A::LOC1)
136    }
137    #[doc = "Location 2"]
138    #[inline(always)]
139    pub fn loc2(self) -> &'a mut W {
140        self.variant(LOCATION_A::LOC2)
141    }
142    #[doc = "Location 3"]
143    #[inline(always)]
144    pub fn loc3(self) -> &'a mut W {
145        self.variant(LOCATION_A::LOC3)
146    }
147    #[doc = "Location 4"]
148    #[inline(always)]
149    pub fn loc4(self) -> &'a mut W {
150        self.variant(LOCATION_A::LOC4)
151    }
152    #[doc = "Location 5"]
153    #[inline(always)]
154    pub fn loc5(self) -> &'a mut W {
155        self.variant(LOCATION_A::LOC5)
156    }
157}
158impl R {
159    #[doc = "Bit 0 - RX Pin Enable"]
160    #[inline(always)]
161    pub fn rxpen(&self) -> RXPEN_R {
162        RXPEN_R::new((self.bits & 1) != 0)
163    }
164    #[doc = "Bit 1 - TX Pin Enable"]
165    #[inline(always)]
166    pub fn txpen(&self) -> TXPEN_R {
167        TXPEN_R::new(((self.bits >> 1) & 1) != 0)
168    }
169    #[doc = "Bit 2 - CS Pin Enable"]
170    #[inline(always)]
171    pub fn cspen(&self) -> CSPEN_R {
172        CSPEN_R::new(((self.bits >> 2) & 1) != 0)
173    }
174    #[doc = "Bit 3 - CLK Pin Enable"]
175    #[inline(always)]
176    pub fn clkpen(&self) -> CLKPEN_R {
177        CLKPEN_R::new(((self.bits >> 3) & 1) != 0)
178    }
179    #[doc = "Bits 8:10 - I/O Location"]
180    #[inline(always)]
181    pub fn location(&self) -> LOCATION_R {
182        LOCATION_R::new(((self.bits >> 8) & 7) as u8)
183    }
184}
185impl W {
186    #[doc = "Bit 0 - RX Pin Enable"]
187    #[inline(always)]
188    #[must_use]
189    pub fn rxpen(&mut self) -> RXPEN_W<0> {
190        RXPEN_W::new(self)
191    }
192    #[doc = "Bit 1 - TX Pin Enable"]
193    #[inline(always)]
194    #[must_use]
195    pub fn txpen(&mut self) -> TXPEN_W<1> {
196        TXPEN_W::new(self)
197    }
198    #[doc = "Bit 2 - CS Pin Enable"]
199    #[inline(always)]
200    #[must_use]
201    pub fn cspen(&mut self) -> CSPEN_W<2> {
202        CSPEN_W::new(self)
203    }
204    #[doc = "Bit 3 - CLK Pin Enable"]
205    #[inline(always)]
206    #[must_use]
207    pub fn clkpen(&mut self) -> CLKPEN_W<3> {
208        CLKPEN_W::new(self)
209    }
210    #[doc = "Bits 8:10 - I/O Location"]
211    #[inline(always)]
212    #[must_use]
213    pub fn location(&mut self) -> LOCATION_W<8> {
214        LOCATION_W::new(self)
215    }
216    #[doc = "Writes raw bits to the register."]
217    #[inline(always)]
218    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
219        self.0.bits(bits);
220        self
221    }
222}
223#[doc = "I/O Routing Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [route](index.html) module"]
224pub struct ROUTE_SPEC;
225impl crate::RegisterSpec for ROUTE_SPEC {
226    type Ux = u32;
227}
228#[doc = "`read()` method returns [route::R](R) reader structure"]
229impl crate::Readable for ROUTE_SPEC {
230    type Reader = R;
231}
232#[doc = "`write(|w| ..)` method takes [route::W](W) writer structure"]
233impl crate::Writable for ROUTE_SPEC {
234    type Writer = W;
235    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
236    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
237}
238#[doc = "`reset()` method sets ROUTE to value 0"]
239impl crate::Resettable for ROUTE_SPEC {
240    const RESET_VALUE: Self::Ux = 0;
241}
efm32gg_pac/efm32gg230/usart0/route.rs

efm32gg_pac/efm32gg230/usart0/
route.rs
