efm32g800_pac/prs/
ch4_ctrl.rs

1#[doc = "Register `CH4_CTRL` reader"]
2pub struct R(crate::R<CH4_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH4_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH4_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH4_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH4_CTRL` writer"]
17pub struct W(crate::W<CH4_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH4_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH4_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH4_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SIGSEL` reader - Signal Select"]
38pub type SIGSEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `SIGSEL` writer - Signal Select"]
40pub type SIGSEL_W<'a> = crate::FieldWriter<'a, u32, CH4_CTRL_SPEC, u8, u8, 3, 0>;
41#[doc = "Source Select\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq)]
43#[repr(u8)]
44pub enum SOURCESEL_A {
45    #[doc = "0: No source selected"]
46    NONE = 0,
47    #[doc = "1: Voltage Comparator"]
48    VCMP = 1,
49    #[doc = "2: Analog Comparator 0"]
50    ACMP0 = 2,
51    #[doc = "3: Analog Comparator 1"]
52    ACMP1 = 3,
53    #[doc = "6: Digital to Analog Converter 0"]
54    DAC0 = 6,
55    #[doc = "8: Analog to Digital Converter 0"]
56    ADC0 = 8,
57    #[doc = "16: Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
58    USART0 = 16,
59    #[doc = "17: Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
60    USART1 = 17,
61    #[doc = "18: Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
62    USART2 = 18,
63    #[doc = "28: Timer 0"]
64    TIMER0 = 28,
65    #[doc = "29: Timer 1"]
66    TIMER1 = 29,
67    #[doc = "30: Timer 2"]
68    TIMER2 = 30,
69    #[doc = "40: Real-Time Counter"]
70    RTC = 40,
71    #[doc = "41: Universal Asynchronous Receiver/Transmitter 0"]
72    UART0 = 41,
73    #[doc = "48: General purpose Input/Output"]
74    GPIOL = 48,
75    #[doc = "49: General purpose Input/Output"]
76    GPIOH = 49,
77}
78impl From<SOURCESEL_A> for u8 {
79    #[inline(always)]
80    fn from(variant: SOURCESEL_A) -> Self {
81        variant as _
82    }
83}
84#[doc = "Field `SOURCESEL` reader - Source Select"]
85pub type SOURCESEL_R = crate::FieldReader<u8, SOURCESEL_A>;
86impl SOURCESEL_R {
87    #[doc = "Get enumerated values variant"]
88    #[inline(always)]
89    pub fn variant(&self) -> Option<SOURCESEL_A> {
90        match self.bits {
91            0 => Some(SOURCESEL_A::NONE),
92            1 => Some(SOURCESEL_A::VCMP),
93            2 => Some(SOURCESEL_A::ACMP0),
94            3 => Some(SOURCESEL_A::ACMP1),
95            6 => Some(SOURCESEL_A::DAC0),
96            8 => Some(SOURCESEL_A::ADC0),
97            16 => Some(SOURCESEL_A::USART0),
98            17 => Some(SOURCESEL_A::USART1),
99            18 => Some(SOURCESEL_A::USART2),
100            28 => Some(SOURCESEL_A::TIMER0),
101            29 => Some(SOURCESEL_A::TIMER1),
102            30 => Some(SOURCESEL_A::TIMER2),
103            40 => Some(SOURCESEL_A::RTC),
104            41 => Some(SOURCESEL_A::UART0),
105            48 => Some(SOURCESEL_A::GPIOL),
106            49 => Some(SOURCESEL_A::GPIOH),
107            _ => None,
108        }
109    }
110    #[doc = "Checks if the value of the field is `NONE`"]
111    #[inline(always)]
112    pub fn is_none(&self) -> bool {
113        *self == SOURCESEL_A::NONE
114    }
115    #[doc = "Checks if the value of the field is `VCMP`"]
116    #[inline(always)]
117    pub fn is_vcmp(&self) -> bool {
118        *self == SOURCESEL_A::VCMP
119    }
120    #[doc = "Checks if the value of the field is `ACMP0`"]
121    #[inline(always)]
122    pub fn is_acmp0(&self) -> bool {
123        *self == SOURCESEL_A::ACMP0
124    }
125    #[doc = "Checks if the value of the field is `ACMP1`"]
126    #[inline(always)]
127    pub fn is_acmp1(&self) -> bool {
128        *self == SOURCESEL_A::ACMP1
129    }
130    #[doc = "Checks if the value of the field is `DAC0`"]
131    #[inline(always)]
132    pub fn is_dac0(&self) -> bool {
133        *self == SOURCESEL_A::DAC0
134    }
135    #[doc = "Checks if the value of the field is `ADC0`"]
136    #[inline(always)]
137    pub fn is_adc0(&self) -> bool {
138        *self == SOURCESEL_A::ADC0
139    }
140    #[doc = "Checks if the value of the field is `USART0`"]
141    #[inline(always)]
142    pub fn is_usart0(&self) -> bool {
143        *self == SOURCESEL_A::USART0
144    }
145    #[doc = "Checks if the value of the field is `USART1`"]
146    #[inline(always)]
147    pub fn is_usart1(&self) -> bool {
148        *self == SOURCESEL_A::USART1
149    }
150    #[doc = "Checks if the value of the field is `USART2`"]
151    #[inline(always)]
152    pub fn is_usart2(&self) -> bool {
153        *self == SOURCESEL_A::USART2
154    }
155    #[doc = "Checks if the value of the field is `TIMER0`"]
156    #[inline(always)]
157    pub fn is_timer0(&self) -> bool {
158        *self == SOURCESEL_A::TIMER0
159    }
160    #[doc = "Checks if the value of the field is `TIMER1`"]
161    #[inline(always)]
162    pub fn is_timer1(&self) -> bool {
163        *self == SOURCESEL_A::TIMER1
164    }
165    #[doc = "Checks if the value of the field is `TIMER2`"]
166    #[inline(always)]
167    pub fn is_timer2(&self) -> bool {
168        *self == SOURCESEL_A::TIMER2
169    }
170    #[doc = "Checks if the value of the field is `RTC`"]
171    #[inline(always)]
172    pub fn is_rtc(&self) -> bool {
173        *self == SOURCESEL_A::RTC
174    }
175    #[doc = "Checks if the value of the field is `UART0`"]
176    #[inline(always)]
177    pub fn is_uart0(&self) -> bool {
178        *self == SOURCESEL_A::UART0
179    }
180    #[doc = "Checks if the value of the field is `GPIOL`"]
181    #[inline(always)]
182    pub fn is_gpiol(&self) -> bool {
183        *self == SOURCESEL_A::GPIOL
184    }
185    #[doc = "Checks if the value of the field is `GPIOH`"]
186    #[inline(always)]
187    pub fn is_gpioh(&self) -> bool {
188        *self == SOURCESEL_A::GPIOH
189    }
190}
191#[doc = "Field `SOURCESEL` writer - Source Select"]
192pub type SOURCESEL_W<'a> = crate::FieldWriter<'a, u32, CH4_CTRL_SPEC, u8, SOURCESEL_A, 6, 16>;
193impl<'a> SOURCESEL_W<'a> {
194    #[doc = "No source selected"]
195    #[inline(always)]
196    pub fn none(self) -> &'a mut W {
197        self.variant(SOURCESEL_A::NONE)
198    }
199    #[doc = "Voltage Comparator"]
200    #[inline(always)]
201    pub fn vcmp(self) -> &'a mut W {
202        self.variant(SOURCESEL_A::VCMP)
203    }
204    #[doc = "Analog Comparator 0"]
205    #[inline(always)]
206    pub fn acmp0(self) -> &'a mut W {
207        self.variant(SOURCESEL_A::ACMP0)
208    }
209    #[doc = "Analog Comparator 1"]
210    #[inline(always)]
211    pub fn acmp1(self) -> &'a mut W {
212        self.variant(SOURCESEL_A::ACMP1)
213    }
214    #[doc = "Digital to Analog Converter 0"]
215    #[inline(always)]
216    pub fn dac0(self) -> &'a mut W {
217        self.variant(SOURCESEL_A::DAC0)
218    }
219    #[doc = "Analog to Digital Converter 0"]
220    #[inline(always)]
221    pub fn adc0(self) -> &'a mut W {
222        self.variant(SOURCESEL_A::ADC0)
223    }
224    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 0"]
225    #[inline(always)]
226    pub fn usart0(self) -> &'a mut W {
227        self.variant(SOURCESEL_A::USART0)
228    }
229    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 1"]
230    #[inline(always)]
231    pub fn usart1(self) -> &'a mut W {
232        self.variant(SOURCESEL_A::USART1)
233    }
234    #[doc = "Universal Synchronous/Asynchronous Receiver/Transmitter 2"]
235    #[inline(always)]
236    pub fn usart2(self) -> &'a mut W {
237        self.variant(SOURCESEL_A::USART2)
238    }
239    #[doc = "Timer 0"]
240    #[inline(always)]
241    pub fn timer0(self) -> &'a mut W {
242        self.variant(SOURCESEL_A::TIMER0)
243    }
244    #[doc = "Timer 1"]
245    #[inline(always)]
246    pub fn timer1(self) -> &'a mut W {
247        self.variant(SOURCESEL_A::TIMER1)
248    }
249    #[doc = "Timer 2"]
250    #[inline(always)]
251    pub fn timer2(self) -> &'a mut W {
252        self.variant(SOURCESEL_A::TIMER2)
253    }
254    #[doc = "Real-Time Counter"]
255    #[inline(always)]
256    pub fn rtc(self) -> &'a mut W {
257        self.variant(SOURCESEL_A::RTC)
258    }
259    #[doc = "Universal Asynchronous Receiver/Transmitter 0"]
260    #[inline(always)]
261    pub fn uart0(self) -> &'a mut W {
262        self.variant(SOURCESEL_A::UART0)
263    }
264    #[doc = "General purpose Input/Output"]
265    #[inline(always)]
266    pub fn gpiol(self) -> &'a mut W {
267        self.variant(SOURCESEL_A::GPIOL)
268    }
269    #[doc = "General purpose Input/Output"]
270    #[inline(always)]
271    pub fn gpioh(self) -> &'a mut W {
272        self.variant(SOURCESEL_A::GPIOH)
273    }
274}
275#[doc = "Edge Detect Select\n\nValue on reset: 0"]
276#[derive(Clone, Copy, Debug, PartialEq)]
277#[repr(u8)]
278pub enum EDSEL_A {
279    #[doc = "0: Signal is left as it is"]
280    OFF = 0,
281    #[doc = "1: A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
282    POSEDGE = 1,
283    #[doc = "2: A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
284    NEGEDGE = 2,
285    #[doc = "3: A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
286    BOTHEDGES = 3,
287}
288impl From<EDSEL_A> for u8 {
289    #[inline(always)]
290    fn from(variant: EDSEL_A) -> Self {
291        variant as _
292    }
293}
294#[doc = "Field `EDSEL` reader - Edge Detect Select"]
295pub type EDSEL_R = crate::FieldReader<u8, EDSEL_A>;
296impl EDSEL_R {
297    #[doc = "Get enumerated values variant"]
298    #[inline(always)]
299    pub fn variant(&self) -> EDSEL_A {
300        match self.bits {
301            0 => EDSEL_A::OFF,
302            1 => EDSEL_A::POSEDGE,
303            2 => EDSEL_A::NEGEDGE,
304            3 => EDSEL_A::BOTHEDGES,
305            _ => unreachable!(),
306        }
307    }
308    #[doc = "Checks if the value of the field is `OFF`"]
309    #[inline(always)]
310    pub fn is_off(&self) -> bool {
311        *self == EDSEL_A::OFF
312    }
313    #[doc = "Checks if the value of the field is `POSEDGE`"]
314    #[inline(always)]
315    pub fn is_posedge(&self) -> bool {
316        *self == EDSEL_A::POSEDGE
317    }
318    #[doc = "Checks if the value of the field is `NEGEDGE`"]
319    #[inline(always)]
320    pub fn is_negedge(&self) -> bool {
321        *self == EDSEL_A::NEGEDGE
322    }
323    #[doc = "Checks if the value of the field is `BOTHEDGES`"]
324    #[inline(always)]
325    pub fn is_bothedges(&self) -> bool {
326        *self == EDSEL_A::BOTHEDGES
327    }
328}
329#[doc = "Field `EDSEL` writer - Edge Detect Select"]
330pub type EDSEL_W<'a> = crate::FieldWriterSafe<'a, u32, CH4_CTRL_SPEC, u8, EDSEL_A, 2, 24>;
331impl<'a> EDSEL_W<'a> {
332    #[doc = "Signal is left as it is"]
333    #[inline(always)]
334    pub fn off(self) -> &'a mut W {
335        self.variant(EDSEL_A::OFF)
336    }
337    #[doc = "A one HFPERCLK cycle pulse is generated for every positive edge of the incoming signal"]
338    #[inline(always)]
339    pub fn posedge(self) -> &'a mut W {
340        self.variant(EDSEL_A::POSEDGE)
341    }
342    #[doc = "A one HFPERCLK clock cycle pulse is generated for every negative edge of the incoming signal"]
343    #[inline(always)]
344    pub fn negedge(self) -> &'a mut W {
345        self.variant(EDSEL_A::NEGEDGE)
346    }
347    #[doc = "A one HFPERCLK clock cycle pulse is generated for every edge of the incoming signal"]
348    #[inline(always)]
349    pub fn bothedges(self) -> &'a mut W {
350        self.variant(EDSEL_A::BOTHEDGES)
351    }
352}
353impl R {
354    #[doc = "Bits 0:2 - Signal Select"]
355    #[inline(always)]
356    pub fn sigsel(&self) -> SIGSEL_R {
357        SIGSEL_R::new((self.bits & 7) as u8)
358    }
359    #[doc = "Bits 16:21 - Source Select"]
360    #[inline(always)]
361    pub fn sourcesel(&self) -> SOURCESEL_R {
362        SOURCESEL_R::new(((self.bits >> 16) & 0x3f) as u8)
363    }
364    #[doc = "Bits 24:25 - Edge Detect Select"]
365    #[inline(always)]
366    pub fn edsel(&self) -> EDSEL_R {
367        EDSEL_R::new(((self.bits >> 24) & 3) as u8)
368    }
369}
370impl W {
371    #[doc = "Bits 0:2 - Signal Select"]
372    #[inline(always)]
373    pub fn sigsel(&mut self) -> SIGSEL_W {
374        SIGSEL_W::new(self)
375    }
376    #[doc = "Bits 16:21 - Source Select"]
377    #[inline(always)]
378    pub fn sourcesel(&mut self) -> SOURCESEL_W {
379        SOURCESEL_W::new(self)
380    }
381    #[doc = "Bits 24:25 - Edge Detect Select"]
382    #[inline(always)]
383    pub fn edsel(&mut self) -> EDSEL_W {
384        EDSEL_W::new(self)
385    }
386    #[doc = "Writes raw bits to the register."]
387    #[inline(always)]
388    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
389        self.0.bits(bits);
390        self
391    }
392}
393#[doc = "Channel Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch4_ctrl](index.html) module"]
394pub struct CH4_CTRL_SPEC;
395impl crate::RegisterSpec for CH4_CTRL_SPEC {
396    type Ux = u32;
397}
398#[doc = "`read()` method returns [ch4_ctrl::R](R) reader structure"]
399impl crate::Readable for CH4_CTRL_SPEC {
400    type Reader = R;
401}
402#[doc = "`write(|w| ..)` method takes [ch4_ctrl::W](W) writer structure"]
403impl crate::Writable for CH4_CTRL_SPEC {
404    type Writer = W;
405}
406#[doc = "`reset()` method sets CH4_CTRL to value 0"]
407impl crate::Resettable for CH4_CTRL_SPEC {
408    #[inline(always)]
409    fn reset_value() -> Self::Ux {
410        0
411    }
412}
efm32g800_pac/prs/ch4_ctrl.rs

efm32g800_pac/prs/
ch4_ctrl.rs
